JP2011221099A - Substrate for electro-optic device, electro-optic device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a substrate for an electro-optic device which can reliably suppress the occurrence of display unevenness and uses low consumption energy by providing a storage capacitor having a sufficient capacitance value.SOLUTION: In a substrate 30 for an electro-optic device of the present invention, first and second TFTs 72, 73 include gate electrodes 74, 75 made of a first conductive film, a gate insulating film 83 made of a first insulating film, a semiconductor layer 76, and source and drain electrodes 77, 79 made of a second conductive film. A storage capacitor 71 is composed of the drain electrode 79 made of the second conductive film, a first passivation film 85A made of a second insulating film, and a storage-capacitor upper electrode 80 made of a third conductive film, which covers the drain electrode 79 with the first passivation film 85A interposed therebetween. A second passivation film 85B and a planarizing film 92 are formed to cover the first and second TFTs 72, 73, and a pixel electrode 35 is formed on the planarizing film 92.

Description

  The present invention relates to a substrate for an electro-optical device, an electro-optical device, and an electronic apparatus.

  2. Description of the Related Art As an electrophoretic display device which is a kind of electro-optical device, a configuration in which an electrophoretic element having a liquid phase dispersion medium and electrophoretic particles is sandwiched between a pair of substrates is known. Since this type of electrophoretic display device has a memory property, it is not always necessary to apply a voltage in order to maintain the display state, and it is sufficient if a voltage can be applied only for a period required to change the display state. However, the voltage must be held for a certain period in each pixel constituting the display, and each pixel needs to have a storage capacitor. Therefore, an electrophoretic display device having a storage capacity is disclosed in Patent Documents 1 and 2 listed below. According to Patent Documents 1 and 2, in these devices, the pixel voltage is sufficiently maintained by adding a storage capacitor in parallel with the electrophoretic element capacitor formed between the pixel electrode and the common electrode. It can be done.

Japanese Patent No. 4275671 JP 2005-346090 A

  The storage capacitors in the devices disclosed in Patent Documents 1 and 2 are the capacitor upper electrode formed in the same layer as the scanning line, the gate insulating film, and the capacitor upper portion formed in the same layer as the data line across the gate insulating film. And an electrode. When this configuration is adopted, since the scanning line and the capacitor lower electrode are arranged in the same layer, it is necessary to prevent a short circuit therebetween. However, in particular, when trying to increase the definition of pixels, the pixels cannot be enlarged unnecessarily. Therefore, if a large space for preventing a short circuit is provided, a storage capacitor having a sufficient capacitance value cannot be formed. Conversely, if the scanning line and the capacitor lower electrode are arranged with sufficient space to obtain a sufficient capacitance value, it is not possible to achieve high definition of the pixels.

  As other methods, there are attempts to increase the storage capacitance value by using a material having a high relative dielectric constant for the capacitor insulating film or by reducing the thickness of the capacitor insulating film. However, in these methods, since the capacitive insulating film is composed of a gate insulating film, the TFT characteristics are adversely affected, such as an increase in leakage current of a thin film transistor (hereinafter abbreviated as TFT). There is a risk.

  In addition, if the storage capacitance value is not sufficient, the feedthrough voltage when the TFT is turned off increases, and the variation in the feedthrough voltage due to the variation in the TFT capacitance becomes unacceptable. As a result, display unevenness particularly appears in the halftone display. This display unevenness is a problem peculiar to an electrophoretic display device which is a direct current display element, and is caused by a larger variation in feedthrough voltage than a liquid crystal display device having an effective value response.

  Further, if the storage capacity value is not sufficient, it is necessary to write the storage capacity over a plurality of frames in order to refresh the pixel voltage. However, the energy consumed in the electrophoretic display device (power x time) is mostly consumed for charging the parasitic capacitance of the data line, so that energy for charging the data line in the case of multiple frame driving. May be consumed wastefully, and there is a problem that power consumption increases.

  For example, in the device described in Patent Document 2, the gate insulating film, which is a capacitive insulating film, is thinned by etching. However, in this case, since the etching variation is added in addition to the gate insulating film deposition variation, the uniformity of the storage capacitance is lowered, and the problem of display unevenness due to the above-described variation in the feedthrough voltage occurs.

  As described above, the electrophoretic display device has been described as a prominent example. However, this type of problem is not limited to the electrophoretic display device. This is also a problem that applies to other electro-optical devices that drive optical materials.

  The present invention has been made in order to solve the above-described problem, and is provided with a storage capacitor having a sufficient capacitance value so that occurrence of display unevenness can be reliably suppressed, and an electro-optical device with low energy consumption. An object of the present invention is to provide a substrate and an electro-optical device used in the above. It is another object of the present invention to provide an electronic device provided with a display portion without display unevenness.

  In order to achieve the above object, an electro-optical device substrate according to the present invention includes a substrate body, a plurality of data lines and a plurality of scanning lines provided on the substrate body, and the data lines and the scanning lines. A plurality of divided pixels, and each of the plurality of pixels is a substrate for an electro-optical device including a pixel switching element, a pixel electrode, and a first storage capacitor, wherein the pixel switching element is A gate electrode made of a first conductive film formed on the substrate body, a gate insulating film made of a first insulating film formed so as to cover at least the gate electrode, and a semiconductor layer formed on the gate insulating film A source electrode made of a second conductive film electrically connected to the source region of the semiconductor layer and the data line, and a drain electrode of the semiconductor layer and the pixel electrode A drain electrode made of the second conductive film, and the first storage capacitor is formed to cover the first storage capacitor lower electrode made of the second conductive film and at least the first storage capacitor lower electrode. A first storage capacitor insulating film made of the second insulating film, and at least a part of the first storage capacitor lower electrode with the first storage capacitor insulating film in between when viewed from the normal direction of the substrate body A first storage capacitor upper electrode made of a third conductive film formed so as to overlap with the first storage capacitor, and a third insulating film is formed to cover at least a part of the pixel switching element and the first storage capacitor The pixel electrode is formed on the third insulating film.

  In the electro-optical device substrate of the present invention, the first storage capacitor includes a first storage capacitor lower electrode made of the second conductive film in the same layer as the source electrode and the drain electrode of the pixel switching element, and a second insulating film made of the second insulating film. The first storage capacitor insulating film and a first storage capacitor upper electrode made of a third conductive film formed on the second insulating film so as to at least partially overlap the first storage capacitor electrode. That is, the first storage capacitor in the present invention does not use a capacitor electrode or a gate insulating film formed in the same layer as the scanning line as described in the conventional patent documents 1 and 2, and is higher than these layers. It is configured using the side film.

  With this configuration, by appropriately setting the film thickness and relative dielectric constant of the first storage capacitor insulating film (second insulating film), the characteristics of the first storage capacitor are designed independently of the characteristics of the pixel switching element. be able to. That is, a storage capacitor having a sufficient capacitance value can be formed without being restricted by the characteristics of the pixel switching element. In addition, since the pixel potential in a period necessary for changing the display state can be reliably held, it is not necessary to write the storage capacitor a plurality of times, and energy consumption can be greatly reduced.

  Furthermore, in the electro-optical device substrate of the present invention, the third insulating film is formed so as to cover at least part of the pixel switching element and the first storage capacitor, and the pixel electrode is formed on the third insulating film. . In the configuration of the present invention, since the third insulating film is not a component of the storage capacitor, the film thickness can be increased regardless of the characteristics of the storage capacitor. The third insulating film covers the pixel switching element and the first storage capacitor, and the step reflecting the shape of the pixel switching element and the first storage capacitor is sufficiently filled by increasing the thickness of the third insulating film. The flatness of the entire substrate can be improved. As a result, when the electro-optical device substrate of the present invention is opposed to another substrate with the electro-optical material layer interposed therebetween, and the electro-optical device is manufactured, the adhesion between the electro-optical device substrate and the electro-optical material layer is improved. Alternatively, the adhesion between the electro-optical device substrate and another substrate can be improved, and a highly reliable electro-optical device can be realized.

  Further, by increasing the thickness of the third insulating film, the position of the pixel electrode (height from the substrate surface) can be separated (increased) from the position of the wiring such as the data line and the scanning line. And parasitic capacitance between wirings can be reduced. In addition, since the pixel electrode can be arranged above the wiring such as the data line and the scanning line, and the wiring can be electrically shielded by the pixel electrode, the leakage electric field from the wiring can be suppressed, and the display quality is suppressed by suppressing the fluctuation of the pixel potential. Can be increased.

  In the electro-optical device substrate of the present invention, each of the plurality of pixels has a second storage capacitor formed so that at least a part thereof overlaps the first storage capacitor when viewed from the normal direction of the substrate body. And the second storage capacitor comprises a second storage capacitor lower electrode made of the first conductive film and a second storage capacitor made of the first insulating film formed to cover at least the second storage capacitor lower electrode. When viewed from the normal direction of the substrate body, the capacitor insulating film is formed so that at least a portion thereof overlaps the second storage capacitor lower electrode with the second storage capacitor insulating film interposed therebetween, A configuration comprising a second storage capacitor upper electrode used also as the first storage capacitor as the storage capacitor lower electrode can be employed.

  According to this configuration, since the second storage capacitor is formed so that at least a part thereof overlaps the first storage capacitor when viewed from the normal direction of the substrate body, the first storage capacitor and the second storage capacitor are provided. By adding the capacitance, the capacitance value per unit area increases, and a sufficiently large storage capacitance value can be obtained without increasing the occupied area. In addition, since the first storage capacitor lower electrode and the second storage capacitor upper electrode are the same electrode and are used as both the first storage capacitor and the second storage capacitor, the first storage capacitor and the second storage capacitor are stacked. The structure is not complicated and the occupation area is not increased.

  In the electro-optical device substrate according to the present invention, as the first connection structure of the capacitor electrodes when the first storage capacitor and the second storage capacitor are stacked, the first storage capacitor lower electrode is electrically connected to the pixel electrode. The first storage capacitor upper electrode is electrically connected to the first capacitor line, and the second storage capacitor lower electrode is electrically connected to a second capacitor line different from the first capacitor line. Can be adopted.

  That is, in the configuration in which the first storage capacitor and the second storage capacitor are stacked, the second storage capacitor lower electrode / first storage capacitor lower electrode (also serving as the second storage capacitor upper electrode) / first storage capacitor from the substrate side. There are three layers of capacitive electrodes for the upper electrode. In the first connection structure, among the three layers of capacitive electrodes, the upper capacitive electrode and the lower capacitive electrode are electrically connected to different capacitive lines (first capacitive line, second capacitive line), respectively. The intermediate capacitance electrode is electrically connected to the pixel electrode. According to this configuration, since only one contact hole is required for electrically connecting the capacitor electrode and the pixel electrode, the area of the storage capacitor can be increased correspondingly, and a large capacitance value can be obtained.

  Alternatively, as a second connection structure of each capacitor electrode, the first storage capacitor upper electrode is electrically connected to the pixel electrode, and the second storage capacitor lower electrode is electrically connected to the pixel electrode. The first storage capacitor lower electrode can be electrically connected to the capacitor line.

  In the second connection structure, contrary to the first connection structure, among the three layers of capacitor electrodes, the upper-layer capacitor electrode and the lower-layer capacitor electrode are electrically connected to the pixel electrode, respectively, The capacitor electrode is electrically connected to the capacitor line. According to this configuration, two contact holes for electrically connecting the capacitor electrode and the pixel electrode are required, while only one capacitor line is required for one pixel, and the degree of freedom in wiring design Can be enhanced.

In the electro-optical device substrate according to the aspect of the invention, it is preferable that the thickness of the second insulating film is smaller than the thickness of the first insulating film.
According to this configuration, since the thickness of the gate insulating film made of the first insulating film can be relatively increased, leakage current of the TFT constituting the pixel switching element can be prevented and TFT characteristics can be improved. Further, since the film thickness of the first storage capacitor insulating film made of the second insulating film can be relatively reduced, the storage capacitor can be increased.

In the electro-optical device substrate of the present invention, a part of the source electrode and a part of the drain electrode are formed on the semiconductor layer, and the source electrode is electrically connected to the source region of the semiconductor layer. And the drain electrode is electrically connected to the drain region of the semiconductor layer.
According to this configuration, a so-called top contact TFT having a structure in which the source electrode and the drain electrode are in contact with the upper surface of the semiconductor layer can be realized as the pixel switching element.

In the case of the above configuration, it is desirable that an etching stop layer is provided in a region above the channel region of the semiconductor layer.
According to this configuration, when a TFT having a top contact structure is employed as the pixel switching element, the channel region of the semiconductor layer is protected from etching damage by the etching stop layer, so that a TFT having excellent characteristics can be formed.

In the substrate for an electro-optical device according to the aspect of the invention, a part of the semiconductor layer is formed on the source electrode and the drain electrode, and the source electrode is electrically connected to the source region of the semiconductor layer. In addition to being connected, the drain electrode can be electrically connected to the drain region of the semiconductor layer.
According to this configuration, a TFT with a so-called bottom contact structure in which the source electrode and the drain electrode are in contact with the lower surface side of the semiconductor layer can be realized as the pixel switching element. In this case, because of the manufacturing process of patterning the source electrode and the drain electrode before forming the semiconductor layer, the semiconductor layer is not damaged by etching, and a TFT having excellent characteristics can be formed.

In the electro-optical device substrate of the present invention, any of non-single-crystal silicon, an oxide semiconductor material, a transparent oxide semiconductor material, and an organic semiconductor material can be used as the semiconductor layer.
According to this configuration, a TFT having excellent electrical characteristics can be manufactured relatively easily using an existing manufacturing process.

The electro-optical device of the present invention includes a pair of substrates and an electro-optical material layer sandwiched between the pair of substrates, and one of the pair of substrates is the electro-optical device of the present invention. It is a device substrate.
According to this configuration, since the electro-optical device substrate of the present invention is used as one of the pair of substrates, variations in feedthrough voltage can be suppressed, and an electro-optical device with less display unevenness can be realized. .

An electronic apparatus according to the present invention includes the electro-optical device according to the present invention.
According to the present invention, since the electro-optical display device of the present invention is provided, an electronic apparatus including a display unit with little display unevenness can be realized.

1 is an equivalent circuit diagram illustrating an electrophoretic display device according to a first embodiment of the present invention. 2 is an equivalent circuit diagram of each pixel in the electrophoretic display device. FIG. 2A is a cross-sectional view of an electrophoretic display device, FIG. 2B is a cross-sectional view of a microcapsule, and FIG. 2C is a view for explaining an operation of the electrophoretic element. 2 is a plan view showing the overall configuration of the electrophoretic display device. FIG. It is a figure which shows the planar pattern of each pixel of the element substrate of an electrophoretic display device similarly. It is sectional drawing which follows the A-A 'line of FIG. It is a figure which shows a feedthrough voltage. It is a figure which shows a common electric potential. It is a figure which shows the planar pattern of each pixel of the element substrate in the electrophoretic display device of 2nd Embodiment of this invention. It is sectional drawing which follows the A-A 'line of FIG. 2 is an equivalent circuit diagram of each pixel of the electrophoretic display device. FIG. It is a figure which shows the planar pattern of each pixel of the element substrate in the electrophoretic display device of 3rd Embodiment of this invention. It is sectional drawing which follows the A-A 'line of FIG. 2 is an equivalent circuit diagram of each pixel of the electrophoretic display device. FIG. It is sectional drawing of each pixel of the element substrate in the electrophoretic display device of 4th Embodiment of this invention. It is sectional drawing of each pixel of the element substrate in the electrophoretic display device of the fifth embodiment of the present invention. It is a figure which shows one Embodiment of the electronic device of this invention. It is a figure which shows other embodiment of the electronic device of this invention. It is a figure which shows other embodiment of the electronic device of this invention.

[First Embodiment]
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
The electro-optical device of this embodiment is an example of an active matrix type electrophoretic display device.
FIG. 1 is an equivalent circuit diagram showing an electrophoretic display device of this embodiment. FIG. 2 is an equivalent circuit diagram of each pixel of the electrophoretic display device. 3A is a cross-sectional view of the electrophoretic display device, FIG. 3B is a cross-sectional view of the microcapsule, and FIG. 3C is a view for explaining the operation of the electrophoretic element. FIG. 4 is a plan view showing the overall configuration of the electrophoretic display device. FIG. 5 is a diagram showing a planar pattern of each pixel of the element substrate of the electrophoretic display device. 6 is a cross-sectional view taken along the line AA ′ of FIG. FIG. 7 is a diagram showing the feedthrough voltage. FIG. 8 is a diagram showing a common potential.
In the following drawings, in order to make each component easy to see, the scale of the size may be varied depending on the component.

  As shown in FIG. 1, the electrophoretic display device 100 of the present embodiment includes a display unit 5 in which a plurality of pixels 40 are arranged in a matrix. Around the display unit 5, a scanning line driving circuit 61, a data line driving circuit 62, a controller (control unit) 63, and a capacitor line driving circuit 64 are arranged. The scanning line driving circuit 61, the data line driving circuit 62, and the capacitor line driving circuit 64 are each connected to the controller 63. The controller 63 comprehensively controls these based on image data and synchronization signals supplied from the host device.

  In the display unit 5, a plurality of scanning lines 66 extending from the scanning line driving circuit 61 and a plurality of data lines 68 extending from the data line driving circuit 62 are formed, and the pixels 40 correspond to these intersecting positions. Is provided. Further, a capacitor line 67 extending from the capacitor line driving circuit 64 is provided in parallel with the data line 68, and the scanning line 66, the data line 68, and the capacitor line 67 are connected to the pixel 40, respectively.

  The scanning line driving circuit 61 is connected to each pixel 40 via m scanning lines 66 (Y1, Y2,..., Ym). Under the control of the controller 63, the first to mth rows are connected. A selection signal defining the timing at which the scanning lines 66 up to the eyes are sequentially selected and a selection transistor 41 (pixel switching element, see FIG. 2) provided in the pixel 40 is turned on is selected via the selected scanning line 66. Supply. The data line driving circuit 62 is connected to each pixel 40 via n data lines 68 (X1, X2,..., Xn), and corresponds to each pixel 40 under the control of the controller 63. An image signal defining pixel data to be supplied is supplied to the pixel 40. The capacitor line driving circuit 64 supplies a predetermined potential to the capacitor line 67 under the control of the controller 63.

As shown in FIG. 2, each pixel 40 is provided with a selection transistor 41, a storage capacitor 71, a pixel electrode 35, an electrophoretic element 32, and a common electrode 37. As the pixel circuit of the present embodiment, a so-called 1T1C (1Transistor, 1Capacitor) type pixel circuit is employed, which includes one transistor and one storage capacitor. A double gate type transistor in which TFTs are connected in series is used. With this configuration, the voltage applied to the selection transistor is distributed by the two TFTs, and a sufficient breakdown voltage of each TFT can be secured.
The storage capacity in the present embodiment corresponds to the “first storage capacity” in the claims.

As described above, the scanning line 66, the data line 68, and the capacitor line 67 are connected to each pixel 40. The gate of the first TFT 72 and the gate of the second TFT 73 constituting the selection transistor 41 are connected to the scanning line 66, the source of the first TFT 72 is connected to the data line 68, and the drain of the first TFT 72 and the source of the second TFT 73 are connected to each other. The drain of the second TFT 73 is connected to the pixel electrode 35 and one electrode of the storage capacitor 71. The other electrode of the storage capacitor 71 is connected to the capacitor line 67.
In the description of this embodiment, of the sources and drains of the TFTs 72 and 73, the side connected to the data line 68 (side close to the data line 68) is the source and the side connected to the pixel electrode 35 (pixel electrode) The side close to 35) is called a drain, but this is simply determined in this way for convenience, and the names of the sources and drains of the TFTs 72 and 73 may be reversed.

  In the case of this embodiment, it is assumed that an n-channel transistor is used as the selection transistor 41, but it may be replaced with another type of switching element having a function equivalent to that of the n-channel transistor. For example, a p-channel transistor may be used instead of an n-channel transistor, and an inverter or a transmission gate may be used.

  In each pixel 40, when the selection transistor 41 is turned on by a selection signal input via the scanning line 66, an image signal is input from the data line 68 to the pixel electrode 35 via the selection transistor 41, and the storage capacitor 71 is charged. The pixel electrode 35 is held at a predetermined potential level by the energy stored in the storage capacitor 71, and the electrophoretic element 32 is driven by the potential difference between the pixel electrode 35 and the common electrode 37.

  As shown in FIG. 3A, the electrophoretic display device 100 includes a configuration in which an electrophoretic element 32 in which a plurality of microcapsules 20 are arranged is sandwiched between an element substrate 30 and a counter substrate 31. Yes. In the display unit 5, the circuit layer 34 on which the scanning lines 66, the data lines 68, the selection transistors 41, and the like illustrated in FIGS. 1 and 2 are formed is provided on the electrophoretic element 32 side of the element substrate 30. A plurality of pixel electrodes 35 are arranged on the circuit layer 34. In FIG. 3A, illustration of specific components inside the circuit layer 34 is omitted.

  The element substrate 30 (electro-optical device substrate) is a substrate made of glass, plastic, or the like, and is disposed on the side opposite to the image display surface, and thus may not be transparent. The pixel electrode 35 is formed of a transparent conductive material such as ITO (indium tin oxide) or a metal material such as Al, and applies a voltage to the electrophoretic element 32 between the pixel electrode 35 and the common electrode 37. Electrode.

On the other hand, a planar common electrode 37 facing the plurality of pixel electrodes 35 is formed on the electrophoretic element 32 side of the counter substrate 31, and the electrophoretic element 32 is provided on the common electrode 37. The counter substrate 31 is a substrate made of glass, plastic, or the like, and is disposed on the image display side. Therefore, a transparent substrate is used. The common electrode 37 is an electrode for applying a voltage to the electrophoretic element 32 together with the pixel electrode 35, and is a transparent electrode formed of MgAg (magnesium silver), ITO, IZO (indium / zinc oxide) or the like.
The electrophoretic element 32 and the pixel electrode 35 are bonded via the adhesive layer 33, so that the element substrate 30 and the counter substrate 31 are bonded.

  The electrophoretic element 32 is generally formed in advance on the counter substrate 31 side and is handled as an electrophoretic sheet including the adhesive layer 33. In the manufacturing process, the electrophoretic sheet is handled in a state where a protective release sheet is attached to the surface of the adhesive layer 33. And the display part 5 is formed by sticking the said electrophoretic sheet which peeled the release sheet with respect to the element board | substrate 30 (The pixel electrode 35, various circuits, etc.) which were manufactured separately. For this reason, the adhesive layer 33 exists only on the pixel electrode 35 side.

  As shown in FIG. 3B, the microcapsule 20 has a particle size of, for example, about 50 μm, and includes a dispersion medium 21, a plurality of white particles (electrophoretic particles) 27, and a plurality of black particles. (Electrophoretic particles) 26 are encapsulated spherical bodies. As shown in FIG. 3A, the microcapsule 20 is sandwiched between the common electrode 37 and the pixel electrode 35, and one or a plurality of microcapsules 20 are arranged in one pixel 40.

The outer shell portion (wall film) of the microcapsule 20 is formed using a translucent polymer resin such as an acrylic resin such as polymethyl methacrylate or polyethyl methacrylate, a urea resin, or gum arabic. .
The dispersion medium 21 is a liquid that disperses the white particles 27 and the black particles 26 in the microcapsules 20.

  Examples of the dispersion medium 21 include water, alcohol solvents (methanol, ethanol, isopropanol, butanol, octanol, methyl cellosolve, etc.), esters (ethyl acetate, butyl acetate, etc.), ketones (acetone, methyl ethyl ketone, methyl isobutyl ketone, etc.). ), Aliphatic hydrocarbons (pentane, hexane, octane, etc.), alicyclic hydrocarbons (cyclohexane, methylcyclohexane, etc.), aromatic hydrocarbons (benzene, toluene, benzenes having a long-chain alkyl group ( Xylene, hexylbenzene, hebutylbenzene, octylbenzene, nonylbenzene, decylbenzene, undecylbenzene, dodecylbenzene, tridecylbenzene, tetradecylbenzene)), halogenated hydrocarbons (methylene chloride, chloroform, tetrachloride) Element, and 1,2-dichloroethane), can be exemplified a carboxylate, it may be other oils. These substances can be used alone or as a mixture, and a surfactant or the like may be further blended.

  The white particles 27 are particles (polymer or colloid) made of a white pigment such as titanium dioxide, zinc white, and antimony trioxide, and are used, for example, by being negatively charged. The black particles 26 are particles (polymer or colloid) made of a black pigment such as aniline black or carbon black, and are used by being charged positively, for example.

If necessary, these pigments include electrolytes, surfactants, metal soaps, resins, rubbers, oils, varnishes, compound charge control agents, titanium-based coupling agents, aluminum-based coupling agents, A dispersant such as a silane coupling agent, a lubricant, a stabilizer, and the like can be added.
Further, instead of the black particles 26 and the white particles 27, for example, pigments such as red, green, blue, yellow, cyan, and magenta may be used. According to such a configuration, red, green, blue, yellow, cyan, magenta, and the like can be displayed on the display unit 5.

  In the electrophoretic element 32 configured as described above, when the pixel 40 is displayed in black, as shown in FIG. 3C, the common electrode 37 is held at a relatively low potential and the pixel electrode 35 is held at a relatively high potential. . That is, when the potential of the common electrode 37 is set as a reference potential, the pixel electrode 35 is held positive. As a result, the positively charged black particles 26 are attracted to the common electrode 37, while the negatively charged white particles 27 are attracted to the pixel electrode 35. As a result, when this pixel is viewed from the common electrode 37 side, black is visually recognized. On the other hand, when the pixel 40 is displayed in white, the common electrode 37 is held at a relatively high potential, the pixel electrode 35 is held at a relatively low potential, and the pixel electrode 35 is made negative with respect to the potential of the common electrode 37. To do. Thereby, the negatively charged white particles 27 are attracted to the common electrode 37 side, and white is visually recognized when viewed from the display surface side.

FIG. 4 shows two examples of the overall configuration of the electrophoretic display device 100.
In the example shown in FIG. 4A, the element substrate 30 has a larger planar dimension than the counter substrate 31 that is an electrophoretic sheet, and two scans are performed on the element substrate 30 protruding outward from the counter substrate 31. The line drive circuit 61 and the two data line drive circuits 62 are mounted on COG (Chip On Glass). In addition, a terminal formation region 110 is provided in the edge portion in the vicinity of the data line driving circuit 62, and a flexible substrate 201 for connecting to an external device is provided in the terminal formation region 110 with an ACP (anisotropic conductive paste). It is bonded via ACF (anisotropic conductive film).

  In the example shown in FIG. 4A, the display unit 5 is formed in a region where the element substrate 30 and the counter substrate 31 overlap, and the scanning lines 66 and the data lines 68 extending from the display unit 5 are included in the scanning line driving circuit 61. The data line driving circuit 62 is extended to a region where the data line driving circuit 62 is mounted, and is connected to a connection terminal formed in the mounting region. A scanning line driving circuit 61 and a data line driving circuit 62 are mounted on the connection terminals via ACPs and ACFs.

  On the other hand, in the example shown in FIG. 4B, the scanning line driving circuit 61 and the data line driving circuit 62 are not mounted on the element substrate 30 and are mounted on the flexible substrates 202 and 203 by COF (Chip On Film) ( Or TAB (Tape Automated Bonding) mounting). Then, the flexible substrate 202 on which the scanning line driving circuit 61 is mounted is mounted on the terminal formation region 120 formed on the edge portion along one short side of the element substrate 30 via the ACP or the like. In addition, the flexible substrate 203 on which the data line driving circuit 62 is mounted is mounted on the terminal formation region 130 formed on the edge portion along one long side of the element substrate 30 via the ACP or the like. A plurality of connection terminals are formed in each of the terminal formation regions 120 and 130, and a scanning line 66 and a data line 68 extending from the display unit 5 are connected to each connection terminal. Further, the flexible substrate 203 on which the data line driving circuit 62 is mounted is also connected to the rigid substrate 204, and the flexible substrate 205 for external connection is connected to the rigid substrate 204.

Next, the configuration of the element substrate 30 (electro-optical device substrate) which is the essence of the present invention will be described.
In the element substrate 30, as shown in the plane pattern of FIG. 5, the data lines 68 extending in the vertical direction of FIG. 5 and the scanning lines 66 extending in the horizontal direction of FIG. One pixel 40 is a region partitioned by the two data lines 68 and two adjacent scanning lines 66. A selection transistor 41 including two TFTs, a first TFT 72 and a second TFT 73, is provided at one corner of the rectangular pixel 40, and a rectangular pixel electrode 35 is provided so as to overlap the selection transistor 41 in a plan view. .

  The gate electrodes 74 and 75 of the first TFT 72 and the second TFT 73 are respectively formed branched from the scanning line 66, and the semiconductor layer 76 is formed so as to straddle the gate electrode 74 of the first TFT 72 and the gate electrode 75 of the second TFT 73. Yes. A source electrode 77 of the first TFT 72 is formed so as to branch from the data line 68 and partially overlap the gate electrode 74 of the first TFT 72. An electrode 78 serving as both the drain electrode of the first TFT 72 and the source electrode of the second TFT 73 so as to partially overlap the gate electrode 74 of the first TFT 72 and the gate electrode 75 of the second TFT 73 (this electrode will be referred to as source / source A drain electrode 78). A drain electrode 79 of the second TFT 73 is formed so as to partially overlap the gate electrode 75 of the second TFT 73. The drain electrode 79 is formed large in a region that does not overlap with the selection transistor 41 in the pixel 40.

  That is, when the first TFT 72 and the second TFT 73 are considered as one selection transistor 41, the source electrode 77 of the first TFT 72 branched from the data line 68 corresponds to the source electrode of the selection transistor 41, and 2 of the first and second TFTs 72 and 73. The two gate electrodes 74 and 75 correspond to the gate electrode of the double gate type selection transistor 41, and the drain electrode 79 of the second TFT 73 corresponds to the drain electrode of the selection transistor 41.

Capacitor lines 67 are arranged substantially parallel to the data lines 68 so as to extend in the vertical direction of FIG. 5. In each pixel 40, a storage capacitor upper electrode 80 (first storage capacitor upper electrode) is provided as a drain electrode. 79 and the pixel electrode 35 are formed integrally with the capacitor line 67 so as to partially overlap. The portion where the storage capacitor upper electrode 80 overlaps the drain electrode 79 in a plane becomes the storage capacitor 71 of each pixel 40. That is, a portion of the drain electrode 79 that overlaps the storage capacitor upper electrode 80 in a plane functions as a storage capacitor lower electrode (first storage capacitor lower electrode) of the storage capacitor 71. Further, a contact hole 81 for electrically connecting the drain electrode 79 and the pixel electrode 35 is formed at an overlapping portion of the drain electrode 79 and the pixel electrode 35 (the storage capacitor upper electrode 80 does not overlap). Reference numeral 92A denotes an opening of a planarizing film 92 described later.
The “storage capacitor upper electrode” in the present embodiment corresponds to the “first storage capacitor upper electrode” in the claims.

FIG. 6 shows a cross-sectional structure of the first TFT 72, the second TFT 73, and the storage capacitor 71 described above. Further, the left side of the omitted portion in FIG. 6 shows the cross-sectional structure of the pixel 40, and the right side shows the cross-sectional structure of a part of the peripheral circuit portion 86 (protection circuit portion).
As shown in FIG. 6, on the surface of the substrate body 82 constituting the element substrate 30 on the side where the electrophoretic element 32 is disposed, the selection transistor 41 including the first TFT 72 and the second TFT 73, the pixel electrode 35, and the storage capacitor upper electrode. 80, a scanning line 66, a data line 68, and the like are formed.

  Gate electrodes 74 and 75 made of a first conductive film are formed on the substrate body 82. Although not shown in FIG. 6, the scanning line 66 integrated with the gate electrodes 74 and 75 is also formed on the substrate body 82. The substrate main body 82 is a substrate made of glass, plastic, or the like, and is disposed on the side opposite to the image display surface. In particular, when an organic TFT having an organic semiconductor layer is used as the selection transistor 41, it is desirable to use a plastic substrate that is inexpensive, lightweight, and excellent in flexibility. Further, as a material of the first conductive film constituting the gate electrodes 74 and 75 and the scanning line 66, for example, a metal laminated film of Al—Nd alloy and Mo can be used. In addition, Al alone, ITO, Cu, Cr, Ta, Mo, Nb, Ag, Pt, Pd, In, Nd, and alloys thereof can be used.

  A gate insulating film 83 made of a first insulating film is formed on the entire surface of the substrate body 82 so as to cover the gate electrodes 74 and 75. As a material of the first insulating film constituting the gate insulating film 83, for example, a silicon nitride film having a thickness of 400 nm can be used. As other materials, inorganic insulating materials such as silicon oxide films and silicon oxynitride films, and organic insulating materials can be used.

  A semiconductor layer 76 is formed on the upper surface of the gate insulating film 83 above the gate electrodes 74 and 75. Examples of the material of the semiconductor layer 76 include non-single-crystal silicon materials such as amorphous silicon and polycrystalline silicon, oxide semiconductor materials, transparent oxide semiconductor materials such as In—Ga—Zn—O, and fluorene-bithiophene copolymers. Organic semiconductor materials, etc. can be used. In this embodiment, an In—Ga—Zn—O film is used. Note that in the case where an oxide semiconductor material is used for the semiconductor layer 76, an oxide insulating material is preferably used for the gate insulating film 83 (first insulating film), and in the case where an organic semiconductor material is used for the semiconductor layer 76, a gate is used. It is desirable to use an organic insulating material also for the insulating film 83 (first insulating film). Further, an etching stop layer 91 made of a silicon nitride film having a thickness of 200 nm is formed in a region above the channel region of the semiconductor layer 76.

  On the gate insulating film 83, a source electrode 77, a source / drain electrode 78, and a drain electrode 79 made of the second conductive film are formed so as to partially run over the upper surface of the semiconductor layer 76 and the upper surface of the etching stopper layer 91. Yes. The source electrode 77, the source / drain electrode 78, and the drain electrode 79 are electrically connected to the source region and the drain region of each of the TFTs 72 and 73 by making direct contact with the semiconductor layer 76. That is, as the first TFT 72 and the second TFT 73 of this embodiment, so-called bottom gate / top contact type TFTs are employed.

On the gate insulating film 83 on the side of the second TFT 73, the end of the drain electrode 79 extends long, and a portion that functions as a storage capacitor lower electrode is formed. As a material of the second conductive film constituting the source electrode 77, the source / drain electrode 78, and the drain electrode 79, for example, a metal laminated film such as Mo / Al / Mo can be used. In addition, the same material as the first conductive film constituting the gate electrodes 74 and 75 can be used.
The “storage capacitor lower electrode” in this embodiment corresponds to the “first storage capacitor lower electrode” in the claims.

A first protective film 85A made of a second insulating film is formed on the entire surface of the gate insulating film 83 so as to cover the source electrode 77, the source / drain electrode 78, and the drain electrode 79. The first protective film 85A is basically a film for insulating and protecting the TFTs 72 and 73. In this embodiment, the storage capacitor upper electrode 80 and the drain electrode 79 sandwich the first protective film 85A. The opposing portion functions as a storage capacitor insulating film of the storage capacitor 71. As a material of the second insulating film constituting the first protective film 85A, for example, a silicon nitride film having a film thickness of 150 nm can be used. Therefore, in the present embodiment, the thickness of the first protective film 85A is set to be smaller than the thickness of the gate insulating film 83. Further, as the other material of the first protective film 85A, an insulating material similar to the gate insulating film 83 (first insulating film) such as an inorganic insulating material such as a silicon oxide film can be used. Alternatively, an organic insulating material such as an acrylic resin may be used.
The “storage capacitor insulating film” in the present embodiment corresponds to the “first storage capacitor insulating film” in the claims.

  On the first protective film 85A, a storage capacitor upper electrode 80 made of a third conductive film is formed in a region facing the drain electrode 79 across the first protective film 85A. As a material of the third conductive film constituting the storage capacitor upper electrode 80, for example, a metal laminated film such as Mo / Al / Mo can be used similarly to the second conductive film constituting the source electrode 77 and the like. In addition, the same material as the first conductive film constituting the gate electrodes 74 and 75 can be used. Although not shown in FIG. 6, a capacitor line 67 integrated with the storage capacitor upper electrode 80 is also formed on the first protective film 85A.

  A second protective film 85B is formed so as to cover the first TFT 72, the second TFT 73, and the storage capacitor upper electrode 80 (capacitor line 67). The same material as that of the first protective film 85A can be used for the second protective film 85B. However, since the second protective film 85B does not function as a storage capacitor insulating film, the material and film thickness may be appropriately determined from the function as the protective film. A planarizing film 92 made of an organic insulating material such as acrylic resin is formed on the entire surface of the substrate covering the second protective film 85B. The planarizing film 92 is a film for planarizing the substrate by filling the steps reflecting the shapes of the first TFT 72, the second TFT 73, the storage capacitor 71, etc., and has a film thickness (for example, several μm) necessary for planarization. ).

  A contact hole 81 that reaches the drain electrode 79 through the planarizing film 92, the second protective film 85B, and the first protective film 85A is formed, and the pixel electrode 35 is formed on the planarizing film 92 including the inside of the contact hole 81. Is formed. With this configuration, the drain electrode 79 and the pixel electrode 35 are electrically connected via the contact hole 81. As a material of the pixel electrode 35, for example, a transparent conductive material such as ITO can be used. Alternatively, since the pixel electrode 35 is located on the opposite side to the viewing side with respect to the electrophoretic element 32, it may not be a transparent material, and a metal material such as Al may be used. Moreover, you may use these laminated films.

  On the right side of FIG. 6, a protection circuit unit is illustrated as an example of the peripheral circuit unit 86. The protection circuit section includes a first electrode 87 made of the first conductive film in the same layer as the gate electrodes 74 and 75, a second electrode 88 made of the second conductive film in the same layer as the source electrode 77 and the like, and the first electrode 87. And a short-circuit wiring 89 that electrically short-circuits the second electrode 88.

Hereinafter, a manufacturing process of the element substrate having the above configuration will be described.
First, a first conductive film made of a metal laminate film of Al—Nd with a thickness of 150 nm and Mo with a thickness of 20 nm is formed on one surface of a substrate body 82 such as glass or plastic by sputtering.
Next, the first conductive film is patterned by photolithography and etching to form the scanning lines 66 and the gate electrodes 74 and 75.

Next, a 400-nm-thick silicon nitride film (first insulating film) to be the gate insulating film 83, an In—Ga—Zn—O film to be the semiconductor layer 76, and a 200-nm-thick silicon nitride film to be the etching stop layer 91 Three layers are formed. For the In—Ga—Zn—O film, an amorphous In—Ga—Zn—O film with a composition ratio of In: Ga: Zn = 1: 1: 1 is formed by a sputtering method using an InGaZnO ₄ target.
Next, the silicon nitride film is patterned by a photolithography method or a wet etching method using an etchant containing hydrofluoric acid to form an etching stop layer 91. Here, a silicon nitride film is used as the material of the etching stop layer 91. However, instead of this, a silicon oxide film may be used, or a laminated film formed by laminating a silicon oxide film / silicon nitride film is used. Also good.

Next, the In—Ga—Zn—O film is patterned by a photolithography method and an etching method, so that the semiconductor layer 76 is formed.
Next, for example, a conductive film such as Mo / Al / Mo is formed, and the conductive film is patterned by a photolithography method and an etching method to form a source electrode 77, a source / drain electrode 78, and a drain electrode 79.
Next, a silicon nitride film having a thickness of 150 nm is formed as a first protective film 85A (second insulating film) by plasma CVD.

Next, for example, a third conductive film such as Mo / Al / Mo is formed, and the third conductive film is patterned by a photolithography method and an etching method, thereby forming the storage capacitor upper electrode 80 and the capacitor line 67.
Next, a silicon nitride film to be the second protective film 85B is formed by plasma CVD.
Next, a photosensitive acrylic resin is applied and exposed to form a planarizing film 92, and a portion of the contact hole 81 that is deep enough to expose the second protective film 85B is formed. Further, the second protective film 85B and the first protective film 85A are selectively removed by a photolithography method and an etching method, and a contact hole 81 reaching the surface of the drain electrode 79 is formed.

Finally, a transparent conductive film made of ITO having a thickness of 100 nm is formed by sputtering.
Next, the transparent conductive film is patterned by a photolithography method or a wet etching method to form the pixel electrode 35.
The element substrate 30 of this embodiment is completed through the above steps.

  In the present embodiment, the storage capacitor 71 does not use a capacitor electrode or a gate insulating film formed in the same layer as the scanning line as described in the conventional patent documents 1 and 2, and is higher than these. That is, the storage capacitor lower electrode 80 formed of a part of the drain electrode 79, the first protective film 85A, and the storage capacitor upper electrode 80 are formed. Accordingly, by appropriately setting the film thickness and relative dielectric constant of the first protective film 85A, the characteristics of the storage capacitor 71 can be designed independently of the characteristics of the selection transistor 41 including the first TFT 72 and the second TFT 73. it can. That is, the storage capacitor 71 having a sufficient capacitance value can be formed without being restricted by the characteristics of the selection transistor 41. As a result, it is possible to realize an electrophoretic display device in which variations in feedthrough voltage are suppressed and display unevenness is small.

Here, the feedthrough voltage will be described with reference to FIGS.
The TFT has a parasitic capacitance due to the structure. In FIG. 2, the broken line capacitor symbol represents the parasitic capacitance, which is formed in the channel region when the gate-drain parasitic capacitance Cgd formed at the overlapping portion of the gate electrode and the drain electrode and the TFT is in the on state. This corresponds to about half of the capacity to be used. At this time, if the storage capacitance is Cst, the electrophoretic element capacitance is Cepd, the gate voltage high level is Vgh, and the low level is Vgl, the feedthrough voltage ΔVg is the gate-drain parasitic capacitance Cgd and the pixel capacitance Cpix (= Cgd + Cst + Cepd). ) And the ratio are expressed as follows.
ΔVg = (Cgd / Cpix) × (Vgh−Vgl)
= (Cgd / (Cgd + Cst + Cepd)) × (Vgh−Vgl) (1)

Further, the pixel effective voltage VPIX-VCOM when the feedthrough voltage ΔVg varies by ΔV due to manufacturing variations such as processing variations can be expressed as shown in FIG.
When the pixel effective voltage is expressed by a mathematical formula, the following formulas (2) and (3) are obtained, respectively, in the case of an AC drive liquid crystal display device and in the case of a DC drive electrophoretic display device.

  As apparent from the equations (2) and (3), in the case of the liquid crystal display device, there is almost no influence on the pixel effective voltage when the feedthrough voltage variation ΔV is ΔV <1. On the other hand, in the case of an electrophoretic display device, ± ΔV directly affects the variation in pixel effective voltage, and is recognized as display unevenness particularly in the case of halftone display. Therefore, in order to improve display uniformity, it is important to reduce the feedthrough voltage variation ΔV.

In order to reduce the feedthrough voltage variation ΔV, it is effective not only to suppress the variation of the gate-drain parasitic capacitance Cgd due to the manufacturing variation and the like, but also to increase the storage capacitance Cst from the equation (1). is there.
In that respect, in the electrophoretic display device 100 of the present embodiment, since the first protective film 85A made of a silicon nitride film having a thickness of 150 nm is used as the storage capacitor insulating film, the capacitance value per unit area can be increased and is sufficiently large. A storage capacitor can be formed. As a result, since the feedthrough voltage variation ΔV can be reduced, fluctuations in pixel potential can be suppressed, and an electrophoretic display device with little display unevenness can be realized.
Since the storage capacitance value is related to the area of the overlapping portion of the drain electrode 79 and the storage capacitor upper electrode 80, a design that can reduce processing variations such as alignment variations between the drain electrode 79 and the storage capacitor upper electrode 80 is minimized. It is desirable to do.

Next, energy consumption of the electrophoretic display device will be described.
In general, the power consumption P is expressed as P = fCV ² where f is the drive frequency, C is the capacitance, and V is the applied voltage. Most of the power P is data with a high drive frequency f and a large applied voltage V. Occupied by line drive. Since the driving voltage of the electrophoretic display device is, for example, about 15V, which is higher than about 5V of the liquid crystal display device, the power consumption for driving the data lines is larger than that of the liquid crystal display device. On the other hand, energy consumption is represented by the product of power consumption and driving time. In the case of an electrophoretic display device having display memory, refresh driving for maintaining display is unnecessary. Therefore, the energy consumption can be made smaller than that of the liquid crystal display device in the usage where the rewriting frequency is low.

  In that respect, in the electrophoretic display device 100 of the present embodiment, a sufficiently large storage capacitor can be formed, so that the pixel potential during a period required to change the display state can be reliably held. In other words, it is not necessary to write the storage capacitor a plurality of times, and the pixel potential can be reliably held only by writing once. Therefore, since driving for refreshing the pixel voltage is not necessary, energy for charging the data line 68 can be reduced, and energy consumption can be greatly reduced.

  Further, in the present embodiment, the second protective film 85B and the planarizing film 92 are formed so as to cover the first TFT 72, the second TFT 73, and the storage capacitor 71, and the pixel electrode 35 is formed on these insulating films. Since the second protective film 85B and the planarizing film 92 are not constituent elements of the storage capacitor 71, these films, particularly the planarizing film 92, can be made thick. For example, when the planarizing film 92 is formed thick, the step on the substrate is sufficiently filled, so that the flatness of the entire element substrate 30 can be improved. As a result, when the electrophoretic display device 100 is manufactured, the adhesiveness between the element substrate 30 and the electrophoretic element 32 or the adhesiveness between the element substrate 30 and the counter substrate 31 can be improved, and highly reliable electricity. An electrophoretic display device can be realized.

  Further, by increasing the thickness of the planarizing film 92, the position of the pixel electrode 35 (height from the substrate surface) can be separated from the position of the wiring such as the data line 68 and the scanning line 66. The parasitic capacitance between the two can be reduced. In addition, since the pixel electrode 35 can be arranged above the wiring such as the data line 68 and the scanning line 66 and these wirings can be shielded by the pixel electrode 35, the leakage electric field from the wiring can be suppressed, and the fluctuation of the pixel potential can be suppressed. Display quality can be improved.

  Further, in the present embodiment, since the transparent oxide semiconductor material such as In—Ga—Zn—O is used as the semiconductor material of the first and second TFTs 72 and 73, the external light is compared with the case where a non-single crystal silicon material is used. TFT leakage current due to can be greatly suppressed. In particular, even in the configuration in which the counter substrate 31 is not provided with a light blocking portion such as a black matrix, leakage current due to external light can be suppressed, which is preferable as an element substrate for use in an electrophoretic display device.

[Second Embodiment]
Hereinafter, a second embodiment of the present invention will be described with reference to FIGS.
The electro-optical device of this embodiment is also an example of an active matrix type electrophoretic display device, as in the first embodiment.
The basic configuration of the electrophoretic display device of this embodiment is the same as that of the first embodiment, except that the storage capacitor of each pixel is configured by two stacked storage capacitors.
FIG. 9 is a diagram showing a planar pattern of each pixel of the element substrate of the electrophoretic display device of this embodiment. 10 is a cross-sectional view taken along the line AA ′ of FIG. FIG. 11 is an equivalent circuit diagram of each pixel of the electrophoretic display device.
9 to 11, the same reference numerals are given to the same components as those in FIGS. 2, 5, and 6 used in the first embodiment, and detailed description thereof is omitted.

  In the electrophoretic display device of the present embodiment, as shown in FIG. 11, each pixel 40A has two storage capacitors 71A and 71B connected in parallel to each other. One electrode of the first storage capacitor 71A and one electrode of the second storage capacitor 71B are electrically connected to the pixel electrode 35, and the other electrode of the first storage capacitor 71A is electrically connected to the first capacitor line 67A. The other electrode of the second storage capacitor 71B is electrically connected to the second capacitor line 67B.

  As shown in the plane pattern of FIG. 9, the first storage capacitor upper electrode 80A and the first capacitor line 67A extending in the lateral direction of FIG. Is formed. Further, in the present embodiment, unlike the first embodiment, the second storage capacitor lower electrode 80B is formed to partially overlap the first storage capacitor upper electrode 80A and the drain electrode 79. Further, a second capacitor line 67B extending in the horizontal direction of FIG. 9 is arranged substantially parallel to the scanning line 66, and in each pixel 40, a second storage capacitor lower electrode 80B is integrated with the second capacitor line 67B. Is formed. Therefore, the region where the first storage capacitor upper electrode 80A and the drain electrode 79 overlap is the first storage capacitor 71A, and the region where the second storage capacitor lower electrode 80B and the drain electrode 79 overlap is the second storage capacitor 71B. About others, it is substantially the same as FIG. 5 of 1st Embodiment. The first capacitor line 67A and the second capacitor line 67B are electrically connected to the outside of the display unit 5 (not shown) and have the same potential.

  As shown in the sectional structure of the element substrate 30B in FIG. 10, the first storage capacitor upper electrode 80A made of the third conductive film, the first capacitor insulating film made of the first protective film 85A, and the first storage capacitor upper electrode. The first storage capacitor 71A is configured by a part of the drain electrode 79 that overlaps with 80A in the same manner as in the first embodiment. This embodiment is different from the first embodiment in that a second storage capacitor 71B is further formed on the lower layer side of the first storage capacitor 71A, and the first storage capacitor 71A is stacked on the second storage capacitor 71B. ing. The second storage capacitor 71B includes a second storage capacitor lower electrode 80B made of the first conductive film in the same layer as the gate electrodes 74 and 75 and the scanning line 66, a part of the drain electrode 79, and the second storage capacitor lower electrode 80B. And a part of the drain electrode 79, and a gate insulating film 83 functioning as a second storage capacitor insulating film. About others, it is substantially the same as FIG. 6 of 1st Embodiment.

  The materials and film thicknesses of various films in the present embodiment are the same as those in the first embodiment. Further, the manufacturing process is the same as that of the first embodiment, and the second storage capacitor lower electrode 80B may be formed at the same time in the step of forming the gate electrodes 74 and 75 and the scanning line 66. Well, the manufacturing process does not increase.

  In the present embodiment, the first storage capacitor 71A is stacked on the second storage capacitor 71B, and the sum of the capacitance values of these two storage capacitors 71A and 71B becomes the storage capacitor value of the entire pixel. Therefore, as compared with the configuration of the first embodiment, a larger capacitance value can be obtained without increasing the area occupied by the storage capacitor. As a result, it is possible to realize an electrophoretic display device in which variations in feedthrough voltage are further suppressed and display unevenness is small.

  In the present embodiment, the drain electrode 79 is electrically connected to the pixel electrode 35, the first storage capacitor upper electrode 80A is electrically connected to the first capacitor line 67A, and the second storage capacitor lower electrode 80B is connected to the first electrode. The second capacitor line 67B is electrically connected. According to this configuration, only one contact hole 81 for electrically connecting the drain electrode 79 functioning as an electrode of both the storage capacitors 71A and 71B and the pixel electrode 35 is required, and accordingly, the storage capacitor correspondingly. A large capacitance value can be obtained.

[Third Embodiment]
Hereinafter, a third embodiment of the present invention will be described with reference to FIGS.
The electro-optical device of this embodiment is also an example of an active matrix type electrophoretic display device, as in the first and second embodiments.
The basic configuration of the electrophoretic display device of this embodiment is the same as that of the second embodiment, and the storage capacitors of each pixel are configured by two stacked storage capacitors.
FIG. 12 is a diagram showing a planar pattern of each pixel of the element substrate of the electrophoretic display device of this embodiment. FIG. 13 is a cross-sectional view taken along the line AA ′ of FIG. FIG. 14 is an equivalent circuit diagram of each pixel of the electrophoretic display device.
12 to 14, the same reference numerals are given to the same components as those in FIGS. 2, 5, and 6 used in the first embodiment, and detailed description thereof is omitted.

  In the electrophoretic display device of the present embodiment, as shown in FIG. 14, each pixel 40A has two storage capacitors 71A and 71B connected in parallel to each other. One electrode of the first storage capacitor 71A and one electrode of the second storage capacitor 71B are electrically connected to the pixel electrode 35, and the other electrode of the first storage capacitor 71A and the other electrode of the second storage capacitor 71B. Are electrically connected to the capacitor line 67.

  In the element substrate 30C of the present embodiment, as shown in a planar pattern in FIG. 12, unlike the second embodiment, a first storage capacitor lower electrode 93 is formed separately from the drain electrode 79C. Further, a contact hole 94A for electrically connecting the drain electrode 79C and the pixel electrode 35, a contact hole 94B for electrically connecting the first storage capacitor upper electrode 80A and the pixel electrode 35, and a second storage capacitor. Three contact holes 94C for electrically connecting the lower electrode 80B and the pixel electrode 35 are provided in the opening 92A of the planarizing film 92. Further, the capacitor line 67 extending in the vertical direction of FIG. 12 and the first storage capacitor lower electrode 93 are formed integrally with the data line 68. About others, it is substantially the same as FIG. 9 of 2nd Embodiment.

  As shown in the cross-sectional structure of the element substrate 30C in FIG. 13, the two-stage storage capacitor composed of the first storage capacitor 71A and the second storage capacitor 71B includes the first storage capacitor upper electrode 80A and the first storage capacitor lower electrode 93. It is composed of three layers of electrodes (also serving as a second storage capacitor upper electrode) and a first storage capacitor lower electrode 80B. The connection structure between these electrodes is different from that of the second embodiment. That is, in the second embodiment, among the three layers of electrodes, the intermediate electrode is electrically connected to the pixel electrode 35, and the upper and lower layers of the two layers of electrodes are electrically connected to different capacitance lines 67A and 67B, respectively. Was connected. In contrast, in the present embodiment, the upper first storage capacitor upper electrode 80A is electrically connected to the pixel electrode 35, and the lower second storage capacitor lower electrode 80B is electrically connected to the pixel electrode 35. The first storage capacitor lower electrode 93 is electrically connected to the capacitor line 67. In other words, the first storage capacitor upper electrode 80A and the second storage capacitor lower electrode 80B are electrically connected to each other with the pixel electrode 35 as a relay layer, and the first storage capacitor lower electrode 93 is electrically connected to the capacitor line 67. Has been.

  In order to realize the above-described connection structure, the contact hole 94A that reaches the drain electrode 79C through the second protective film 85B and the first protective film 85A and electrically connects the drain electrode 79C and the pixel electrode 35, the first The contact hole 94C that penetrates the second protective film 85B, the first protective film 85A, and the gate insulating film 83 and reaches the second storage capacitor lower electrode 80B, and electrically connects the second storage capacitor lower electrode 80B and the pixel electrode 35. A contact hole 94B that penetrates the second protective film 85B to reach the first storage capacitor upper electrode 80A and electrically connects the first storage capacitor upper electrode 80A and the pixel electrode 35 is formed. About others, it is substantially the same as FIG. 10 of 2nd Embodiment.

  As in the second embodiment, the materials and film thicknesses of various films in this embodiment are the same as those in the first embodiment. Further, the manufacturing process is the same as that of the first embodiment, and the number of second storage capacitor electrodes 80B is increased as a component. However, the second storage capacitor electrode 80B is simultaneously formed in the step of forming the gate electrodes 74 and 75 and the scanning line 66. Since it only needs to be formed, only the design of the photomask needs to be changed, and the manufacturing process does not increase.

  In the present embodiment, the first storage capacitor 71A is stacked on the second storage capacitor 71B, and the sum of the capacitance values of these two storage capacitors 71A and 71B becomes the storage capacitor value of the entire pixel. Therefore, as compared with the configuration of the first embodiment, a larger capacitance value can be obtained without increasing the area occupied by the storage capacitor. As a result, it is possible to realize an electrophoretic display device in which variations in feedthrough voltage are further suppressed and display unevenness is small.

  According to the configuration of this embodiment, the contact holes 94A, 94B, and 94C are contact holes that connect the drain electrode 79C, the pixel electrode 35, the first storage capacitor upper electrode 80A, and the second storage capacitor lower electrode 80B to each other. Although a total of three is required, unlike the second embodiment, one capacitance line is sufficient for one pixel, so that the degree of freedom in wiring design can be increased.

  In the present embodiment, the first storage capacitor upper electrode 80A and the second storage capacitor lower electrode 80B are connected to each other using the pixel electrode 35 as a relay layer. However, the pixel electrode 35 is not necessarily used as the relay layer. For example, a contact hole forming step is added before the third conductive film constituting the first storage capacitor upper electrode 80A is formed, and the second storage capacitor lower electrode penetrates the first protective film 85A and the gate insulating film 83. After the contact hole reaching 80B is formed, a third conductive film may be formed, and this third conductive film may be used as a relay layer.

[Fourth Embodiment]
Hereinafter, a fourth embodiment of the present invention will be described with reference to FIG.
The electro-optical device of this embodiment is also an example of an active matrix type electrophoretic display device, as in the first to third embodiments.
The basic configuration of the electrophoretic display device of this embodiment is the same as that of the second and third embodiments, and the storage capacitor of each pixel is configured by two stacked storage capacitors. Further, the connection structure of the capacitor electrode is the same as that of the second embodiment, and only the configuration of the TFT is different from that of the second embodiment.
FIG. 15 is a cross-sectional view of an element substrate in the electrophoretic display device of this embodiment.
In FIG. 15, the same components as those in FIG. 11 used in the second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the element substrate 30D of the present embodiment, as shown in FIG. 15, the source electrode 77D and the drain electrode 79D are formed on the gate insulating film 83, and a part of the semiconductor layer 76D is formed on the source electrode 77D and the drain electrode 79D. It is formed to ride on. That is, the TFT 72D of this embodiment is a bottom contact type TFT unlike the TFTs of the first to third embodiments. Also in the present embodiment, as in the first to third embodiments, a transparent oxide semiconductor material such as In—Ga—Zn—O is used for the semiconductor layer 76D. Other configurations are the same as those of the second embodiment.

When manufacturing the element substrate 30D, the gate electrode 74, the scanning line 66, and the second storage capacitor lower electrode 80B are formed on one surface of the substrate body 82, and then the silicon nitride having a film thickness of 400 nm that becomes the gate insulating film 83 is formed. A film (first insulating film) is formed.
Next, for example, a conductive film such as Mo / Al / Mo is formed, and the conductive film is patterned by a photolithography method or an etching method to form a source electrode 77D, a drain electrode 79D, and the like.

Next, an In—Ga—Zn—O film to be the semiconductor layer 76D is formed. For the In—Ga—Zn—O film, an amorphous In—Ga—Zn—O film with a composition ratio of In: Ga: Zn = 1: 1: 1 is formed by a sputtering method using an InGaZnO ₄ target.
Next, the In—Ga—Zn—O film is patterned by a photolithography method and an etching method, so that the semiconductor layer 76D is formed.
The following steps are the same as those in the first to third embodiments. After the first protective film 85A, the first storage capacitor upper electrode 80A, the second protective film 85B, and the planarizing film 92 are formed, the pixel electrode 35 is formed. To do.
The element substrate 30D of this embodiment is completed through the above steps.

Also in the present embodiment, the effects similar to those of the first to third embodiments are obtained such that formation of a sufficient storage capacitor can suppress variation in feedthrough voltage and can realize an electrophoretic display device with less display unevenness. be able to.
Further, according to the manufacturing process of the present embodiment, since the source electrode 77D and the drain electrode 79D are formed before the semiconductor layer 76D is formed, the semiconductor layer 76D is not damaged by etching. Therefore, a TFT having excellent electrical characteristics can be formed by a simple manufacturing process without forming an etching stop layer as in the first to third embodiments.
In addition, the adoption of a transparent oxide semiconductor TFT such as In—Ga—Zn—O can achieve the effect that the leakage current of the TFT due to external light can be greatly suppressed, as in the first to third embodiments. is there.

[Fifth Embodiment]
Hereinafter, a fifth embodiment of the present invention will be described with reference to FIG.
The electro-optical device of this embodiment is also an example of an active matrix type electrophoretic display device, as in the first to fourth embodiments.
The basic configuration of the electrophoretic display device of this embodiment is the same as that of the second to fourth embodiments, and the storage capacitor of each pixel is configured by two stacked storage capacitors. Further, the connection structure of the capacitor electrode is the same as that of the second and fourth embodiments, and the configuration of the TFT is only different from that of the second and fourth embodiments.
FIG. 16 is a cross-sectional view of an element substrate in the electrophoretic display device of this embodiment.
In FIG. 16, the same components as those in FIG. 10 used in the second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

In the element substrate 30E of this embodiment, as shown in FIG. 16, N ⁺ semiconductor layers 84 in which an N-type impurity such as phosphorus is introduced into a semiconductor material are formed at both ends of the semiconductor layer 76. Each N ⁺ semiconductor layer 84 functions as a source region and a drain region, respectively. The TFT used in this embodiment is a so-called back channel etch type. As a material of the semiconductor layer 76 and the N ⁺ semiconductor layer 84, for example, amorphous silicon having a film thickness of 150 nm is used. In addition, non-single-crystal silicon materials such as polycrystalline silicon, oxide semiconductor materials, transparent oxide semiconductor materials, organic semiconductor materials, and the like can be used. When an organic semiconductor material is used for the semiconductor layer 76, it is desirable to use an organic insulating material also for the gate insulating film 83 (first insulating film).

Hereinafter, when manufacturing the element substrate 30E having the above-described configuration, the scanning line 66, the gate electrode 74, and the second storage capacitor lower electrode 80B are formed on one surface of the substrate body 82, and then the gate insulating film 83 is formed by plasma CVD. A silicon nitride film having a thickness of 400 nm serving as a (first insulating film), a non-doped amorphous silicon film having a thickness of 150 nm serving as a semiconductor layer 76, and an amorphous silicon film doped with phosphorus having a thickness of 50 nm serving as an N ⁺ semiconductor layer 84. Three layers are continuously formed without breaking the vacuum in the chamber. The TFT 72E of this embodiment is an inverted stagger type, and in particular, a clean interface can be obtained by continuously forming the gate insulating film 83 and the semiconductor layer 76 serving as a channel region, and the reproducibility and stability of TFT characteristics are improved. To do.

Next, among the three layers formed in the previous step by photolithography and etching, the non-doped amorphous silicon film and the phosphorus-doped amorphous silicon film are selectively patterned leaving the gate insulating film 83, and the semiconductor layer 76 and N ⁺ Semiconductor layer 84 is formed. Etching in this step employs dry etching using an etching gas containing SF ₆ . At this time, it is desirable to minimize damage to the gate insulating film 83 by using the plasma mode.

Next, a second conductive film made of a metal laminated film of 5 nm thick Mo, 150 nm thick Al, and 50 nm thick Mo is formed from the lower layer side by sputtering.
Next, the second conductive film is patterned by photolithography and etching to form a source electrode 77 and a drain electrode 79.
Next, the N ⁺ semiconductor layer 84 between the source electrode 77 and the drain electrode 79 of the TFT 72E is selectively removed by dry etching to separate the source region and the drain region.

Next, a silicon nitride film having a thickness of 150 nm is formed as a first protective film 85A (second insulating film) by plasma CVD.
Next, for example, after forming a third conductive film made of a metal laminated film similar to the second conductive film by sputtering, the third conductive film is patterned by photolithography and etching, and the first storage capacitor upper electrode 80A is formed. Form.
The following is the same as in the first embodiment.

  Also in the present embodiment, the effects similar to those of the first to fourth embodiments are obtained such that the formation of a sufficient storage capacitor can suppress variations in feedthrough voltage and can realize an electrophoretic display device with less display unevenness. be able to.

The technical scope of the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention.
For example, in the above embodiment, an example using an amorphous silicon TFT and a transparent oxide semiconductor TFT has been described. However, an organic TFT, a polycrystalline silicon TFT, or the like may be used. Note that an oxide semiconductor TFT is higher in mobility than amorphous silicon, and can be downsized. Therefore, the oxide semiconductor TFT is preferable in that the parasitic capacitance between the gate and the drain can be reduced, and variation in feedthrough voltage can be reduced.
In addition, the specific configuration of each member of the electrophoretic display device, such as the material, film thickness, shape, and manufacturing method, is not limited to the above embodiment, and can be changed as appropriate.

  In the above embodiment, an example of an active matrix electrophoretic display device has been described. However, the present invention may be applied to other electro-optical devices such as an active matrix liquid crystal display device. For example, when applied to a reflective liquid crystal display device, since the storage capacity is large, the retention rate of the pixel potential can be increased even when the writing frequency is lowered, and power consumption can be reduced while suppressing flicker. The effect is obtained.

  Furthermore, the present invention is more effective when combined with other techniques for increasing capacity density. For example, only the region for forming the storage capacitor in the gate insulating film may be thinned. According to this configuration, it is possible to reduce the power consumption while ensuring the breakdown voltage of the TFT and suppressing the leakage current. Specifically, as a method of thinning the gate insulating film, the gate insulating film has a two-layer structure, the first gate insulating film is formed on the entire surface, and then the first gate insulating film in the storage capacitor formation region is removed. In addition, a method of forming the second gate insulating film over the entire surface can be given. According to this method, since the film thickness variation of the entire gate insulating film in the storage capacitor formation region is only the film thickness variation of the second gate insulating film, the gate insulating film of one layer is etched halfway to reduce the thickness. The film thickness variation can be reduced as compared with the method.

[Electronics]
Next, a case where the electrophoretic display device 100 of the above embodiment is applied to an electronic device will be described.
FIG. 17 is a front view of the wristwatch 1000. The wrist watch 1000 includes a watch case 1002 and a pair of bands 1003 connected to the watch case 1002.
On the front surface of the watch case 1002, a display unit 1005 including the electrophoretic display device of each of the above embodiments, a second hand 1021, a minute hand 1022, and an hour hand 1023 are provided. On the side surface of the watch case 1002, a crown 1010 and an operation button 1011 are provided as operation elements. The crown 1010 is connected to a winding stem (not shown) provided inside the case, and is integrally provided with the winding stem so that it can be pushed and pulled in multiple stages (for example, two stages) and can be rotated. . The display unit 1005 can display a background image, a character string such as date and time, or a second hand, a minute hand, and an hour hand.

  FIG. 18 is a perspective view illustrating a configuration of the electronic paper 1100. An electronic paper 1100 includes the electrophoretic display device of the above embodiment in a display area 1101. The electronic paper 1100 is flexible and includes a main body 1102 made of a rewritable sheet having the same texture and flexibility as conventional paper.

  FIG. 19 is a perspective view illustrating a configuration of the electronic notebook 1200. An electronic notebook 1200 is obtained by bundling a plurality of the electronic papers 1100 and sandwiching them between covers 1201. The cover 1201 includes display data input means (not shown) for inputting display data sent from an external device, for example. Thereby, according to the display data, the display content can be changed or updated while the electronic paper is bundled.

According to the wristwatch 1000, the electronic paper 1100, and the electronic notebook 1200 described above, the electrophoretic display device according to the present invention is employed, so that the electronic apparatus is provided with display means capable of obtaining excellent reliability over a long period of time. .
In addition, said electronic device illustrates the electronic device which concerns on this invention, Comprising: The technical scope of this invention is not limited. For example, the electro-optical device according to the present invention can be suitably used for a display portion of an electronic device such as a mobile phone or a portable audio device.

  30, 30B, 30C, 30D, 30E ... element substrate (electro-optical device substrate), 35 ... pixel electrode, 40, 40A ... pixel, 41 ... selection transistor (pixel switching element), 66 ... scanning line, 67 ... capacitance line , 67A ... first capacitor line, 67B ... second capacitor line, 68 ... data line, 71 ... storage capacitor, 71A ... first storage capacitor, 71B ... second storage capacitor, 74, 75 ... gate electrode, 76, 76D ... Semiconductor layer, 77, 77D ... source electrode, 79, 79C, 79D ... drain electrode (first storage capacitor lower electrode and second storage capacitor upper electrode), 80 ... storage capacitor upper electrode, 80A ... first storage capacitor upper electrode, 80B ... second storage capacitor lower electrode, 83 ... gate insulating film, 85A ... first protective film, 85B ... second protective film (third insulating film), 91 ... etching stop layer, 92 ... flattening film (third insulating film) film) 93 ... first storage capacitor lower electrode, 100 ... electrophoretic display device, 1000 ... wristwatch (electronic apparatus), 1100 ... electronic paper (Electronic Equipment), 1200 ... electronic notebook (electronic equipment).

Claims (14)

A substrate body, a plurality of data lines and a plurality of scanning lines provided in the substrate body, and a plurality of pixels partitioned by the data lines and the scanning lines,
Each of the plurality of pixels is a substrate for an electro-optical device including a pixel switching element, a pixel electrode, and a first storage capacitor,
The pixel switching element includes a gate electrode made of a first conductive film formed on the substrate body, a gate insulating film made of a first insulating film formed so as to cover at least the gate electrode, and the gate insulating film A semiconductor layer formed thereon; a source electrode made of a second conductive film electrically connected to the source region of the semiconductor layer and the data line; and a drain region of the semiconductor layer and the pixel electrode electrically A drain electrode made of the second conductive film connected,
A first storage capacitor lower electrode made of the second conductive film; and a first storage capacitor insulation film made of a second insulation film formed so as to cover at least the first storage capacitor lower electrode; A third conductive film formed of a third conductive film formed so as to overlap at least a portion of the first storage capacitor lower electrode with the first storage capacitor insulating film in between when viewed from the normal direction of the substrate body. 1 storage capacitor upper electrode, and
A third insulating film is formed so as to cover at least a part of the pixel switching element and the first storage capacitor, and the pixel electrode is formed on the third insulating film. substrate. Each of the plurality of pixels includes a second storage capacitor formed so that at least a portion thereof overlaps the first storage capacitor when viewed from the normal direction of the substrate body;
The second storage capacitor comprises a second storage capacitor lower electrode made of the first conductive film and a second storage capacitor insulation film made of the first insulation film so as to cover at least the second storage capacitor lower electrode. And, when viewed from the normal direction of the substrate body, at least a portion thereof overlaps the second storage capacitor lower electrode with the second storage capacitor insulating film interposed therebetween, and the lower portion of the first storage capacitor The substrate for an electro-optical device according to claim 1, further comprising: a second storage capacitor upper electrode that is also used as the first storage capacitor.   The first storage capacitor lower electrode is electrically connected to the pixel electrode, the first storage capacitor upper electrode is electrically connected to the first capacitor line, and the second storage capacitor lower electrode is the first electrode. 3. The electro-optical device substrate according to claim 2, wherein the substrate is electrically connected to a second capacitor line different from the capacitor line.   The first storage capacitor upper electrode is electrically connected to the pixel electrode, the second storage capacitor lower electrode is electrically connected to the pixel electrode, and the first storage capacitor lower electrode is electrically connected to the capacitor line. The substrate for an electro-optical device according to claim 2, wherein the substrate is connected electrically.   5. The electro-optical device substrate according to claim 1, wherein a thickness of the second insulating film is smaller than a thickness of the first insulating film.   A part of the source electrode and a part of the drain electrode are formed on the semiconductor layer, the source electrode is electrically connected to the source region of the semiconductor layer, and the drain electrode is 6. The electro-optical device substrate according to claim 1, wherein the substrate is electrically connected to the drain region of the semiconductor layer.   The electro-optical device substrate according to claim 6, wherein an etching stopper layer is provided in a region above the channel region of the semiconductor layer.   A part of the semiconductor layer is formed on the source electrode and the drain electrode, the source electrode is electrically connected to the source region of the semiconductor layer, and the drain electrode is 6. The electro-optical device substrate according to claim 1, wherein the substrate is electrically connected to the drain region of the semiconductor layer.   The substrate for an electro-optical device according to claim 1, wherein the semiconductor layer is made of non-single crystal silicon.   The substrate for an electro-optical device according to claim 1, wherein the semiconductor layer is made of an oxide semiconductor material.   9. The electro-optical device substrate according to claim 1, wherein the semiconductor layer is made of a transparent oxide semiconductor material.   9. The electro-optical device substrate according to claim 1, wherein the semiconductor layer is made of an organic semiconductor material. A pair of substrates, and an electro-optic material layer sandwiched between the pair of substrates,
An electro-optical device, wherein one of the pair of substrates is the substrate for an electro-optical device according to any one of claims 1 to 12.   An electronic apparatus comprising the electro-optical device according to claim 13.

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