CN107153308A - Array base palte and preparation method - Google Patents
Array base palte and preparation method Download PDFInfo
- Publication number
- CN107153308A CN107153308A CN201710464019.5A CN201710464019A CN107153308A CN 107153308 A CN107153308 A CN 107153308A CN 201710464019 A CN201710464019 A CN 201710464019A CN 107153308 A CN107153308 A CN 107153308A
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- wire body
- scan line
- active layer
- string holes
- line
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- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 238000002161 passivation Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000012212 insulator Substances 0.000 claims description 11
- 230000003071 parasitic effect Effects 0.000 abstract description 7
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical group [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 239000011733 molybdenum Substances 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000010408 sweeping Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention provides a kind of array base palte, including substrate, multi-strip scanning line, the active layer in scan line, a plurality of data lines being staggered with scan line, the drain electrode contacted, the passivation layer being formed on drain electrode and the pixel electrode being formed on passivation layer with active layer, it is located in the scan line at the position that data wire interlocks and has scanning string holes, in this part wire body interlocked on the data wire with scan line, a part of wire body of wire body is overlapping with scanning string holes, and another part wire body of wire body is overlapping with active layer and mutually overlaps.Present invention also offers a kind of preparation method of array base palte.Compared with prior art, by opening up scanning string holes at the position that interlocks in scan line with data wire, reduce scan line and the area of data line overlap, so as to reduce parasitic capacitance and then reduce the influence that Vacuum-Voltss counter plate is shown, so while pixel electrode aperture opening ratio is improved the resistance of scan line can also be kept constant.
Description
Technical field
The present invention relates to a kind of LCD plate technique, particularly a kind of array base palte and preparation method.
Background technology
Liquid crystal display (Liquid Crystal Display, LCD) has thin fuselage, power saving, radiationless etc. numerous excellent
Point, is widely used, such as：LCD TV, mobile phone, personal digital assistant (PDA), digital camera, computer screen
Curtain or notebook computer screen etc., occupy an leading position in flat display field.
Thin film transistor (TFT) (Thin Film Transistor, TFT) liquid crystal display is that current mainstream market is most common
Liquid crystal display, and typically use Sun-shading type structure design to reduce leakage current caused by backlight illumination in the design of TFT pixels
The problem of influence bigger than normal；One big shortcoming of Sun-shading type structure has big parasitic capacitance, causes big Feedthrough (vacuum)
Voltage, causes signal write-in by mistake.At present, large size panel requires that the line width of scan line is tried one's best and does big, with driven panel, but
It is that the parasitic capacitance that can so make data wire and scan line becomes big, causing RC retardation ratio, (RC Delay, i.e. electric capacity and resistance increase are led
Cause time delay), it can so cause splashette (Flicker) abnormal problem.
The content of the invention
To overcome the deficiencies in the prior art, the present invention provides a kind of array base palte and preparation method, makes data wire and scanning
The area of line overlap reduces, and so reduces parasitic capacitance and then reduces the influence that Vacuum-Voltss counter plate is shown.
The invention provides a kind of array base palte, including substrate, multi-strip scanning line, the active layer in scan line, with
A plurality of data lines that scan line is staggered, the drain electrode contacted with active layer, the passivation layer being formed on drain electrode and formation
In the pixel electrode on passivation layer, the pixel electrode passes through the via being located on passivation layer and is connected with drain electrode；The scan line
It is upper to have this part wire body interlocked on scanning string holes, the data wire with scan line at the position that data wire interlocks
In, a part of wire body of wire body is overlapping with scanning string holes, and another part wire body of wire body is overlapping with active layer and mutually overlaps.
Further, the part wire body for body line width half that at least the line is busy is overlapping with scan line bore portion, remaining portion of wire body
Separated time body partly overlaps and overlapped with active layer.
Further, an at least lateral edges and a lateral edges pair of the scan line hole position at wire body in the active layer
Together.
Further, the scanning string holes is rectangular opening.
Further, in the scanning string holes with the length of data wire bearing of trend identical via first edge and active
Equal length in layer with data wire bearing of trend identical active layer first edge；With via first edge in the data wire
The length of vertical via second edge is at least twice of data wire line width.
Further, the part wire body for body line width 2/3rds that the line is busy in the wire body is overlapping with scan line bore portion.
Further, it is located in the scan line between adjacent data line provided with broadening portion.
Present invention also offers a kind of preparation method of array base palte, comprise the following steps：
Step S01, one substrate of offer, make gate electrode layer and graphically form scan line on a surface of a substrate；
Step S02, the length direction making scanning string holes in scan line along scan line；
Step S03, gate insulator is made in scan line；
Step S04, it is located on gate insulator by each scanning string holes and makes active layer respectively；
Step S05, making is staggered with scan line respectively on gate insulator data wire, drain electrode, the leakage
Electrode is contacted with active layer, and in this part wire body interlocked on the data wire with scan line, a part of wire body of wire body is with sweeping
Retouch that string holes is overlapping, another part wire body of wire body is overlapping with active layer and mutually overlaps；
Step S06, make passivation layer on data wire and drain electrode, and be located at over the passivation layer at drain electrode and made
Hole；
Step S07, the via made over the passivation layer on pixel electrode, the passivated layer of pixel electrode connect with drain electrode
Touch.
Further, the part wire body for body line width half that at least the line is busy in the step S05 is overlapping with scan line bore portion,
Remaining part wire body of wire body partly overlaps and overlapped with active layer.
Further, in the step S05 in active layer an at least lateral edges and scan line hole position at wire body one
Side edge-justified calibrations.
The present invention compared with prior art, by opening up scanning string holes at the position that interlocks in scan line with data wire,
Reduce scan line and the area of data line overlap, so as to reduce parasitic capacitance and then reduce what Vacuum-Voltss counter plate was shown
Influence, so can also keep the resistance of scan line constant while pixel electrode aperture opening ratio is improved.
Brief description of the drawings
Fig. 1-1 is the top view of array base palte of the present invention；
Fig. 1-2 is sectional views of the Fig. 1 along A-A directions；
Fig. 2-1 is the top view that the present invention makes scan line；
Fig. 2-2 is sectional views of the Fig. 2-1 along B-B directions；
Fig. 3-1 is the top view that the present invention makes active layer；
Fig. 3-2 is sectional views of the Fig. 3-1 along C-C directions；
Fig. 4-1 is the top view that the present invention makes data wire and drain electrode；
Fig. 4-2 is sectional views of the Fig. 4-1 along D-D directions；
Fig. 5-1 is the top view that the present invention makes passivation layer；
Fig. 5-2 is sectional views of the Fig. 5-1 along E-E directions；
Fig. 6 is the flow chart of preparation method of the present invention.
Embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.
Device position relation related to the present invention is illustrate only in Fig. 1-1,2-1,3-1,4-1,5-1.
As shown in Fig. 1-1 and Fig. 1-2, a kind of array base palte of the invention, including a substrate 1, multi-strip scanning line (grid
Line) 2, the active layer 3 in scan line 2, a plurality of data lines 4 being staggered with scan line 2, the leakage contacted with active layer 3
Electrode 5, the passivation layer 6 being formed on drain electrode 5 and the pixel electrode 7 being formed on passivation layer 6；In scan line 2 and active layer 3
Between be provided with one layer of gate insulator 12, the pixel electrode 7 is connected through being located at the via on passivation layer 6 with drain electrode 5；
This portion interlocked on scanning string holes 8, data wire 4 with scan line 2 is had at the position interlocked in scan line 2 with data wire 4
In separated time body 9 (dotted portion is and the scanning lap of string holes 8 in Fig. 1-1), a part of wire body and the scanning string holes 8 of wire body 9
Overlapping, another part wire body of wire body 9 is overlapping with active layer 3 and mutually overlaps, and is so the equal of to enter the line width of scan line 2
Go change, reduced the area with data line overlap, so as to reduce parasitic capacitance, and then reduce Vacuum-Voltss to display panel
Influence.
In the present invention, the part wire body for the line width half of body 9 that at least the line is busy with scanning string holes 8 partly overlap, wire body 9 remaining
Part wire body partly overlap and overlap with active layer 3, further reduce the area of scan line and data line overlap, specifically
The part wire body for the line width 2/3rds of body 9 that the line is busy in ground, wire body 9 partly overlaps with scanning string holes 8, can so ensure film
Transistor can be with normal work.
As one embodiment of the present invention, an at least lateral edges are located at wire body 9 with scanning string holes 8 in active layer 3
One side edge-justified calibrations at place, it is ensured that data wire can be overlapping with active layer and overlapped, and become with the overlapping area of scan line 2
Very little is obtained, so can also ensure that scan line plays a part of shading.
In the present invention, scanning string holes 8 is rectangular opening (shown in Fig. 2-1), specifically, and scanning string holes 8 has prolongs with data wire 4
Stretch identical direction and two via first edges 10 being oppositely arranged and vertical with via first edge 10 and relative set
The two via second edges 13 put；Wherein, in the length and active layer 3 of the via first edge 10 of the lower section of data wire 4
With the equal length of the bearing of trend identical active layer first edge 11 (shown in Fig. 3-1) of data wire 4；The via second edge
13 length is at least twice of the line width of data wire 4.
As shown in Fig. 1-1 and Fig. 2-1, in order that the resistance of scan line is constant, adjacent data is located in scan line 2
Broadening portion 14 is provided between line 4, the both sides of the edge of scan line 2 is formed rectangular toothed structure；Active layer 3 and the broadening position of portion 14
It is corresponding.
As shown in fig. 6, the preparation method of array base palte of the present invention, comprises the following steps：
Step S01, one substrate 1 of offer, gate electrode layer is made on the surface of substrate 1 and scan line (grid are graphically formed
Polar curve) 2 (Fig. 2-1 and Fig. 2-2 shown in), specifically, using the method such as magnetron sputtering depositing gate electrode layer, pass through photoetching and etching
Technique is patterned to form scan line 2 to gate electrode layer；
The material of the gate electrode layer is molybdenum aluminium alloy, chromium metal, molybdenum, it would however also be possible to employ with shade function and
Conductive material, is not specifically limited herein；
Step S02, the length direction making scanning string holes 8 in scan line 2 along scan line 2, the scanning string holes 8 can be adopted
Formed with the photoetching and etching technics of prior art；
Step S03, the making gate insulator 12 (shown in Fig. 3-2) in scan line 2, are formed using existing depositing operation
Gate insulator 12；
Step S04, it is located on gate insulator 12 by each scanning string holes 8 and makes active layer 3 (Fig. 3-1 and 3-2 respectively
It is shown), specifically, the material of active layer 3 is non-crystalline silicon, metal oxide, polysilicon etc.；Photoetching and quarter by prior art
Etching technique etches away remaining active layer 3 for locating to be located at beyond the active layer 3 on the side of scanning line traffic control 8；
Step S05, the data wire 4 that making is staggered with scan line 2 respectively on the gate insulator 12, (figure of drain electrode 5
Shown in 4-1 and Fig. 4-2), specifically, the drain electrode 5 is contacted with active layer 3, this portion interlocked on data wire 4 with scan line 2
In separated time body 9, a part of wire body of wire body 9 is overlapping with scanning string holes 8, and another part wire body of wire body 9 is overlapping with active layer 3 simultaneously
Mutually overlap；
The material of the data wire 4 and drain electrode 5 is molybdenum aluminium alloy, chromium metal, molybdenum, it would however also be possible to employ with shading
The material of function and electric conductivity, is not specifically limited herein；
Step S06, the making passivation layer 6 on data wire 4 and drain electrode 5, and be located on passivation layer 6 at drain electrode 5
Via (Fig. 5-1 and Fig. 5-2 institutes) is made, the via is formed using existing photoetching and etching technics；
Step S07, pixel electrode 7 (Fig. 1-1 and Fig. 1-2 shown in) is made on passivation layer 6, the pixel electrode 7 is through blunt
The via changed on layer 6 is contacted with drain electrode 5.
The part wire body for the line width half of body 9 that at least the line is busy in step S05 with scanning string holes 8 partly overlap, wire body 9 remaining
Part wire body partly overlaps and overlapped with active layer 3, further reduces scan line and the area of data line overlap, specifically,
The part wire body for the line width 2/3rds of body 9 that the line is busy in wire body 9 partly overlaps with scanning string holes 8, can so ensure that film is brilliant
Body pipe can be with normal work.
An at least lateral edges are located at the side edge-justified calibrations at wire body 9 with scanning string holes 8 in active layer 3 in step S05
(as shown in figure 3-1), it is ensured that data wire can be overlapping with active layer and overlapped, and with the overlapping area of scan line 2 become
Very little, so can also ensure that scan line plays a part of shading.
In the present invention, scanning string holes 8 is rectangular opening (shown in Fig. 2-1), specifically, and scanning string holes 8 has prolongs with data wire 4
Stretch identical direction and two via first edges 10 being oppositely arranged and vertical with via first edge 10 and relative set
The two via second edges 13 put；Wherein, in the length and active layer 3 of the via first edge 10 of the lower section of data wire 4
With the equal length of the bearing of trend identical active layer first edge 11 (shown in Fig. 3-1) of data wire 4；The via second edge
13 length is at least twice of the line width of data wire 4.
As shown in Fig. 1-1 and Fig. 2-1, in order that the resistance of scan line is constant, adjacent data is located in scan line 2
Broadening portion 14 is provided between line 4, the both sides of the edge of scan line 2 is formed rectangular toothed structure；Active layer 3 and the broadening position of portion 14
It is corresponding.
In the preparation method of the present invention, in addition to above-mentioned steps, it is also understood as also preparing the normal of array base palte including remaining
Making step is advised, the above-mentioned improvement only for the present invention is described.
Part line width of the invention by changing scan line, reduces the overlapping area of data wire, active layer and scan line,
So as to reduce the parasitic capacitance of pixel, while pixel aperture ratio is improved, keep the resistance value of scan line constant.
Although the present invention has shown and described with reference to specific embodiment, it should be appreciated by those skilled in the art that：
In the case where not departing from the spirit and scope of the present invention limited by claim and its equivalent, can carry out herein form and
Various change in details.
Claims (10)
1. a kind of array base palte, it is characterised in that：Including substrate (1), multi-strip scanning line (2), active in scan line (2)
Layer (3), be staggered with scan line (2) a plurality of data lines (4), contacted with active layer (3) drain electrode (5), be formed at Lou
Passivation layer (6) on electrode (5) and the pixel electrode (7) being formed on passivation layer (6), the pixel electrode (7) are blunt through being located at
The via changed on layer (6) is connected with drain electrode (5)；It is located on the scan line (2) at the position that data wire (4) interlocks and opens respectively
Have in this part wire body (9) interlocked on scanning string holes (8), the data wire (4) with scan line (2), a part for wire body (9)
Wire body is overlapping with scanning string holes (8), and another part wire body of wire body (9) is overlapping with active layer (3) and mutually overlaps.
2. array base palte according to claim 1, it is characterised in that：The part wire body for line width half that at least the line is busy body (9)
Partly overlapped with scanning string holes (8), remaining part wire body of wire body (9) partly overlaps and overlapped with active layer (3).
3. array base palte according to claim 1 or 2, it is characterised in that：An at least lateral edges in the active layer (3)
It is located at a side edge-justified calibrations at wire body (9) place with scanning string holes (8).
4. the array base palte according to claim 3 any one, it is characterised in that：The scanning string holes (8) is rectangular opening.
5. array base palte according to claim 4, it is characterised in that：Extend in the scanning string holes (8) with data wire (4)
With data wire (4) bearing of trend identical active layer in the length and active layer (3) of direction identical via first edge (10)
The equal length of first edge (11)；The via second edge vertical with via first edge (10) in the data wire (4)
(13) length is at least twice of data wire (4) line width.
6. array base palte according to claim 2, it is characterised in that：Body (9) line width three that the line is busy in the wire body (9)/
Two part wire body partly overlaps with scanning string holes (8).
7. array base palte according to claim 1, it is characterised in that：It is located at adjacent data line (4) on the scan line (2)
Between be provided with broadening portion (14).
8. a kind of preparation method of array base palte, it is characterised in that：Comprise the following steps：
Step S01, one substrate of offer (1), gate electrode layer is made on the surface of substrate (1) and scan line (2) is graphically formed；
Step S02, the length direction making scanning string holes (8) in scan line (2) along scan line (2)；
Step S03, the making gate insulator (12) in scan line (2)；
Step S04, it is located on gate insulator (12) that each scanning string holes (8) is other to make active layer (3) respectively；
Step S05, making is staggered with scan line (2) respectively on gate insulator (12) data wire (4), drain electrode
(5), the drain electrode (5) contacts with active layer (3), this part wire body interlocked on the data wire (4) with scan line (2)
(9) in, a part of wire body of wire body (9) is overlapping with scanning string holes (8), another part wire body and active layer (3) weight of wire body (9)
Fold and mutually overlap；
Step S06, the making passivation layer (6) on data wire (4) and drain electrode (5), and positioned at drain electrode on passivation layer (6)
(5) place makes via；
Step S07, pixel electrode (7) is made on passivation layer (6), the via on the passivated layer of the pixel electrode (7) (6) with
Drain electrode (5) is contacted.
9. array base palte according to claim 8, it is characterised in that：Line width one that at least the line is busy in the step S05 body (9)
Half part wire body partly overlaps with scanning string holes (8), and remaining part wire body of wire body (9) partly overlaps simultaneously with active layer (3)
Overlap joint.
10. array base palte according to claim 8 or claim 9, it is characterised in that：In the step S05 in active layer (3) at least
There are a lateral edges to be located at a side edge-justified calibrations at wire body (9) place with scanning string holes (8).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710464019.5A CN107153308B (en) | 2017-06-19 | 2017-06-19 | Array substrate and manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710464019.5A CN107153308B (en) | 2017-06-19 | 2017-06-19 | Array substrate and manufacturing method |
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| CN107153308A true CN107153308A (en) | 2017-09-12 |
| CN107153308B CN107153308B (en) | 2020-08-28 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109240017A (en) * | 2018-11-22 | 2019-01-18 | 上海天马微电子有限公司 | Display panel and display device |
| WO2019072189A1 (en) * | 2017-10-13 | 2019-04-18 | 京东方科技集团股份有限公司 | Testing circuit, array substrate, display panel and display device |
| CN109828419A (en) * | 2019-04-08 | 2019-05-31 | 惠科股份有限公司 | Array substrate and manufacturing method thereof |
| WO2020056845A1 (en) * | 2018-09-17 | 2020-03-26 | 重庆惠科金渝光电科技有限公司 | Array substrate, display panel and display device |
| CN112379552A (en) * | 2020-12-03 | 2021-02-19 | 深圳市华星光电半导体显示技术有限公司 | Display panel and manufacturing method thereof |
| CN113936564A (en) * | 2021-10-09 | 2022-01-14 | 惠州华星光电显示有限公司 | Display panel and display terminal |
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