CN105824160A - Display panel - Google Patents
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- CN105824160A CN105824160A CN201510008774.3A CN201510008774A CN105824160A CN 105824160 A CN105824160 A CN 105824160A CN 201510008774 A CN201510008774 A CN 201510008774A CN 105824160 A CN105824160 A CN 105824160A
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Abstract
The present invention discloses a display panel. Scanning lines and data line are staggeredly disposed on a substrate, an active layer is disposed on the substrate and positioned between the data lines and the substrate, and a transparent conducting layer is disposed on the substrate and positioned over the active layer. The active layer comprises a first connecting hole area electrically connected with the data lines, a second connecting hole area electrically connected with the transparent conducting layer, and an intermediate connecting area positioned between the first connecting hole area and the second connecting hole area. Positions where the intermediate connecting area and the scanning line are overlapped are channel regions, positions where the intermediate connecting area and the scanning line are not overlapped are non-channel regions, and the width of the non-channel regions is larger than the width of the channel regions.
Description
Technical field
The present invention relates to display floater technology, particularly relate to use the active layer design of the display floater of the active layer of low temperature polycrystalline silicon making thin film transistor (TFT).
Background technology
In recent years, liquid crystal display, because having the advantages such as slimming, lightweight, low-power consume and Low emissivity, has become as topmost flat-panel screens, and is widely used in various electronic installation.In the liquid crystal display of active matrix, thin film transistor (TFT) (thin-filmtransistor；TFT) as controlling the driving element that pixel switches, according to the active layer material of thin film transistor (TFT), thin film transistor (TFT) can be divided into two classes: one type is amorphous silicon film transistor, another kind of is polycrystalline SiTFT.
In technology previously, manufacture polycrystalline SiTFT to need to use the high temperature higher than 1000 degree, make amorphous silicon layer melted and recrystallize into as polysilicon layer, but, development along with laser technology, the processing technology temperature that can be used below 600 degree at present forms polysilicon layer, and this manufacturing technology is referred to as low temperature polycrystalline silicon (low-temperaturepolysilicon；LTPS) thin-film transistor technologies.
Low-temperature polysilicon film transistor has carrier mobility faster compared to amorphous silicon film transistor, therefore uses the liquid crystal display of low-temperature polysilicon film transistor manufacture to have the advantages such as high-effect, short response time.
But, for using the liquid crystal display that low temperature polycrystalline silicon makes, the low temperature polycrystalline silicon of the active layer forming thin film transistor (TFT) also has the place that many can be improved, so that liquid crystal display reaches more preferably display quality.
Summary of the invention
It is an object of the invention to provide a kind of display floater the low-temperature polysilicon silicon active layer of thin film transistor (TFT) is improved, the pattern width utilizing low-temperature polysilicon silicon active layer designs, the overall resistance allowing low-temperature polysilicon silicon active layer reduces, thus can improve the electric characteristics of thin film transistor (TFT), and then improve the image display quality of display floater.
For reaching above-mentioned purpose, in some embodiments of the invention, it is provided that display floater, including: first substrate；Scan line and data wire are crisscross arranged on first substrate；Active layer is arranged on first substrate, and active layer is between data wire and first substrate；And first transparency conducting layer be arranged on first substrate, and first transparency conducting layer be positioned at above active layer, wherein active layer includes: first connects porose area electrically connects with data wire, second connects porose area and the electrical connection of the first transparency conducting layer, and middle attachment zone connects porose area and second first and connects between porose area, middle attachment zone and scan line overlapping comprise first passage district, and middle attachment zone and this scan line not overlapping are non-channel region, and the width of non-channel region is more than the width in first passage district.
Accompanying drawing explanation
Fig. 1 is the part plan schematic diagram of the display floater of some embodiments of the present invention；
Fig. 2 is the some embodiments of the present invention partial cutaway schematic along the display floater of the hatching 2-2 ' of Fig. 1；
Fig. 3 is the part plan schematic diagram of the display floater of other embodiments of the present invention；
Fig. 4 is the some embodiments of the present invention partial cutaway schematic along the display floater of the hatching 4-4 ' of Fig. 3；
Fig. 5 is the part plan schematic diagram of the display floater of some other embodiments of the present invention；
Fig. 6 is the part plan schematic diagram of the display floater of some other embodiments of the present invention.
Symbol description
100～display floater；
101～first substrate；
102～second substrate；
1301～first connect porose area；
1302～second connect porose area；
1303～middle attachment zone；
1303-L1,1303-L2～the side of middle attachment zone；
1304～the first non-channel region；
1305～the second non-channel region；
1306～the 3rd non-channel region；
1307～protuberance；
1308～first passage district；
1309～second channel district；
1311～firstth district；
1312～secondth district；
110～first transparency conducting layer；
113～first slit of transparency conducting layer；
115,117,119～via；
117-1,119-1～bottom margin；
117-2,119-2～top；
120～second transparency conducting layer；
122～second slit of transparency conducting layer；
125～second opening of transparency conducting layer；
126～first insulating barrier；
128～second insulating barrier；
132～the 3rd insulating barrier；
134～the 4th insulating barrier；
130～active layer；
136～display dielectric layer；
140～scan line；
150～data wire；
152～drain electrode；
W1～the width in first passage district；
W2～the width in second channel district；
W3～the width of the 3rd non-channel region；
W4～the width in the firstth district；
W5～the width in the secondth district；
W6～the width of the first non-channel region；
W7～the width of the second non-channel region；
W8～first connects the width of porose area；
W9～second connects the width of porose area.
Detailed description of the invention
Fig. 1 shows according to some embodiments of the present invention, the part plan schematic diagram of display floater 100, display floater 100 comprises multi-strip scanning line 140 and is arranged at intermeshing on first substrate (Fig. 1 does not draws) to define repeatedly pixel region with a plurality of data lines 150.In the present embodiment, sub-pixel region is the region that adjacent data line surrounds with adjacent scanning lines.The staggered place being adjacent to scan line 140 and data wire 150 is provided with thin film transistor (TFT), and thin film transistor (TFT) is in order to control sub-pixel region and the switch element electrically connected with data wire.According to embodiments of the invention, thin film transistor (TFT) comprises the active layer 130 made with low temperature polycrystalline silicon, active layer 130 comprises and first connects porose area 1301, second connects porose area 1302, and connects, first, the middle attachment zone 1303 that porose area 1301 and second connects between porose area 1302.The middle attachment zone 1303 of active layer 130 produces two channel regions with scan line 140 overlapping, it is respectively first passage district 1308 and second channel district 1309, the middle attachment zone 1303 of active layer 130 and scan line 140 not overlapping be then non-channel region, be positioned at the first non-channel region 1304 of close data wire on the upside of scan line 140, be positioned on the upside of scan line further away from the second non-channel region 1305 of data wire and be positioned at the non-channel region 1306 of the 3rd on the downside of scan line 140 as marked in Fig. 1.
In addition, as shown in Figure 1, in certain embodiments, display floater 100 further comprises as the second transparency conducting layer 120 of top transparency conducting layer, in this embodiment, second transparency conducting layer 120 is as common electrode, and the second transparency conducting layer 120 has multiple slit 122 and is formed at wherein, and the second transparency conducting layer 120 covers scan line 140, data wire 150 and active layer 130.In certain embodiments, the second transparency conducting layer 120 covers and is positioned at the first of active layer 130 and connects the via (via) 115 of porose area 1301 and be positioned at the second of active layer 130 and connect the via (via) 117 and 119 of porose area 1302.In further embodiments, second transparency conducting layer 120 can have opening (opening) (not drawing in FIG), this opening is adjacent to the forming position of via 117 and 119, that is second the opening of transparency conducting layer 120 be adjacent to second and connect porose area 1302, and the second transparency conducting layer 120 can be avoided without covering via 117 and 119.In the present embodiment, data wire 150 is non-rectilinear wiring configuration, but this data wire 150 generally has a substantial bearing of trend；In other embodiments, data wire 150 can be straight line wiring configuration.In the present embodiment, scan line 140 is straight line wiring configuration；In other embodiments, scan line 140 can be non-rectilinear wiring configuration, but this scan line 140 generally has a substantial bearing of trend.
As it is shown in figure 1, first passage district 1308 has the first width W1, second channel district 1309 has the second width W2, and the direction of the first width W1 and the second width W2 is the substantially bearing of trend being parallel to scan line 140.The middle attachment zone 1303 part between first passage district 1308 and second channel district 1309, that is the 3rd non-channel region 1306 there is the 3rd width W3, the 3rd width W3 is the vertical dimension between the first side 1303-L1 of middle attachment zone 1303 and second side 1303-L2.First side 1303-L1 refers to that the side inside the middle attachment zone 1303 of active layer 130, second side 1303-L2 refer to the side outside active layer middle attachment zone 1303.
According to embodiments of the invention, the 3rd width W3 of the 3rd non-channel region 1306 is more than the first width W1 in first passage district 1308, and the 3rd width W3 of the 3rd non-channel region 1306 is also greater than the second width W2 in second channel district 1309 simultaneously.In addition, according to embodiments of the invention, the width of middle attachment zone 1303 and the nonoverlapping first non-channel region 1304 of scan line 140 and the second non-channel region 1305 is more than the first width W1 in first passage district 1308, and the width of the first non-channel region 1304 and the second non-channel region 1305 is also greater than the second width W2 in second channel district 1309.In an embodiment of the present invention, the width of each several part of middle attachment zone 1303 is defined as the vertical dimension between two side 1303-L1 and 1303-L2 of middle attachment zone 1303, and therefore the direction of the some parts of width of middle attachment zone 1303 can be not parallel to the bearing of trend of scan line 140.
In order to meet the thin film transistor (TFT) functional requirement as pixel switch element, produced by the active layer 130 of thin film transistor (TFT) and the overlapping of scan line 140, the length and width ratio in first passage district 1308 and the length and width ratio in second channel district 1309 are required for maintaining in certain ratio range, and therefore the first width W1 in first passage the district 1308 and second width W2 in second channel district 1309 need to meet the resolution of the display floater design requirement to the passage aspect ratio of thin film transistor (TFT).In known display floater manufacturing technology, the active layer of thin film transistor (TFT) is in addition to the part connecing porose area, remainder has consistent width, the width that generally width of active layer uses the length and width ratio meeting channel region to require makes, but, the resistance using the active layer that this mode makes cannot reduce, and causes the usefulness of thin film transistor (TFT) to promote.
According to embodiments of the invention, first non-channel region the 1304, second non-channel region 1305 of active layer 130 and the width of the 3rd non-channel region 1306 are more than the width in first passage district 1308, width also greater than second channel district 1309 so that the pattern of active layer 130 has the wide thin change that non-channel region is wider and channel region is narrower.Via first non-channel region the 1304, second non-channel region 1305 and the 3rd non-channel region 1306 that width is bigger, the overall resistance of the active layer 130 being made up of low temperature polycrystalline silicon can be reduced, simultaneously, the width in first passage district 1308 and second channel district 1309 also complies with the Aspect Ratio requirement of the channel region of thin film transistor (TFT), therefore, embodiments of the invention can promote the electrical property efficiency of thin film transistor (TFT).
In certain embodiments, as shown in Figure 1, the middle attachment zone 1303 the 3rd non-channel region 1306 between first passage district 1308 and second channel district 1309 has two protuberances 1307, and the two protuberance 1307 protrudes from outside first passage district 1308 and second channel district 1309 on the direction being parallel to scan line 140 respectively.It addition, in certain embodiments, the width W1 in first passage the district 1308 and width W2 in second channel district 1309 can be with rough identical.In some other embodiments, the width W1 in first passage district 1308 then can be different from the width W2 in second channel district 1309.In addition, as it is shown in figure 1, in certain embodiments, data wire 150 can be the data wire with bending curve, and the first of active layer 130 connects porose area 1301 and second and connect porose area 1302 and be more or less the same from the distance of scan line 140, form the active layer 130 that the length of middle attachment zone 1303 is shorter.
Fig. 2 shows according to some embodiments of the present invention, along the hatching 2-2 ' of Fig. 1, the partial cutaway schematic of display floater 100.As shown in Figure 2, display floater 100 comprises first substrate 101, scan line 140 and data wire 150 are arranged on first substrate 101, active layer 130 is arranged on first substrate 101, and active layer 130 is positioned at below data wire 150 and scan line 140, active layer 130 is between data wire 150 and first substrate 101 simultaneously.In certain embodiments, the thin film transistor (TFT) of display floater 100 can be top grid (top-gate) structure, as in figure 2 it is shown, channel region produced by scan line (grid) 140 and active layer 130 overlapping is positioned at above active layer 130.In further embodiments, the thin film transistor (TFT) of display floater 100 can be bottom grid (bottom-gate) structure, and channel region produced by its scan line (grid) and active layer overlapping is positioned at below active layer.
Refering to Fig. 1 and Fig. 2, connecing porose area 1301 at the first of active layer 130 and be formed above via (viahole) 115, the first of active layer 130 connects porose area 1301 and electrically connects with data wire 150 via via 115.In addition, as shown in Figure 2, display floater 100 also comprises the first transparency conducting layer 110, connects porose area 1302 at the second of active layer 130 and is formed above via 117 and 119, and the second of active layer 130 connects porose area 1302 and be electrically connected to the first transparency conducting layer 110 via via 117 and 119.Via 115 is to be formed at the first of active layer 130 to connect the first insulating barrier 126 above porose area 1301 and the hole in the second insulating barrier 128, the metal material forming data wire 150 is filled in via 115, make data wire 150 can connect porose area 1301 via via 115 with the first of active layer 130 to electrically connect, and a part for data wire 150 forms the source electrode (sourceelectrode) of thin film transistor (TFT).Additionally, via 117 is to be formed at the second of active layer 130 to connect the first insulating barrier 126 above porose area 1302 and the hole in the second insulating barrier 128, and the metal material of the drain electrode (drainelectrode) 152 forming thin film transistor (TFT) can be connected with active layer 130 via via 117.Additionally, via 119 is the hole being formed in the 3rd insulating barrier 132 above the second insulating barrier 128, and the material forming the first transparency conducting layer 110 is filled in via 119, make the first transparency conducting layer 110 can be electrically connected to the drain electrode 152 of thin film transistor (TFT) via via 119, be then electrically connected to the second of active layer 130 via via 117 and connect porose area 1302.First insulating barrier 126 and the second insulating barrier 128 can be identical or different inorganic material, for example, SiOxOr SiNx。
As shown in Figure 2, there is between the bigrid that active layer 130 and scan line 140 are formed the first insulating barrier 126, it is formed above the second insulating barrier 128 and the 3rd insulating barrier 132 in scan line 140, via 115 and 117 is formed in the first insulating barrier 126 and the second insulating barrier 128, via 119 is then formed in the 3rd insulating barrier 132, in certain embodiments, a part for first transparency conducting layer 110 can be conformally formed in the via 119 of the 3rd insulating barrier 132, and the metal material forming the source electrode of thin film transistor (TFT) can be conformally formed in via 115, and the metal material forming the drain electrode 152 of thin film transistor (TFT) also can be conformally formed in via 117.3rd insulating barrier 132 can be organic material, can be used for planarizing, such as, can be organic material (the most poly-Fluoroalkyloxy polyfluoroalkoxy, PFA) or chromatic filter layer (ColorFilter) material.
Display floater 100 also comprises second substrate 102, and display dielectric layer 136 is arranged between second substrate 102 and first substrate 101.In certain embodiments, display dielectric layer 136 can be liquid crystal layer, and second substrate 102 can be colored filter (colorfilter；CF) substrate, first substrate 101 is then thin film transistor (TFT) array (Array) substrate.In further embodiments, chromatic filter layer may be disposed on first substrate 101, and the such as the 3rd insulating barrier 132 can use colorized optical filtering layer material to replace it.
In certain embodiments, as depicted in figs. 1 and 2, display floater 100 also comprises the second transparency conducting layer 120 and is positioned at above the first transparency conducting layer 110, and between the first transparency conducting layer 110 and the second transparency conducting layer 120, there is the 4th insulating barrier 134, first transparency conducting layer 110 is electrically insulated with the second transparency conducting layer 120 by the 4th insulating barrier 134,4th insulating barrier 134 can be inorganic material, such as silicon oxide sioxOr silicon nitride SiNx.In certain embodiments, second transparency conducting layer 120 is the patterned electrodes comprising multiple slit 122, slit 122 and the setting of the first transparency conducting layer 110 via the second transparency conducting layer 120 so that display floater 100 becomes boundary electric field switching (FringeFieldSwitching；FFS) liquid crystal display panel with wide visual angle.In this embodiment, slit 122 is not out sub-pixel regional extent；In other embodiments, slit 122 can exceed sub-pixel regional extent, such as, may span across data wire 150 or may span across scan line 140.
Fig. 3 is other embodiments according to the present invention, the part plan schematic diagram of display floater 100, the middle attachment zone 1303 of active layer 130 produces two channel regions with scan line 140 overlapping, being respectively first passage district 1308 and second channel district 1309, middle attachment zone 1303 and the scan line 140 not overlapping of active layer 130 are then first non-channel region the 1304, second non-channel region 1305 and the 3rd non-channel region 1306.According to embodiments of the invention, the width of first non-channel region the 1304, second non-channel region 1305 and the 3rd non-channel region 1306 is more than first passage district 1308 and the width in second channel district 1309, the pattern making active layer 130 has the wide thin change that non-channel region is wider and channel region is narrower, thus reduces effect of the resistance of active layer.
As it is shown on figure 3, in certain embodiments, the first of active layer 130 connect porose area 1301 connect porose area 1302 compared to second must be away from scan line 140 so that first connects the non-channel region of first between porose area 1301 and scan line 140 1304 has longer length.Because the first non-channel region 1304 is longer compared to what the length of the 3rd non-channel region 1306 was come, therefore can stagger and first connect porose area 1301 and second and connect porose area 1302, because connecing the area relatively big (retaining the bit errors in processing technology) that porose area needs, therefore stagger and two can be allowed to connect porose area be closer on parallel scan lines 140 direction, single sub-pixel width on parallel scan lines 140 direction can be reduced.But because the first non-channel region 1304 length is longer, if maintenance fixed width, the sub-pixel quantity that can arrange may be reduced, and then limit the resolution design requirement of display floater, therefore, make the first non-channel region 1304 have different in width (but coming wide than channel region), both can maintain resistance, it is possible to reduce the impact on aperture opening ratio.
In certain embodiments, as shown in Figure 3, data wire 150 can be the data wire with straight curve, and the middle attachment zone 1303 of active layer 130 partly overlaps with data wire 150, make middle attachment zone 1303 and the nonoverlapping part of data wire 150 have the first district 1311 and the second district 1312 lays respectively at the both sides of data wire 150, wherein the second district 1312 connects between porose area 1302 at data wire 150 and second, and the first district 1311 is then positioned at the opposite side that data wire 150 is different with the second district 1312.First district 1311 has width W4, and the second district 1312 has width W5, and the direction of width W4 and width W5 is roughly parallel to the essence bearing of trend of scan line 140.In certain embodiments, the width W4 in the first district 1311 and width W5 in the second district 1312 is rough equal.In further embodiments, the width W4 in the first district 1311 can be more than the width W5 in the second district 1312.In some other embodiments, the width W4 in the first district 1311 can be less than the width W5 in the second district 1312.
Being compared to the example that active layer is completely overlapped with data wire, in some embodiments of the invention, the middle attachment zone 1303 of active layer 130 partly overlaps with data wire 150, can reduce the parasitic capacitance produced between active layer 130 and data wire 150.Additionally, the example staggered completely compared to active layer and data wire, in some embodiments of the invention, the middle attachment zone 1303 of active layer 130 partly overlaps with data wire 150, can increase the aperture opening ratio of display floater.
In addition, in certain embodiments, as shown in Figure 3, first non-channel region 1304 of the middle attachment zone 1303 of active layer 130 connects adjacent to first has width W6 at porose area 1301, and the second non-channel region 1305 of middle attachment zone 1303 connects adjacent to second and has width W7 at porose area 1302, and width W6 is more than width W7.It addition, in certain embodiments, first connects porose area 1301 has a width W8, and second connects porose area 1302 and have width W9, and width W9 is more than width W8.In certain embodiments, the direction of above-mentioned width W4～W9 is roughly parallel to the direction substantially extended of scan line 140.
Fig. 4 is according to some embodiments of the present invention, along the hatching 4-4 ' of Fig. 3, the partial cutaway schematic of display floater 100.As shown in Figure 4, in certain embodiments, being electrically connected to the second of active layer 130 and connecing the first transparency conducting layer 110 of porose area 1302 is the patterned electrodes comprising multiple slit 113, second transparency conducting layer 120 is positioned at below the first transparency conducting layer 110, and the second transparency conducting layer 120 has opening 125 and is adjacent to second and connects at porose area 1302, and the setting of opening 125 can allow the second transparency conducting layer 120 will not cover via 119 and then avoid via 119 position.In this embodiment, via slit 113 and the setting of the second transparency conducting layer 120 of the first transparency conducting layer 110 so that display floater 100 becomes the display panels of boundary electric field switching (FFS).
Fig. 5 is other embodiments according to the present invention, the part plan schematic diagram of display floater 100, as shown in Figure 5, in certain embodiments, the first of active layer 130 connects porose area 1301 away from scan line 140 so that first connects porose area 1301 and second connects the first non-channel region 1304 of the middle attachment zone 1303 between porose area 1302 and have longer length.In addition, in the 5 embodiment of figure 5, data wire 150 can be the wiring configuration with bending curve, data wire 150 generally has a substantial bearing of trend, the middle attachment zone 1303 making active layer 130 partly overlaps with data wire 150, middle attachment zone 1303 can comprise two regions and lay respectively at the both sides of data wire 150, in this embodiment, middle attachment zone 1303 is positioned at the region on the left of data wire 150 and is positioned at the region on the right side of data wire 150 compared to middle attachment zone 1303 and has bigger width.In addition, as shown in Figure 5, it is positioned at the second of active layer 130 to connect the via 117 of porose area 1302 there is bottom margin (or claiming through hole lower edge) 117-1 and top (or claiming through hole upper limb) 117-2, wherein bottom margin 117-1 around area less than top 117-2 around area, therefore, in the plane graph shown in Fig. 5, via 117 has two ring-type borders.Via 115, via 119 also have top and bottom margin, only illustrate the top of via in Fig. 1, Fig. 3, Fig. 5.
In the 5 embodiment of figure 5, middle attachment zone 1303 produced first non-channel region 1304, second non-channel region 1305 the most overlapping with the scan line 140 produced first passage district 1308 overlapping with scan line 140 more than middle attachment zone 1303 with the width of the 3rd non-channel region 1306 of active layer 130 and the width in second channel district 1309, the pattern making active layer 130 has the wide thin change that non-channel region is wider and channel region is narrower, thus reduces the resistance of active layer and effect of parasitic capacitance.
Additionally, the most do not draw the first transparency conducting layer and second transparency conducting layer of display floater 100, in certain embodiments, the display floater 100 of Fig. 5 can use the patterned electrodes of the second transparency conducting layer 120 comprising slit 122 as shown in Figure 1, forms the display panels of boundary electric field switching (FFS).In further embodiments, the display floater 100 of Fig. 5 may be used without the patterned electrodes of the first transparency conducting layer 110 comprising slit 113 as shown in Figure 3, forms the display panels of boundary electric field switching (FFS).
nullFig. 6 is other embodiments according to the present invention，The part plan schematic diagram of display floater 100，As shown in Figure 6，In certain embodiments，The first of active layer 130 connects porose area 1301 near scan line 140，Make first to connect porose area 1301 and second and connect the non-channel region of first between porose area 1,302 1304 and the second non-channel region 1305 has shorter length，But the first non-channel region 1304 length is more than the second non-channel region 1305 length，Thus can stagger and first connect porose area 1301 and second and connect the position of porose area 1302 to reduce the impact on resolution，This is because connect porose area need to occupy larger area，If two connect porose area and are arranged side by side，Then may need bigger sub-pixel width (being parallel on the essence bearing of trend of scan line) that first could be accommodated to connect porose area 1301 and second and connect porose area 1302，So will limit the quantity of sub-pixel，And then affect the display floater design requirement to high-resolution.In this embodiment, the middle attachment zone 1303 of active layer 130 connects adjacent to first has width W6 at porose area 1301, and middle attachment zone 1303 connects adjacent to second and has width W7 at porose area 1302, and width W6 is more than width W7.Additionally, scan line 140 and data wire 150 can be straight line wiring patterns.In other embodiments, scan line 140 and data wire 150 can non-be straight lines, but scan line 140 and data wire 150 are generally respectively provided with a substantial bearing of trend.
In addition, as shown in Figure 6, it is positioned at the second of active layer 130 to connect the via 117 of porose area 1302 there is bottom margin (or claiming through hole lower edge) 117-1 and top (or claiming through hole upper limb) 117-2, wherein bottom margin 117-1 around area less than top 117-2 around area, and be positioned at the second of active layer 130 and connect the via 119 of porose area 1302 also there is bottom margin (or claiming through hole lower edge) 119-1 and top (or claiming through hole upper limb) 119-2, wherein bottom margin 119-1 around area less than top 119-2 around area, therefore in the plane graph shown in Fig. 6, via 117 and via 119 are respectively provided with two ring-type borders.In other embodiments, via can be non-circular, such as, can be oval or irregular shape.
In the embodiment in fig 6, middle attachment zone 1303 produced first non-channel region 1304, second non-channel region 1305 the most overlapping with the scan line 140 produced first passage district 1308 overlapping with scan line 140 more than middle attachment zone 1303 with the width of the 3rd non-channel region 1306 of active layer 130 and the width in second channel district 1309, the pattern making active layer 130 has the wide thin change that non-channel region is wider and channel region is narrower, thus reduces the resistance of active layer and effect of parasitic capacitance.
It addition, the most do not draw the first transparency conducting layer and second transparency conducting layer of display floater 100, in certain embodiments, the display floater 100 of Fig. 6 can use the patterned electrodes of the second transparency conducting layer 120 comprising slit 122 as shown in Figure 1；In further embodiments, the slit 122 of the second transparency conducting layer 120 of the display floater 100 of Fig. 6 can not interrupt and crosses over data wire or cross over scan line, and end regards design requirement.In further embodiments, the display floater 100 of Fig. 6 may be used without the patterned electrodes of the first transparency conducting layer 110 comprising slit 113 as shown in Figure 3, to form the display panels of boundary electric field switching (FFS).
In sum, according to some embodiments of the present invention, the pattern of the active layer of the thin film transistor (TFT) of display floater is improved, especially for the active layer being made up of low temperature polycrystalline silicon, allow the first of active layer connect the width of porose area and the second middle attachment zone connecing between porose area produced non-channel region the most overlapping with scan line overlapping with scan line more than middle attachment zone produced by the width of channel region, the pattern making active layer has the wide thin change that non-channel region is wider and channel region is narrower, thus reduce the resistance of active layer and effect of parasitic capacitance, to promote the electrical property efficiency of thin film transistor (TFT).
Although disclosing the present invention in conjunction with preferred embodiment above, but it being not limited to the present invention, those having an ordinary knowledge in this technical field are when it can be appreciated that without departing from the spirit and scope of the present invention, can do a little change and retouching.Therefore, protection scope of the present invention should be with being as the criterion that the claim enclosed is defined.
Claims (17)
1. a display floater, including:
First substrate；
Scan line and data wire, be crisscross arranged on this first substrate；
Active layer, is arranged on this first substrate, and this active layer is between this data wire and this first substrate；And
First transparency conducting layer, is arranged on this first substrate, and this first transparency conducting layer is positioned at above this active layer,
Wherein this active layer includes:
First connects porose area, electrically connects with this data wire；
Second connects porose area, electrically connects with this first transparency conducting layer；And
Middle attachment zone, first connects porose area and this second connects between porose area at this,
Wherein this middle attachment zone and this scan line overlapping comprise a first passage district, and this middle attachment zone and this scan line not overlapping are a non-channel region, and the width of this non-channel region is more than the width in this first passage district.
2. display floater as claimed in claim 1, wherein this middle attachment zone partly overlaps with this data wire, and this middle attachment zone comprises the firstth district and the secondth district lays respectively at the both sides of this data wire, wherein this secondth district is positioned at this data wire and this second connects between porose area.
3. display floater as claimed in claim 2, wherein the width in this firstth district is equal with the width in this secondth district.
4. display floater as claimed in claim 2, wherein the width in this firstth district is more than the width in this secondth district.
5. display floater as claimed in claim 2, wherein the width in this firstth district is less than the width in this secondth district.
6. display floater as claimed in claim 1, wherein this middle attachment zone first connects width of porose area more than this middle attachment zone adjacent to this second width connecing porose area adjacent to this.
7. display floater as claimed in claim 1, wherein this second connects width of porose area more than this first width connecing porose area, and those width be oriented parallel to this scan line.
8. display floater as claimed in claim 1, wherein this middle attachment zone and this scan line overlapping also comprise second channel district, and the width of this non-channel region is more than the width in this second channel district.
9. display floater as claimed in claim 8, wherein the width in this second channel district is different from the width in this first passage district.
10. display floater as claimed in claim 8, wherein the width in this second channel district is identical with the width in this first passage district.
11. display floaters as claimed in claim 8, wherein a part for this middle attachment zone is between this first passage district and this second channel district, the width of this part of this middle attachment zone is more than the width in this first passage district, and the width of this part of this middle attachment zone is more than the width in this second channel district.
12. display floaters as claimed in claim 11, wherein this part of this middle attachment zone has two protuberances, and these two protuberances protrude from this first passage district and this second channel district on the direction be parallel to this scan line respectively.
13. display floaters as claimed in claim 1, also include:
Second substrate, is arranged oppositely with this first substrate；And
Display medium, is arranged between this first substrate and this second substrate.
14. display floaters as claimed in claim 1, also include the second transparency conducting layer, are arranged on this first substrate, and this second transparency conducting layer is positioned at above this first transparency conducting layer.
15. display floaters as claimed in claim 14, wherein this second transparency conducting layer is a patterned electrodes comprising multiple slit.
16. display floaters as claimed in claim 1, also include the second transparency conducting layer, are arranged on this first substrate, and this second transparency conducting layer is positioned at below this first transparency conducting layer.
17. display floaters as claimed in claim 16, wherein this first transparency conducting layer is a patterned electrodes comprising multiple slit, and this second transparency conducting layer has an opening and is adjacent to this and second connects porose area.
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| CN201510008774.3A CN105824160B (en) | 2015-01-08 | 2015-01-08 | Display panel |
| CN202010428830.XA CN111665669A (en) | 2015-01-08 | 2015-01-08 | Display panel |
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| CN201510008774.3A CN105824160B (en) | 2015-01-08 | 2015-01-08 | Display panel |
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| CN202010428830.XA Division CN111665669A (en) | 2015-01-08 | 2015-01-08 | Display panel |
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Also Published As
| Publication number | Publication date |
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| CN111665669A (en) | 2020-09-15 |
| CN105824160B (en) | 2020-06-16 |
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