CN111665669A - Display panel - Google Patents
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- CN111665669A CN111665669A CN202010428830.XA CN202010428830A CN111665669A CN 111665669 A CN111665669 A CN 111665669A CN 202010428830 A CN202010428830 A CN 202010428830A CN 111665669 A CN111665669 A CN 111665669A
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Abstract
The invention discloses a display panel, which comprises scanning lines and data lines which are arranged on a substrate in a staggered manner, an active layer which is arranged on the substrate and is positioned between the data lines and the substrate, and a transparent conducting layer which is arranged on the substrate and is positioned above the active layer, wherein the active layer comprises a first connecting hole area which is electrically connected with the data lines, a second connecting hole area which is electrically connected with the transparent conducting layer, an intermediate connecting area which is positioned between the first connecting hole area and the second connecting hole area, the overlapping part of the intermediate connecting area and the scanning lines is a channel area, the non-overlapping part of the intermediate connecting area and the scanning lines is a non-channel area, and the width of the non-channel area is larger than that of the channel area.
Description
The application is a divisional application of Chinese invention patent application (application number: 201510008774.3, application date: 2015, 01, 08 and title: display panel).
Technical Field
The present invention relates to a display panel technology, and more particularly, to an active layer pattern design of a display panel in which an active layer of a thin film transistor is formed using low temperature polysilicon.
Background
In recent years, liquid crystal displays have become the most dominant flat panel displays because of their advantages such as thinness, lightweight, low power consumption, and low radiation, and are widely used in various electronic devices. In an active matrix liquid crystal display, a thin-film transistor (TFT) is used as a driving element for controlling switching of pixels, and the TFT may be classified into two types according to an active layer material of the TFT: one type is an amorphous silicon thin film transistor, and the other type is a polycrystalline silicon thin film transistor.
In the prior art, high temperature higher than 1000 ℃ is required to melt and recrystallize the amorphous silicon layer into a polysilicon layer in the manufacture of the polysilicon thin film transistor, however, with the development of laser technology, the polysilicon layer can be formed at a fabrication process temperature lower than 600 ℃, which is called low-temperature polysilicon (LTPS) thin film transistor technology.
The low temperature polysilicon thin film transistor has a faster carrier mobility than the amorphous silicon thin film transistor, so that the liquid crystal display manufactured by using the low temperature polysilicon thin film transistor has the advantages of high efficiency, short response time and the like.
However, there are many areas where the low temperature polysilicon forming the active layer of the thin film transistor can be improved for the liquid crystal display made using the low temperature polysilicon, so that the liquid crystal display achieves better display quality.
Disclosure of Invention
The invention aims to provide a display panel for improving a low-temperature polysilicon active layer of a thin film transistor, and the overall resistance value of the low-temperature polysilicon active layer is reduced by utilizing the pattern width design of the low-temperature polysilicon active layer, so that the electrical property of the thin film transistor can be improved, and the image display quality of the display panel is further improved.
To achieve the above object, in some embodiments of the present invention, there is provided a display panel including: a first substrate; the scanning lines and the data lines are arranged on the first substrate in a staggered mode; the active layer is arranged on the first substrate, and the active layer is positioned between the data line and the first substrate; and the first transparent conducting layer is arranged on the first substrate, and the first transparent conducting layer is positioned above the active layer, wherein the active layer comprises: the first connection hole area is electrically connected with the data line, the second connection hole area is electrically connected with the first transparent conductive layer, the middle connection area is positioned between the first connection hole area and the second connection hole area, the overlapping part of the middle connection area and the scanning line comprises a first channel area, the non-overlapping part of the middle connection area and the scanning line is a non-channel area, and the width of the non-channel area is larger than that of the first channel area.
Drawings
FIG. 1 is a schematic partial plan view of a display panel according to some embodiments of the invention;
FIG. 2 is a partial cross-sectional view of the display panel along section line 2-2' of FIG. 1 according to some embodiments of the present invention;
FIG. 3 is a schematic partial plan view of a display panel according to further embodiments of the present invention;
FIG. 4 is a partial cross-sectional view of the display panel along section line 4-4' of FIG. 3 according to some embodiments of the present invention;
FIG. 5 is a schematic partial plan view of a display panel according to some other embodiments of the invention;
fig. 6 is a partial schematic plan view of a display panel according to some other embodiments of the invention.
Description of the symbols
100-a display panel;
101-a first substrate;
102 to a second substrate;
1301-a first via area;
1302-a second via area;
1303 to the middle connecting region;
1303-L1, 1303-L2 to the side of the middle attachment zone;
1304 to a first non-channel region;
1305 to a second non-channel region;
1306 to a third non-channel region;
1307-projection;
1308 to a first channel region;
1309-second channel zone;
1311 to a first zone;
1312 to a second region;
110 to a first transparent conductive layer;
113 to a slit of the first transparent conductive layer;
115. 117, 119-via holes;
117-1, 119-1 to bottom edge;
117-2, 119-2 to the top edge;
120 to a second transparent conductive layer;
122 to a slit of the second transparent conductive layer;
125 to an opening of the second transparent conductive layer;
126 to a first insulating layer;
128 to a second insulating layer;
132 to a third insulating layer;
134 to a fourth insulating layer;
130-active layer;
136-display dielectric layer;
140-scanning lines;
150-data line;
152-a drain electrode;
w1 width of first channel region;
w2 width of second channel region;
w3 width of third non-channel region;
w4 width of first zone;
w5 width of second zone;
w6 width of first non-channel region;
w7 width of second non-channel region;
w8 width of first via region;
w9 width of second via region.
Detailed Description
Fig. 1 is a partial plan view of a display panel 100 according to some embodiments of the invention, in which the display panel 100 includes a plurality of scan lines 140 and a plurality of data lines 150 alternately disposed on a first substrate (not shown in fig. 1) to define a plurality of pixel regions. In this embodiment, the sub-pixel region is a region surrounded by the adjacent data line and the adjacent scan line. A thin film transistor is disposed adjacent to the intersection of the scan line 140 and the data line 150, and the thin film transistor is used to control the sub-pixel region and is electrically connected to the switch element of the data line. According to an embodiment of the present invention, the tft includes an active layer 130 made of low temperature polysilicon, the active layer 130 includes a first contact hole region 1301, a second contact hole region 1302, and an intermediate connection region 1303 located between the first contact hole region 1301 and the second contact hole region 1302. Two channel regions, namely a first channel region 1308 and a second channel region 1309, are generated at the overlapping position of the middle connection region 1303 of the active layer 130 and the scan line 140, and a non-channel region is generated at the non-overlapping position of the middle connection region 1303 of the active layer 130 and the scan line 140, as indicated in fig. 1, a first non-channel region 1304 located at the upper side of the scan line 140 near the data line, a second non-channel region 1305 located at the upper side of the scan line farther from the data line, and a third non-channel region 1306 located at the lower side of the scan line 140.
In addition, as shown in fig. 1, in some embodiments, the display panel 100 further includes a second transparent conductive layer 120 as an upper transparent conductive layer, in which the second transparent conductive layer 120 serves as a common electrode, the second transparent conductive layer 120 has a plurality of slits 122 formed therein, and the second transparent conductive layer 120 covers the scan lines 140, the data lines 150 and the active layer 130. In some embodiments, the second transparent conductive layer 120 covers the via hole (via)115 located at the first connection hole region 1301 of the active layer 130 and the via holes (via)117 and 119 located at the second connection hole region 1302 of the active layer 130. In other embodiments, the second transparent conductive layer 120 may have an opening (not shown in fig. 1) adjacent to the formation position of the via holes 117 and 119, i.e., the opening of the second transparent conductive layer 120 is adjacent to the second hole region 1302, and the second transparent conductive layer 120 can avoid covering the via holes 117 and 119. In the present embodiment, the data line 150 is in a non-linear layout, but the data line 150 generally has a substantially extending direction; in other embodiments, the data line 150 may be in the form of a straight line. In the present embodiment, the scan lines 140 are in the form of straight wiring; in other embodiments, the scan lines 140 may be non-linear, but the scan lines 140 generally have a substantially extending direction.
As shown in fig. 1, the first channel region 1308 has a first width W1, the second channel region 1309 has a second width W2, and the directions of the first width W1 and the second width W2 are parallel to the substantial extending direction of the scan line 140. The portion of the intermediate connecting zone 1303 between the first channel region 1308 and the second channel region 1309, i.e., the third non-channel region 1306, has a third width W3, the third width W3 being the perpendicular distance between the first side edge 1303-L1 and the second side edge 1303-L2 of the intermediate connecting zone 1303. The first side edge 1303-L1 refers to the side edge inside the active layer 130 of the middle connection region 1303, and the second side edge 1303-L2 refers to the side edge outside the active layer middle connection region 1303.
In accordance with an embodiment of the present invention, the third width W3 of the third non-channel region 1306 is greater than the first width W1 of the first channel region 1308, while the third width W3 of the third non-channel region 1306 is also greater than the second width W2 of the second channel region 1309. Further, according to the embodiment of the present invention, the widths of the first non-channel region 1304 and the second non-channel region 1305, in which the intermediate connection region 1303 does not overlap with the scan line 140, are larger than the first width W1 of the first channel region 1308, and the widths of the first non-channel region 1304 and the second non-channel region 1305 are also larger than the second width W2 of the second channel region 1309. In the embodiment of the present invention, the width of each portion of the intermediate connection region 1303 is defined as the perpendicular distance between both side edges 1303-L1 and 1303-L2 of the intermediate connection region 1303, and thus the direction of the width of some portions of the intermediate connection region 1303 may not be parallel to the extending direction of the scan lines 140.
In order to meet the functional requirements of the tft as a pixel switch component, the ratio of the length to the width of the first channel region 1308 and the ratio of the length to the width of the second channel region 1309 generated at the overlapping position of the active layer 130 of the tft and the scan line 140 need to be maintained within a certain ratio range, and therefore the first width W1 of the first channel region 1308 and the second width W2 of the second channel region 1309 need to meet the design requirements of the resolution of the display panel on the channel aspect ratio of the tft. In the conventional display panel manufacturing technology, the active layer of the thin film transistor has a uniform width except for the contact region, and the width of the active layer is usually manufactured by a width that meets the requirement of the aspect ratio of the channel region.
According to an embodiment of the present invention, the widths of the first non-channel region 1304, the second non-channel region 1305 and the third non-channel region 1306 of the active layer 130 are greater than the width of the first channel region 1308 and also greater than the width of the second channel region 1309, so that the pattern of the active layer 130 has a variation in width where the non-channel region is wider and the channel region is narrower. The first non-channel region 1304, the second non-channel region 1305 and the third non-channel region 1306 with larger widths can reduce the overall resistance of the active layer 130 made of low temperature polysilicon, and the widths of the first channel region 1308 and the second channel region 1309 also meet the length-width ratio requirement of the channel region of the thin film transistor, so that the embodiment of the invention can improve the electrical performance of the thin film transistor.
In some embodiments, as shown in FIG. 1, the intermediate connection region 1303 has two protrusions 1307 in a third non-channel region 1306 between the first channel region 1308 and the second channel region 1309, the two protrusions 1307 protruding out of the first channel region 1308 and the second channel region 1309, respectively, in a direction parallel to the scan lines 140. Additionally, in some embodiments, the width W1 of the first channel region 1308 may be about the same as the width W2 of the second channel region 1309. In some other embodiments, the width W1 of the first channel region 1308 may be different than the width W2 of the second channel region 1309. In addition, as shown in fig. 1, in some embodiments, the data line 150 may be a data line having a bending curve, and the distances from the scan line 140 of the first connection hole region 1301 and the second connection hole region 1302 of the active layer 130 are not greatly different, forming the active layer 130 with a shorter length of the intermediate connection region 1303.
FIG. 2 is a partial cross-sectional view of the display panel 100 taken along line 2-2' of FIG. 1 according to some embodiments of the invention. As shown in fig. 2, the display panel 100 includes a first substrate 101, a scan line 140 and a data line 150 disposed on the first substrate 101, an active layer 130 disposed on the first substrate 101, the active layer 130 disposed below the data line 150 and the scan line 140, and the active layer 130 disposed between the data line 150 and the first substrate 101. In some embodiments, the thin film transistor of the display panel 100 may be a top-gate (top-gate) structure, as shown in fig. 2, and the channel region generated where the scan line (gate) 140 overlaps the active layer 130 is located above the active layer 130. In other embodiments, the thin film transistor of the display panel 100 may be a bottom-gate (bottom-gate) structure, and the channel region generated where the scan line (gate) overlaps the active layer is located below the active layer.
Referring to fig. 1 and 2, a via hole (via)115 is formed above the first connection hole region 1301 of the active layer 130, and the first connection hole region 1301 of the active layer 130 is electrically connected to the data line 150 through the via hole 115. In addition, as shown in fig. 2, the display panel 100 further includes a first transparent conductive layer 110, via holes 117 and 119 are formed above the second connection hole region 1302 of the active layer 130, and the second connection hole region 1302 of the active layer 130 is electrically connected to the first transparent conductive layer 110 through the via holes 117 and 119. The via hole 115 is a hole formed in the first insulating layer 126 and the second insulating layer 128 above the first contact hole region 1301 of the active layer 130, a metal material forming the data line 150 is filled in the via hole 115, so that the data line 150 can be electrically connected to the first contact hole region 1301 of the active layer 130 through the via hole 115, and a portion of the data line 150 forms a source electrode (source electrode) of the thin film transistor. In addition, the via hole 117 is a hole formed in the first insulating layer 126 and the second insulating layer 128 above the second connection hole region 1302 of the active layer 130, and the metal material forming the drain electrode (drain) 152 of the thin film transistor may be connected to the active layer 130 through the via hole 117. In addition, the via hole 119 is a hole formed in the third insulating layer 132 above the second insulating layer 128, and the material forming the first transparent conductive layer 110 is filled in the via hole 119, so that the first transparent conductive layer 110 can be electrically connected to the drain electrode 152 of the tft through the via hole 119, and then electrically connected to the second contact hole region 1302 of the active layer 130 through the via hole 117. The first and second insulating layers 126, 128 may be the sameOr a different inorganic material, e.g. SiOxOr is SiNx。
As shown in fig. 2, a first insulating layer 126 is disposed between the active layer 130 and the dual gate formed by the scan line 140, a second insulating layer 128 and a third insulating layer 132 are formed above the scan line 140, via holes 115 and 117 are formed in the first insulating layer 126 and the second insulating layer 128, and a via hole 119 is formed in the third insulating layer 132, in some embodiments, a portion of the first transparent conductive layer 110 may be conformally formed in the via hole 119 of the third insulating layer 132, and a metal material forming a source electrode of a tft may be conformally formed in the via hole 115, and a metal material forming a drain electrode 152 of the tft may also be conformally formed in the via hole 117. The third insulating layer 132 may be an organic material, which may be used for planarization, such as an organic material (e.g., PFA) or a Color Filter (Color Filter) material.
The display panel 100 further includes a second substrate 102, and a display medium layer 136 is disposed between the second substrate 102 and the first substrate 101. In some embodiments, the display medium layer 136 may be a liquid crystal layer, the second substrate 102 may be a Color Filter (CF) substrate, and the first substrate 101 may be a thin film transistor Array (Array) substrate. In other embodiments, a color filter layer may be disposed on the first substrate 101, for example, the third insulating layer 132 may be replaced by a color filter layer material.
In some embodiments, as shown in fig. 1 and 2, the display panel 100 further includes a second transparent conductive layer 120 located above the first transparent conductive layer 110, and a fourth insulating layer 134 is disposed between the first transparent conductive layer 110 and the second transparent conductive layer 120, the first transparent conductive layer 110 is electrically insulated from the second transparent conductive layer 120 by the fourth insulating layer 134, and the fourth insulating layer 134 can be an inorganic material, such as SiO (silicon oxide), for examplexOr silicon nitride SiNx. In some embodiments, the second transparent conductive layer 120 is a patterned electrode comprising a plurality of slits 122, and the display panel 100 is made to be a boundary through the arrangement of the slits 122 of the second transparent conductive layer 120 and the first transparent conductive layer 110FFS (Fringe Field Switching) wide-viewing-angle liquid crystal display panel. In this embodiment, the slit 122 does not exceed the sub-pixel area; in other embodiments, the slit 122 may extend beyond the sub-pixel region, for example, may span the data line 150 or may span the scan line 140.
Fig. 3 is a partial plan view of the display panel 100 according to another embodiment of the present invention, in which two channel regions, namely a first channel region 1308 and a second channel region 1309, are generated at the overlapping portion of the middle connection region 1303 of the active layer 130 and the scan line 140, and a first non-channel region 1304, a second non-channel region 1305 and a third non-channel region 1306 are generated at the non-overlapping portion of the middle connection region 1303 of the active layer 130 and the scan line 140. According to the embodiment of the invention, the widths of the first non-channel region 1304, the second non-channel region 1305 and the third non-channel region 1306 are greater than the widths of the first channel region 1308 and the second channel region 1309, so that the pattern of the active layer 130 has a width variation that the non-channel region is wider and the channel region is narrower, thereby achieving the effect of reducing the resistance of the active layer.
As shown in fig. 3, in some embodiments, the first connection hole region 1301 of the active layer 130 is farther from the scan line 140 than the second connection hole region 1302, such that the first non-channel region 1304 between the first connection hole region 1301 and the scan line 140 has a longer length. Because the first non-channel region 1304 is longer than the third non-channel region 1306, the first connection hole region 1301 and the second connection hole region 1302 can be staggered, and because the connection hole regions need larger areas (the alignment error in the manufacturing process is reserved), the two connection hole regions can be closer to each other in the direction of the parallel scan line 140 due to the staggering, and the width of a single sub-pixel in the direction of the parallel scan line 140 can be reduced. However, since the length of the first non-channel region 1304 is long, if the width of the first non-channel region 1304 is kept constant, the number of sub-pixels that can be set may be reduced, and the resolution design requirement of the display panel is further limited, therefore, the resistance value can be maintained and the influence on the aperture ratio can be reduced by making the first non-channel region 1304 have different widths (but wider than the channel region).
In some embodiments, as shown in fig. 3, the data line 150 may be a data line having a straight curve, and the middle connection region 1303 of the active layer 130 partially overlaps the data line 150, such that the non-overlapping portion of the middle connection region 1303 and the data line 150 has a first region 1311 and a second region 1312 respectively located at two sides of the data line 150, wherein the second region 1312 is located between the data line 150 and the second connection hole region 1302, and the first region 1311 is located at the other side of the data line 150 different from the second region 1312. The first region 1311 has a width W4, the second region 1312 has a width W5, and the directions of the width W4 and the width W5 are substantially parallel to the substantial extending direction of the scan line 140. In some embodiments, the width W4 of the first region 1311 is approximately equal to the width W5 of the second region 1312. In other embodiments, the width W4 of the first region 1311 may be greater than the width W5 of the second region 1312. In some other embodiments, the width W4 of the first region 1311 may be less than the width W5 of the second region 1312.
In some embodiments of the present invention, the intermediate connection region 1303 of the active layer 130 partially overlaps the data line 150, which may reduce parasitic capacitance generated between the active layer 130 and the data line 150, compared to an example in which the active layer and the data line completely overlap. In addition, compared to the case where the active layer and the data line are completely staggered, in some embodiments of the invention, the middle connection region 1303 of the active layer 130 partially overlaps the data line 150, which may increase the aperture ratio of the display panel.
Furthermore, in some embodiments, as shown in fig. 3, the first non-channel region 1304 of the middle connection region 1303 of the active layer 130 has a width W6 adjacent to the first via region 1301, and the second non-channel region 1305 of the middle connection region 1303 has a width W7 adjacent to the second via region 1302, and the width W6 is greater than the width W7. Additionally, in some embodiments, the first jack region 1301 has a width W8, while the second jack region 1302 has a width W9, and the width W9 is greater than the width W8. In some embodiments, the widths W4-W9 are oriented substantially parallel to the direction of substantial extension of the scan line 140.
FIG. 4 is a partial cross-sectional view of the display panel 100 taken along section line 4-4' of FIG. 3 according to some embodiments of the invention. As shown in fig. 4, in some embodiments, the first transparent conductive layer 110 electrically connected to the second connection hole region 1302 of the active layer 130 is a patterned electrode including a plurality of slits 113, the second transparent conductive layer 120 is located below the first transparent conductive layer 110, and the second transparent conductive layer 120 has an opening 125 adjacent to the second connection hole region 1302, the opening 125 is disposed such that the second transparent conductive layer 120 does not cover the via hole 119 and thus avoids the location of the via hole 119. In this embodiment, the display panel 100 becomes a boundary electric field switching (FFS) liquid crystal display panel through the arrangement of the slits 113 of the first transparent conductive layer 110 and the second transparent conductive layer 120.
Fig. 5 is a partial plan view of the display panel 100 according to another embodiment of the present invention, as shown in fig. 5, in some embodiments, the first connection hole region 1301 of the active layer 130 is far away from the scan line 140, so that the first non-channel region 1304 of the middle connection region 1303 between the first connection hole region 1301 and the second connection hole region 1302 has a longer length. In addition, in the embodiment of fig. 5, the data line 150 may be in the form of a wire having a bending curve, the data line 150 generally has a substantially extending direction, such that the middle connection region 1303 of the active layer 130 is partially overlapped with the data line 150, and the middle connection region 1303 may include two regions respectively located at two sides of the data line 150, in this embodiment, the region of the middle connection region 1303 located at the left side of the data line 150 has a larger width than the region of the middle connection region 1303 located at the right side of the data line 150. In addition, as shown in fig. 5, the via 117 located in the second hole region 1302 of the active layer 130 has a bottom edge (or lower edge) 117-1 and a top edge (or upper edge) 117-2, wherein the area surrounded by the bottom edge 117-1 is smaller than the area surrounded by the top edge 117-2, so that the via 117 has two annular boundaries in the plan view shown in fig. 5. The vias 115 and 119 also have top and bottom edges, only the top edge of the via is shown in fig. 1, 3 and 5.
In the embodiment of fig. 5, the widths of the first non-channel region 1304, the second non-channel region 1305 and the third non-channel region 1306 generated by the non-overlapping of the middle connection region 1303 of the active layer 130 and the scan line 140 are greater than the widths of the first channel region 1308 and the second channel region 1309 generated by the overlapping of the middle connection region 1303 and the scan line 140, so that the pattern of the active layer 130 has a wide and narrow variation of the non-channel region and the channel region, thereby achieving the effect of reducing the resistance value and the parasitic capacitance of the active layer.
In addition, the first transparent conductive layer and the second transparent conductive layer of the display panel 100 are not shown in fig. 5, and in some embodiments, the display panel 100 of fig. 5 may employ a patterned electrode of the second transparent conductive layer 120 including the slits 122 as shown in fig. 1 to form a Fringe Field Switching (FFS) liquid crystal display panel. In other embodiments, the display panel 100 of fig. 5 may also use the patterned electrode of the first transparent conductive layer 110 including the slits 113 as shown in fig. 3 to form a Fringe Field Switching (FFS) liquid crystal display panel.
Fig. 6 is a partial schematic plan view of a display panel 100 according to other embodiments of the present invention, as shown in fig. 6, in some embodiments, the first contact hole region 1301 of the active layer 130 is adjacent to the scan line 140, such that the first non-channel region 1304 and the second non-channel region 1305 between the first connection hole region 1301 and the second connection hole region 1302 have shorter lengths, however, the first non-channel region 1304 is longer than the second non-channel region 1305, so that the first and second contact hole regions 1301, 1302 can be staggered to reduce the resolution effect, since the contact hole regions occupy a larger area, if two contact hole regions are placed side by side, a larger sub-pixel width (parallel to the substantial extension direction of the scan lines) may be required to accommodate the first connection hole region 1301 and the second connection hole region 1302, this limits the number of sub-pixels, which in turn affects the design requirements of the display panel for higher resolution. In this embodiment, the intermediate connection region 1303 of the active layer 130 has a width W6 adjacent to the first via region 1301, and the intermediate connection region 1303 has a width W7 adjacent to the second via region 1302, and the width W6 is greater than the width W7. In addition, the scan line 140 and the data line 150 may be a linear wiring pattern. In other embodiments, the scan lines 140 and the data lines 150 may not be straight lines, but the scan lines 140 and the data lines 150 have a substantially extending direction, respectively.
In addition, as shown in fig. 6, the via 117 located in the second connection hole region 1302 of the active layer 130 has a bottom edge (or via bottom edge) 117-1 and a top edge (or via top edge) 117-2, wherein the area surrounded by the bottom edge 117-1 is smaller than the area surrounded by the top edge 117-2, and the via 119 located in the second connection hole region 1302 of the active layer 130 also has a bottom edge (or via bottom edge) 119-1 and a top edge (or via top edge) 119-2, wherein the area surrounded by the bottom edge 119-1 is smaller than the area surrounded by the top edge 119-2, so that the via 117 and the via 119 have two annular boundaries in the plan view shown in fig. 6. In other embodiments, the via hole may be non-circular, such as oval or irregular.
In the embodiment of fig. 6, the widths of the first non-channel region 1304, the second non-channel region 1305 and the third non-channel region 1306 generated by the non-overlapping of the middle connection region 1303 of the active layer 130 and the scan line 140 are greater than the widths of the first channel region 1308 and the second channel region 1309 generated by the overlapping of the middle connection region 1303 and the scan line 140, so that the pattern of the active layer 130 has a wide and narrow variation of the non-channel region and the channel region, thereby achieving the effect of reducing the resistance value and the parasitic capacitance of the active layer.
In addition, the first transparent conductive layer and the second transparent conductive layer of the display panel 100 are not depicted in fig. 6, and in some embodiments, the display panel 100 of fig. 6 may employ a patterned electrode of the second transparent conductive layer 120 including the slits 122 as shown in fig. 1; in other embodiments, the slits 122 of the second transparent conductive layer 120 of the display panel 100 of fig. 6 may cross the data lines or the scan lines without interruption, depending on design requirements. In other embodiments, the display panel 100 of fig. 6 may also employ patterned electrodes of the first transparent conductive layer 110 including the slits 113 as shown in fig. 3 to form a Fringe Field Switching (FFS) liquid crystal display panel.
In summary, according to some embodiments of the present invention, the pattern of the active layer of the thin film transistor of the display panel is improved, and particularly, for the active layer made of low temperature polysilicon, the width of the non-channel region generated by the non-overlapping of the middle connection region between the first connection hole region and the second connection hole region of the active layer and the scan line is greater than the width of the channel region generated by the overlapping of the middle connection region and the scan line, so that the pattern of the active layer has a wide and narrow variation of the non-channel region and the narrow channel region, thereby achieving the effect of reducing the resistance value and the parasitic capacitance of the active layer and improving the electrical performance of the thin film transistor.
Although the present invention has been described in connection with the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art will appreciate that various modifications and variations can be made without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention should be subject to the definition of the appended claims.
Claims (10)
1. A display panel, comprising:
a first substrate;
a scan line disposed on the first substrate, the scan line having an extending direction; and
an active layer disposed on the first substrate;
wherein the overlapping portion of the active layer and the scan line comprises a first overlapping region and a second overlapping region, and a minimum width of the non-overlapping portion between the first overlapping region and the second overlapping region and along the extending direction is larger than a minimum width of the first overlapping region along the extending direction.
2. The display panel of claim 1, wherein a minimum width along a direction perpendicular to the extending direction where the first overlapping region and the second overlapping region do not overlap with the scan line is a distance between a first side edge and a second side edge.
3. The display panel of claim 1, wherein a minimum width of a portion between the first overlapping area and the second overlapping area that does not overlap with the scan line along a direction perpendicular to the extending direction is greater than a minimum width of the second overlapping area along the extending direction.
4. The display panel of claim 1, further comprising a data line, wherein the data line is not overlapped between the first overlapping area and the second overlapping area where the scan line is not overlapped.
5. The display panel of claim 4, wherein the active layer is between the data line and the first substrate.
6. The display panel of claim 4, wherein the active layer further comprises a first via region electrically connected to the data line.
7. The display panel of claim 1, wherein the first overlapping area and the second overlapping area are located under the scan line at a position not overlapping with the scan line.
8. The display panel of claim 1, further comprising a conductive layer disposed on the first substrate, the conductive layer overlapping a portion between the first overlapping area and the second overlapping area that does not overlap the scan line.
9. The display panel of claim 8, wherein the conductive layer is an electrode.
10. The display panel of claim 8, wherein the active layer further comprises a second via region electrically connected to the conductive layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010428830.XA CN111665669A (en) | 2015-01-08 | 2015-01-08 | Display panel |
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| US10825839B2 (en) * | 2016-12-02 | 2020-11-03 | Innolux Corporation | Touch display device |
| CN108761944B (en) * | 2018-08-22 | 2023-06-02 | 武汉华星光电技术有限公司 | Array panel |
| CN110764326A (en) * | 2019-10-14 | 2020-02-07 | 深圳市华星光电半导体显示技术有限公司 | Liquid crystal display panel and preparation method thereof |
| CN114068590B (en) * | 2022-01-14 | 2022-06-21 | 京东方科技集团股份有限公司 | Array substrate and display panel |
| CN117795678A (en) * | 2022-07-28 | 2024-03-29 | 京东方科技集团股份有限公司 | Display substrate, display panel and display device |
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| CN105824160B (en) | 2020-06-16 |
| CN105824160A (en) | 2016-08-03 |
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