CN204422934U - Display panel - Google Patents
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- CN204422934U CN204422934U CN201520011129.2U CN201520011129U CN204422934U CN 204422934 U CN204422934 U CN 204422934U CN 201520011129 U CN201520011129 U CN 201520011129U CN 204422934 U CN204422934 U CN 204422934U
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Abstract
The utility model discloses a kind of display panel, it comprises sweep trace and data line is crisscross arranged on substrate, active layer to be arranged on substrate and between data line and substrate, and transparency conducting layer to be arranged on substrate and to be positioned at above active layer, wherein active layer comprises first and connects porose area and be electrically connected with data line, second connects porose area is electrically connected with transparency conducting layer, and middle attachment zone connects porose area and second first and connects between porose area, middle attachment zone and sweep trace overlapping are channel region, middle attachment zone and sweep trace not overlapping are non-channel region, the width of non-channel region is greater than the width of channel region.
Description
Technical field
The utility model relates to display panel technology, particularly relates to the active layer design using low temperature polycrystalline silicon to make the display panel of the active layer of thin film transistor (TFT).
Background technology
In recent years, liquid crystal display, because have the advantages such as slimming, lightweight, low-power consume and Low emissivity, has become topmost flat-panel screens, and has been widely used in various electronic installation.In the liquid crystal display of active matrix, thin film transistor (TFT) (thin-film transistor; TFT) as the driving element controlling pixel switching, according to the active layer material of thin film transistor (TFT), thin film transistor (TFT) can be divided into two classes: wherein a class is amorphous silicon film transistor, another kind of is polycrystalline SiTFT.
In previous technology, manufacture polycrystalline SiTFT to need to use the high temperature higher than 1000 degree, make amorphous silicon layer melting and recrystallize into as polysilicon layer, but, along with the development of laser technology, the manufacture craft temperature lower than 600 degree can be used at present to form polysilicon layer, and this manufacturing technology is called low temperature polycrystalline silicon (low-temperature polysilicon; LTPS) thin-film transistor technologies.
Low-temperature polysilicon film transistor has carrier mobility faster compared to amorphous silicon film transistor, therefore uses the liquid crystal display of low-temperature polysilicon film transistor manufacture to have the advantages such as high-effect, short response time.
But for the liquid crystal display using low temperature polycrystalline silicon to make, the low temperature polycrystalline silicon forming the active layer of thin film transistor (TFT) also has many places that can improve, with the display quality making liquid crystal display reach better.
Utility model content
The purpose of this utility model is to provide a kind of display panel, its low-temperature polysilicon silicon active layer for thin film transistor (TFT) is improved, the pattern width of low-temperature polysilicon silicon active layer is utilized to design, the overall resistance of low-temperature polysilicon silicon active layer is allowed to reduce, the electric characteristics of thin film transistor (TFT) can be improved thus, and then improve the image display quality of display panel.
For reaching above-mentioned purpose, the utility model provides a kind of display panel, comprising: first substrate; Sweep trace and data line are crisscross arranged on first substrate; Active layer is arranged on first substrate, and active layer is between data line and first substrate; And first transparency conducting layer be arranged on first substrate, and the first transparency conducting layer is positioned at above active layer, wherein active layer comprises: first connects porose area is electrically connected with data line, second connects porose area is electrically connected with the first transparency conducting layer, and middle attachment zone connects porose area and second first and connects between porose area, middle attachment zone and sweep trace overlapping comprise first passage district, middle attachment zone and this sweep trace not overlapping are non-channel region, and the width of non-channel region is greater than the width in first passage district.
This middle attachment zone and this data line partly overlap, and this middle attachment zone comprises the both sides that one first district and one second district lay respectively at this data line, and wherein this secondth district is positioned at this data line and this second connects between porose area.
The width in this firstth district is equal with the width in this secondth district.
The width in this firstth district is greater than the width in this secondth district.
The width in this firstth district is less than the width in this secondth district.
This middle attachment zone this first width connecing porose area contiguous is greater than this middle attachment zone this second width connecing porose area contiguous.
This second width connecing porose area is greater than this first width connecing porose area, and the direction of those width is parallel to this sweep trace.
This middle attachment zone and this sweep trace overlapping also comprise a second channel district, and the width of this non-channel region is greater than the width in this second channel district.
The width in this second channel district is different from the width in this first passage district.
The width in this second channel district is identical with the width in this first passage district.
A part for this middle attachment zone is between this first passage district and this second channel district, and the width of this part of this middle attachment zone is greater than the width in this first passage district, and the width of this part of this middle attachment zone is greater than the width in this second channel district.
This part of this middle attachment zone has two teats, and these two teats protrude from this first passage district and this second channel district respectively on the direction being parallel to this sweep trace.
This display panel also comprises: second substrate, arranges with this first substrate subtend; And display medium, be arranged between this first substrate and this second substrate.
This display panel also comprises one second transparency conducting layer, is arranged on this first substrate, and this second transparency conducting layer is positioned at above this first transparency conducting layer.
This second transparency conducting layer is a patterned electrodes comprising multiple slit.
This display panel also comprises one second transparency conducting layer, is arranged on this first substrate, and this second transparency conducting layer is positioned at below this first transparency conducting layer.
This first transparency conducting layer is a patterned electrodes comprising multiple slit, and this second transparency conducting layer has an opening is adjacent to this and second connects porose area.
The utility model has the advantage of, it is improved the pattern of the active layer of the thin film transistor (TFT) of display panel, particularly for the active layer be made up of low temperature polycrystalline silicon, allow first of active layer to connect porose area and second and connect the width that middle attachment zone between porose area and the width of not overlapping the produced non-channel region of sweep trace be greater than produced channel region overlapping with sweep trace, middle attachment zone, the pattern of active layer is made to have the wider and wide thin change that channel region is narrower in non-channel region, reach thus and reduce the resistance of active layer and effect of stray capacitance, to promote the electrical property efficiency of thin film transistor (TFT).
Accompanying drawing explanation
Fig. 1 is the part plan schematic diagram of the display panel of embodiments more of the present utility model;
Fig. 2 is the partial cutaway schematic of embodiments more of the present utility model along the display panel of the profile line 2-2 ' of Fig. 1;
Fig. 3 is the part plan schematic diagram of the display panel of other embodiments of the present utility model;
Fig. 4 is the partial cutaway schematic of embodiments more of the present utility model along the display panel of the profile line 4-4 ' of Fig. 3;
Fig. 5 is the part plan schematic diagram of the display panel of other embodiments more of the present utility model;
Fig. 6 is the part plan schematic diagram of the display panel of other embodiments more of the present utility model.
Symbol description
100 ~ display panel;
101 ~ first substrate;
102 ~ second substrate;
1301 ~ the first connect porose area;
1302 ~ the second connect porose area;
1303 ~ middle attachment zone;
The side of 1303-L1,1303-L2 ~ middle attachment zone;
1304 ~ the first non-channel regions;
1305 ~ the second non-channel regions;
1306 ~ three non-channel region;
1307 ~ teat;
1308 ~ first passage district;
1309 ~ second channel district;
1311st ~ the first district;
1312nd ~ the second district;
110 ~ the first transparency conducting layers;
The slit of 113 ~ the first transparency conducting layers;
115,117,119 ~ via;
117-1,119-1 ~ bottom margin;
117-2,119-2 ~ top;
120 ~ the second transparency conducting layers;
The slit of 122 ~ the second transparency conducting layers;
The opening of 125 ~ the second transparency conducting layers;
126 ~ the first insulation courses;
128 ~ the second insulation courses;
132 ~ three insulation course;
134 ~ four insulation course;
130 ~ active layer;
136 ~ display dielectric layer;
140 ~ sweep trace;
150 ~ data line;
152 ~ drain electrode;
The width in W1 ~ first passage district;
The width in W2 ~ second channel district;
The width of the non-channel region of W3 ~ three;
The width in W4 ~ the first district;
The width in W5 ~ the second district;
The width of the non-channel region of W6 ~ the first;
The width of the non-channel region of W7 ~ the second;
W8 ~ the first connects the width of porose area;
W9 ~ the second connects the width of porose area.
Embodiment
Fig. 1 shows according to embodiments more of the present utility model, the part plan schematic diagram of display panel 100, display panel 100 comprises multi-strip scanning line 140 and is arranged at intermeshing on first substrate (Fig. 1 does not draw) to define repeatedly pixel region with a plurality of data lines 150.In the present embodiment, secondary pixel region is the region that adjacent data line and adjacent scanning lines are surrounded.Be adjacent to sweep trace 140 and the staggered place of data line 150 is provided with thin film transistor (TFT), thin film transistor (TFT) is in order to control time pixel region and the on-off element be electrically connected with data line.According to embodiment of the present utility model, thin film transistor (TFT) comprises the active layer 130 made with low temperature polycrystalline silicon, active layer 130 comprises first and connects porose area 1301, second and connect porose area 1302, and connects porose area 1301 and second first and connect middle attachment zone 1303 between porose area 1302.Middle attachment zone 1303 and sweep trace 140 overlapping of active layer 130 produce two channel regions, be respectively first passage district 1308 and second channel district 1309, the middle attachment zone 1303 of active layer 130 and sweep trace 140 not overlapping be then non-channel region, as in Fig. 1 indicate be positioned at close data line on the upside of sweep trace 140 the first non-channel region 1304, be positioned on the upside of sweep trace compared with away from the second non-channel region 1305 of data line and the 3rd non-channel region 1306 that is positioned on the downside of sweep trace 140.
In addition, as shown in Figure 1, in certain embodiments, display panel 100 also comprises the second transparency conducting layer 120 as top transparency conducting layer, in this embodiment, second transparency conducting layer 120 is as common electrode, and the second transparency conducting layer 120 has multiple slit 122 and is formed at wherein, and the second transparency conducting layer 120 covers sweep trace 140, data line 150 and active layer 130.In certain embodiments, the second transparency conducting layer 120 covers and is positioned at first of active layer 130 and connects the via (via) 115 of porose area 1301 and be positioned at the via (via) 117 and 119 that second of active layer 130 connects porose area 1302.In further embodiments, second transparency conducting layer 120 can have opening (opening) (not drawing in FIG), this opening is adjacent to the forming position of via 117 and 119, that is second the opening of transparency conducting layer 120 be adjacent to second and connect porose area 1302, and make the second transparency conducting layer 120 to avoid and via 117 and 119 can not be covered.In the present embodiment, data line 150 is non-rectilinear wiring configuration, but this data line 150 has a substantial bearing of trend haply; In other embodiments, data line 150 can be straight line wiring configuration.In the present embodiment, sweep trace 140 is straight line wiring configuration; In other embodiments, sweep trace 140 can be non-rectilinear wiring configuration, but this sweep trace 140 has a substantial bearing of trend haply.
As shown in Figure 1, first passage district 1308 has the first width W 1, and the direction that second channel district 1309 has the second width W 2, first width W 1 and the second width W 2 is the bearing of trend being in fact parallel to sweep trace 140.The part of middle attachment zone 1303 between first passage district 1308 and second channel district 1309, that is the 3rd to have the 3rd width W the 3, three width W 3 be vertical range between the first side 1303-L1 of middle attachment zone 1303 and second side 1303-L2 in non-channel region 1306.First side 1303-L1 refers to the side inside the middle attachment zone 1303 of active layer 130, and second side 1303-L2 refers to the side outside active layer middle attachment zone 1303.
According to embodiment of the present utility model, the 3rd width W 3 of the 3rd non-channel region 1306 is greater than first width W 1 in first passage district 1308, and the 3rd width W 3 of the 3rd non-channel region 1306 is also greater than second width W 2 in second channel district 1309 simultaneously.In addition, according to embodiment of the present utility model, the width of middle attachment zone 1303 and the nonoverlapping first non-channel region 1304 of sweep trace 140 and the second non-channel region 1305 is greater than first width W 1 in first passage district 1308, and the width of the first non-channel region 1304 and the second non-channel region 1305 is also greater than second width W 2 in second channel district 1309.In embodiment of the present utility model, the width of each several part of middle attachment zone 1303 is defined as the vertical range between two side 1303-L1 and 1303-L2 of middle attachment zone 1303, and therefore the direction of the width of the some parts of middle attachment zone 1303 can be not parallel to the bearing of trend of sweep trace 140.
In order to meet the functional requirement of thin film transistor (TFT) as pixel switch element, the length and width ratio in the first passage district 1308 that the active layer 130 of thin film transistor (TFT) produces with the overlapping place of sweep trace 140 and the length and width ratio in second channel district 1309 all need to maintain in certain ratio range, and therefore first width W 1 in first passage district 1308 and second width W 2 in second channel district 1309 need meet the resolution of display panel to the design requirement of the passage aspect ratio of thin film transistor (TFT).In known display panel manufacturing technology, the active layer of thin film transistor (TFT) is except the part connecing porose area, remainder has consistent width, the width that the width of usual active layer adopts the length and width ratio meeting channel region to require makes, but, the resistance of the active layer adopting this mode to make cannot reduce, and causes the usefulness of thin film transistor (TFT) to promote.
According to embodiment of the present utility model, first non-channel region 1305, non-channel region 1304, second of active layer 130 and the width of the 3rd non-channel region 1306 are greater than the width in first passage district 1308, also be greater than the width in second channel district 1309, make the pattern of active layer 130 have the wider and wide thin change that channel region is narrower in non-channel region.Via the first non-channel region 1305, non-channel region 1304, second and the 3rd non-channel region 1306 that width is larger, the overall resistance of the active layer 130 be made up of low temperature polycrystalline silicon can be reduced, simultaneously, the width in first passage district 1308 and second channel district 1309 also meets the Aspect Ratio requirement of the channel region of thin film transistor (TFT), therefore, embodiment of the present utility model can promote the electrical property efficiency of thin film transistor (TFT).
In certain embodiments, as shown in Figure 1, the three non-channel region 1306 of middle attachment zone 1303 between first passage district 1308 and second channel district 1309 has two teats 1307, and these two teats 1307 protrude from respectively outside first passage district 1308 and second channel district 1309 on the direction being parallel to sweep trace 140.In addition, in certain embodiments, the width W 1 in first passage district 1308 and the width W 2 in second channel district 1309 can be rough identical.In some other embodiments, the width W 1 in first passage district 1308 can be different from the width W 2 in second channel district 1309.In addition, as shown in Figure 1, in certain embodiments, data line 150 can be the data line with bending curve, and first of active layer 130 connects porose area 1301 and second connects porose area 1302 and is more or less the same from the distance of sweep trace 140, forms the active layer 130 that the length of middle attachment zone 1303 is shorter.
Fig. 2 shows according to embodiments more of the present utility model, along the profile line 2-2 ' of Fig. 1, and the partial cutaway schematic of display panel 100.As shown in Figure 2, display panel 100 comprises first substrate 101, sweep trace 140 and data line 150 are arranged on first substrate 101, active layer 130 is arranged on first substrate 101, and active layer 130 is positioned at below data line 150 and sweep trace 140, active layer 130 is between data line 150 and first substrate 101 simultaneously.In certain embodiments, the thin film transistor (TFT) of display panel 100 can be top grid (top-gate) structure, as shown in Figure 2, the channel region that sweep trace (grid) 140 place overlapping with active layer 130 produces is positioned at above active layer 130.In further embodiments, the thin film transistor (TFT) of display panel 100 can be bottom grid (bottom-gate) structure, and the channel region that its sweep trace (grid) place overlapping with active layer produces is positioned at below active layer.
Consult Fig. 1 and Fig. 2, connect above porose area 1301 at first of active layer 130 and be formed with via (viahole) 115, first of active layer 130 connects porose area 1301 and is electrically connected with data line 150 via via 115.In addition, as shown in Figure 2, display panel 100 also comprises the first transparency conducting layer 110, and connect above porose area 1302 at second of active layer 130 and be formed with via 117 and 119, second of active layer 130 connects porose area 1302 and is electrically connected to the first transparency conducting layer 110 via via 117 and 119.Via 115 first connects the first insulation course 126 above porose area 1301 and the hole in the second insulation course 128 for what be formed in active layer 130, the metal material forming data line 150 is filled in via 115, make data line 150 can connect porose area 1301 via via 115 with first of active layer 130 to be electrically connected, and a part for data line 150 forms the source electrode (source electrode) of thin film transistor (TFT).In addition, via 117 second connects the first insulation course 126 above porose area 1302 and the hole in the second insulation course 128 for what be formed in active layer 130, and the metal material forming the drain electrode (drain electrode) 152 of thin film transistor (TFT) can be connected with active layer 130 via via 117.In addition, via 119 is for being formed in the hole in the 3rd insulation course 132 above the second insulation course 128, and the material forming the first transparency conducting layer 110 is filled in via 119, make the first transparency conducting layer 110 can be electrically connected to the drain electrode 152 of thin film transistor (TFT) via via 119, be then electrically connected to second of active layer 130 via via 117 and connect porose area 1302.First insulation course 126 and the second insulation course 128 can be identical or different inorganic material, such as, be SiOx or SiNx.
As shown in Figure 2, between the bigrid that active layer 130 and sweep trace 140 are formed, there is the first insulation course 126, the second insulation course 128 and the 3rd insulation course 132 is formed above sweep trace 140, via 115 and 117 is formed in the first insulation course 126 and the second insulation course 128, via 119 is then formed in the 3rd insulation course 132, in certain embodiments, a part for first transparency conducting layer 110 can be formed in compliance in the via 119 of the 3rd insulation course 132, and the metal material forming the source electrode of thin film transistor (TFT) can be formed in compliance in via 115, and the metal material forming the drain electrode 152 of thin film transistor (TFT) also can be formed in compliance in via 117.3rd insulation course 132 can be organic material, can be used for planarization, such as, can be organic material (such as poly-Fluoroalkyloxy polyfluoro alkoxy, PFA) or chromatic filter layer (Color Filter) material.
Display panel 100 also comprises second substrate 102, and display dielectric layer 136 is arranged between second substrate 102 and first substrate 101.In certain embodiments, display dielectric layer 136 can be liquid crystal layer, and second substrate 102 can be colored filter (color filter; CF) substrate, first substrate 101 is then thin film transistor (TFT) array (Array) substrate.In further embodiments, chromatic filter layer can be arranged on first substrate 101, and such as the 3rd insulation course 132 can adopt colorized optical filtering layer material to replace it.
In certain embodiments, as depicted in figs. 1 and 2, display panel 100 also comprises the second transparency conducting layer 120 and is positioned at above the first transparency conducting layer 110, and between the first transparency conducting layer 110 and the second transparency conducting layer 120, there is the 4th insulation course 134, first transparency conducting layer 110 is electrically insulated by the 4th insulation course 134 and the second transparency conducting layer 120,4th insulation course 134 can be inorganic material, such as silicon oxide sio x or silicon nitride SiNx.In certain embodiments, second transparency conducting layer 120 is for comprising the patterned electrodes of multiple slit 122, via the slit 122 of the second transparency conducting layer 120 and the setting of the first transparency conducting layer 110, make display panel 100 become boundary electric field and switch (Fringe FieldSwitching; FFS) liquid crystal display panel with wide visual angle.In this embodiment, slit 122 does not exceed time pixel region scope; In other embodiments, slit 122 can exceed time pixel region scope, such as, can cross over data line 150 and maybe can cross over sweep trace 140.
Fig. 3 is according to other embodiments of the present utility model, the part plan schematic diagram of display panel 100, middle attachment zone 1303 and sweep trace 140 overlapping of active layer 130 produce two channel regions, be respectively first passage district 1308 and second channel district 1309, the middle attachment zone 1303 of active layer 130 and sweep trace 140 not overlapping are then the first non-channel region 1305, non-channel region 1304, second and the 3rd non-channel region 1306.According to embodiment of the present utility model, the width of the first non-channel region 1305, non-channel region 1304, second and the 3rd non-channel region 1306 is greater than the width in first passage district 1308 and second channel district 1309, make the pattern of active layer 130 have the wider and wide thin change that channel region is narrower in non-channel region, reach the effect of the resistance reducing active layer thus.
As shown in Figure 3, in certain embodiments, first of active layer 130 connects porose area 1301 and connects porose area 1302 compared to second and must, away from sweep trace 140, make the first the first non-channel region 1304 connect between porose area 1301 and sweep trace 140 have longer length.Because of the first non-channel region 1304 compared to the 3rd non-channel region 1306 length come longer, therefore can stagger and first connect porose area 1301 and second and connect porose area 1302, because connect the area comparatively large (retaining the bit errors in manufacture craft) that porose area needs, therefore stagger and can allow two to connect porose area comparatively close on parallel scan lines 140 direction, can reduce by single the width of pixel on parallel scan lines 140 direction.But because the first non-channel region 1304 length is longer, if maintenance fixed width, the secondary pixel quantity that can arrange may be reduced, and then limit the resolution design requirement of display panel, therefore, make the first non-channel region 1304 have different in width (but coming wide than channel region), both can maintain resistance, and also can reduce the impact on aperture opening ratio.
In certain embodiments, as shown in Figure 3, data line 150 can be the data line with straight curve, and middle attachment zone 1303 and the data line 150 of active layer 130 partly overlap, middle attachment zone 1303 and the nonoverlapping part of data line 150 are had both sides that the first district 1311 and the second district 1312 lay respectively at data line 150, wherein the second district 1312 connects between porose area 1302 at data line 150 and second, and the first district 1311 is then positioned at the different opposite side of data line 150 and the second district 1312.First district 1311 has width W 4, and the second district 1312 has width W 5, and the direction of width W 4 and width W 5 is roughly parallel to the essence bearing of trend of sweep trace 140.In certain embodiments, the width W 4 in the first district 1311 is rough equal with the width W 5 in the second district 1312.In further embodiments, the width W 4 in the first district 1311 can be greater than the width W 5 in the second district 1312.In some other embodiments, the width W 4 in the first district 1311 can be less than the width W 5 in the second district 1312.
Be compared to the example that active layer is completely overlapping with data line, in embodiments more of the present utility model, middle attachment zone 1303 and the data line 150 of active layer 130 partly overlap, and can reduce the stray capacitance produced between active layer 130 and data line 150.In addition, compared to the example that active layer and data line stagger completely, in embodiments more of the present utility model, middle attachment zone 1303 and the data line 150 of active layer 130 partly overlap, and can increase the aperture opening ratio of display panel.
In addition, in certain embodiments, as shown in Figure 3, first non-channel region 1304 contiguous first of the middle attachment zone 1303 of active layer 130 meets porose area 1301 place and has width W 6, and second of middle attachment zone 1303 the non-channel region 1305 contiguous second meets porose area 1302 place and has width W 7, and width W 6 is greater than width W 7.In addition, in certain embodiments, first connects porose area 1301 has width W 8, and second connects porose area 1302 and have width W 9, and width W 9 is greater than width W 8.In certain embodiments, the direction of above-mentioned width W 4 ~ W9 is roughly parallel to the direction extended in fact of sweep trace 140.
Fig. 4 is according to embodiments more of the present utility model, along the profile line 4-4 ' of Fig. 3, and the partial cutaway schematic of display panel 100.As shown in Figure 4, in certain embodiments, be electrically connected to second of active layer 130 and connect the first transparency conducting layer 110 of porose area 1302 for comprising the patterned electrodes of multiple slit 113, second transparency conducting layer 120 is positioned at below the first transparency conducting layer 110, and the second transparency conducting layer 120 has opening 125 and is adjacent to second and meets porose area 1302 place, and the setting of opening 125 can allow the second transparency conducting layer 120 can not cover via 119 and then avoid via 119 position.In this embodiment, via the slit 113 of the first transparency conducting layer 110 and the setting of the second transparency conducting layer 120, display panel 100 is made to become the display panels of boundary electric field switching (FFS).
Fig. 5 is according to other embodiments of the present utility model, the part plan schematic diagram of display panel 100, as shown in Figure 5, in certain embodiments, first of active layer 130 connects porose area 1301 away from sweep trace 140, makes the first the first non-channel region 1304 connecing the middle attachment zone 1303 that porose area 1301 and second connects between porose area 1302 have longer length.In addition, in the 5 embodiment of figure 5, data line 150 can be the wiring configuration with bending curve, data line 150 has a substantial bearing of trend haply, the middle attachment zone 1303 of active layer 130 is partly overlapped with data line 150, middle attachment zone 1303 can comprise the both sides that two regions lay respectively at data line 150, in this embodiment, the region that middle attachment zone 1303 is positioned on the left of data line 150 has larger width compared to the region be positioned on the right side of data line 150, middle attachment zone 1303.In addition, as shown in Figure 5, be positioned at the via 117 that second of active layer 130 connects porose area 1302 and there is bottom margin (or claiming through hole lower edge) 117-1 and top (or claiming through hole upper limb) 117-2, wherein bottom margin 117-1 around area be less than top 117-2 around area, therefore, in the planimetric map shown in Fig. 5, via 117 has two ring-type borders.Via 115, via 119 also have top and bottom margin, only illustrate the top of via in Fig. 1, Fig. 3, Fig. 5.
In the 5 embodiment of figure 5, middle attachment zone 1303 and not overlapping the first the produced non-channel region 1305, non-channel region 1304, second of sweep trace 140 and the width of the 3rd non-channel region 1306 of active layer 130 are greater than the width in produced first passage district 1308 overlapping with sweep trace 140, middle attachment zone 1303 and second channel district 1309, make the pattern of active layer 130 have the wider and wide thin change that channel region is narrower in non-channel region, reach thus and reduce the resistance of active layer and effect of stray capacitance.
In addition, do not draw the first transparency conducting layer and second transparency conducting layer of display panel 100 in Figure 5, in certain embodiments, the display panel 100 of Fig. 5 can adopt the patterned electrodes comprising the second transparency conducting layer 120 of slit 122 as shown in Figure 1, forms the display panels that boundary electric field switches (FFS).In further embodiments, the display panel 100 of Fig. 5 also can adopt the patterned electrodes comprising the first transparency conducting layer 110 of slit 113 as shown in Figure 3, forms the display panels that boundary electric field switches (FFS).
Fig. 6 is according to other embodiments of the present utility model, the part plan schematic diagram of display panel 100, as shown in Figure 6, in certain embodiments, first of active layer 130 connects porose area 1301 near sweep trace 140, make first to connect porose area 1301 and second and connect the first non-channel region 1304 between porose area 1302 and the second non-channel region 1305 has shorter length, but the first non-channel region 1304 length is greater than the second non-channel region 1305 length, thus can stagger and first connect porose area 1301 and second and connect the position of porose area 1302 to reduce the impact on resolution, this is because connect porose area need occupy larger area, if two connect porose area and are arranged side by side, then may need larger secondary pixel wide (being parallel on the essence bearing of trend of sweep trace) that first could be held to connect porose area 1301 and second and connect porose area 1302, so will limit the quantity of time pixel, and then affect the design requirement of display panel to high-resolution.In this embodiment, the middle attachment zone 1303 of active layer 130 contiguous first meets porose area 1301 place and has width W 6, and middle attachment zone 1303 contiguous second meets porose area 1302 place and has width W 7, and width W 6 is greater than width W 7.In addition, sweep trace 140 and data line 150 can be straight line wiring patterns.In other embodiments, sweep trace 140 and data line 150 can non-ly be straight lines, but sweep trace 140 and data line 150 have a substantial bearing of trend haply respectively.
In addition, as shown in Figure 6, be positioned at the via 117 that second of active layer 130 connects porose area 1302 and there is bottom margin (or claiming through hole lower edge) 117-1 and top (or claiming through hole upper limb) 117-2, wherein bottom margin 117-1 around area be less than top 117-2 around area, and be positioned at the via 119 that second of active layer 130 connects porose area 1302 also there is bottom margin (or claiming through hole lower edge) 119-1 and top (or claiming through hole upper limb) 119-2, wherein bottom margin 119-1 around area be less than top 119-2 around area, therefore in the planimetric map shown in Fig. 6, via 117 and via 119 have two ring-type borders respectively.In other embodiments, via can be non-circular, such as, can be oval or irregular shape.
In the embodiment in fig 6, middle attachment zone 1303 and not overlapping the first the produced non-channel region 1305, non-channel region 1304, second of sweep trace 140 and the width of the 3rd non-channel region 1306 of active layer 130 are greater than the width in produced first passage district 1308 overlapping with sweep trace 140, middle attachment zone 1303 and second channel district 1309, make the pattern of active layer 130 have the wider and wide thin change that channel region is narrower in non-channel region, reach thus and reduce the resistance of active layer and effect of stray capacitance.
In addition, do not draw the first transparency conducting layer and second transparency conducting layer of display panel 100 in figure 6, in certain embodiments, the display panel 100 of Fig. 6 can adopt the patterned electrodes comprising the second transparency conducting layer 120 of slit 122 as shown in Figure 1; In further embodiments, the slit 122 of the second transparency conducting layer 120 of the display panel 100 of Fig. 6 can not interrupt and cross over data line or cross over sweep trace, looks closely design requirement.In further embodiments, the display panel 100 of Fig. 6 also can adopt the patterned electrodes comprising the first transparency conducting layer 110 of slit 113 as shown in Figure 3, to form the display panels that boundary electric field switches (FFS).
In sum, according to embodiments more of the present utility model, the pattern of the active layer of the thin film transistor (TFT) of display panel is improved, particularly for the active layer be made up of low temperature polycrystalline silicon, allow first of active layer to connect porose area and second and connect the width that middle attachment zone between porose area and the width of not overlapping the produced non-channel region of sweep trace be greater than produced channel region overlapping with sweep trace, middle attachment zone, the pattern of active layer is made to have the wider and wide thin change that channel region is narrower in non-channel region, reach thus and reduce the resistance of active layer and effect of stray capacitance, to promote the electrical property efficiency of thin film transistor (TFT).
Claims (17)
1. a display panel, is characterized in that, this display panel comprises:
First substrate;
Sweep trace and data line, be crisscross arranged on this first substrate;
Active layer, is arranged on this first substrate, and this active layer is between this data line and this first substrate; And
First transparency conducting layer, is arranged on this first substrate, and this first transparency conducting layer is positioned at above this active layer,
Wherein this active layer comprises:
First connects porose area, is electrically connected with this data line;
Second connects porose area, is electrically connected with this first transparency conducting layer; And
Middle attachment zone, first connects porose area and this second connects between porose area at this,
Wherein this middle attachment zone and this sweep trace overlapping comprise first passage district, and this middle attachment zone and this sweep trace not overlapping are a non-channel region, and the width of this non-channel region is greater than the width in this first passage district.
2. display panel as claimed in claim 1, it is characterized in that, this middle attachment zone and this data line partly overlap, and this middle attachment zone comprises the firstth district and the secondth district, lay respectively at the both sides of this data line, wherein this secondth district is positioned at this data line and this second connects between porose area.
3. display panel as claimed in claim 2, it is characterized in that, the width in this firstth district is equal with the width in this secondth district.
4. display panel as claimed in claim 2, it is characterized in that, the width in this firstth district is greater than the width in this secondth district.
5. display panel as claimed in claim 2, it is characterized in that, the width in this firstth district is less than the width in this secondth district.
6. display panel as claimed in claim 1, is characterized in that, this middle attachment zone this first width connecing porose area contiguous is greater than this middle attachment zone this second width connecing porose area contiguous.
7. display panel as claimed in claim 1, is characterized in that, this second width connecing porose area is greater than this first width connecing porose area, and the direction of those width is parallel to this sweep trace.
8. display panel as claimed in claim 1, it is characterized in that, this middle attachment zone and this sweep trace overlapping also comprise second channel district, and the width of this non-channel region is greater than the width in this second channel district.
9. display panel as claimed in claim 8, it is characterized in that, the width in this second channel district is different from the width in this first passage district.
10. display panel as claimed in claim 8, it is characterized in that, the width in this second channel district is identical with the width in this first passage district.
11. display panels as claimed in claim 8, it is characterized in that, a part for this middle attachment zone is between this first passage district and this second channel district, the width of this part of this middle attachment zone is greater than the width in this first passage district, and the width of this part of this middle attachment zone is greater than the width in this second channel district.
12. display panels as claimed in claim 11, is characterized in that, this part of this middle attachment zone has two teats, and these two teats protrude from this first passage district and this second channel district respectively on the direction being parallel to this sweep trace.
13. display panels as claimed in claim 1, it is characterized in that, this display panel also comprises:
Second substrate, is arranged with this first substrate subtend; And
Display medium, is arranged between this first substrate and this second substrate.
14. display panels as claimed in claim 1, it is characterized in that, this display panel also comprises the second transparency conducting layer, is arranged on this first substrate, and this second transparency conducting layer is positioned at above this first transparency conducting layer.
15. display panels as claimed in claim 14, is characterized in that, this second transparency conducting layer is a patterned electrodes comprising multiple slit.
16. display panels as claimed in claim 1, it is characterized in that, this display panel also comprises one second transparency conducting layer, is arranged on this first substrate, and this second transparency conducting layer is positioned at below this first transparency conducting layer.
17. display panels as claimed in claim 16, is characterized in that, this first transparency conducting layer is a patterned electrodes comprising multiple slit, and this second transparency conducting layer has an opening is adjacent to this and second connects porose area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520011129.2U CN204422934U (en) | 2015-01-08 | 2015-01-08 | Display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520011129.2U CN204422934U (en) | 2015-01-08 | 2015-01-08 | Display panel |
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| Publication Number | Publication Date |
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| CN204422934U true CN204422934U (en) | 2015-06-24 |
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| CN201520011129.2U Active CN204422934U (en) | 2015-01-08 | 2015-01-08 | Display panel |
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| Country | Link |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105824160A (en) * | 2015-01-08 | 2016-08-03 | 群创光电股份有限公司 | Display panel |
| CN107367875A (en) * | 2016-05-13 | 2017-11-21 | 群创光电股份有限公司 | Display device |
| CN109087608A (en) * | 2017-06-14 | 2018-12-25 | 乐金显示有限公司 | Gating drive circuit and the display device for utilizing the gating drive circuit |
-
2015
- 2015-01-08 CN CN201520011129.2U patent/CN204422934U/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105824160A (en) * | 2015-01-08 | 2016-08-03 | 群创光电股份有限公司 | Display panel |
| CN105824160B (en) * | 2015-01-08 | 2020-06-16 | 群创光电股份有限公司 | Display panel |
| CN107367875A (en) * | 2016-05-13 | 2017-11-21 | 群创光电股份有限公司 | Display device |
| US10802352B2 (en) | 2016-05-13 | 2020-10-13 | Innolux Corporation | Display device |
| CN112987422A (en) * | 2016-05-13 | 2021-06-18 | 群创光电股份有限公司 | Display device |
| US11474400B2 (en) | 2016-05-13 | 2022-10-18 | Rexon Industrial Corp., Ltd. | Display device |
| CN109087608A (en) * | 2017-06-14 | 2018-12-25 | 乐金显示有限公司 | Gating drive circuit and the display device for utilizing the gating drive circuit |
| CN109087608B (en) * | 2017-06-14 | 2021-12-31 | 乐金显示有限公司 | Gate driving circuit and display device using the same |
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