CN106449706B - Display panel and its manufacturing method - Google Patents
Display panel and its manufacturing method Download PDFInfo
- Publication number
- CN106449706B CN106449706B CN201610901303.XA CN201610901303A CN106449706B CN 106449706 B CN106449706 B CN 106449706B CN 201610901303 A CN201610901303 A CN 201610901303A CN 106449706 B CN106449706 B CN 106449706B
- Authority
- CN
- China
- Prior art keywords
- metal layer
- layer
- film transistor
- display panel
- gate driving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
Present invention discloses a kind of display panel and its manufacturing methods, in display panel provided by the invention and its manufacturing method, the first film transistor of gate driving circuit uses bottom grating structure, second thin film transistor (TFT) of pixel circuit uses top gate structure, and the polysilicon layer of the first film transistor and second thin film transistor (TFT) is same layer, the gate driving circuit is electrically connected with the pixel circuit, realize purpose gate driving circuit being arranged in below pixel circuit, pixel circuit neighboring area is thereby saved, narrow side structure is preferably realized.
Description
Technical field
The present invention relates to display fields, more particularly to a kind of display panel and its manufacturing method.
Background technique
Flat-panel display device has many merits such as thin fuselage, power saving, radiationless, is widely used.It is existing
Flat-panel display device mainly includes liquid crystal display device (Liquid Crystal Display, LCD) and Organic Light Emitting Diode
Display device (Organic Light Emitting Display, OLED).
Organic LED display device have self-luminous, driving voltage is low, luminous efficiency is high, the response time is short, clear
Clear degree with contrast height, nearly 180 ° of visual angles, use temperature range is wide, it can be achieved that Flexible Displays and large area total colouring etc. are many
Advantage is known as being the display device for most having development potentiality by industry.OLED display can be divided into nothing according to driving method
Source matrix type OLED (Passive Matrix OLED, PMOLED) and active array type OLED (Active Matrix OLED,
AMOLED) two major classes.Wherein, AMOLED has the pixel in array arrangement, belongs to active display type, has high comparison
Degree, wide viewing angle, low-power consumption, it is thinner the advantages that, so being typically considered next-generation display technology.
In order to enable AMOLED display screen is beautiful, narrow frame design has become the trend of field of display screen at present.Most often
It is GIP (Gate Drive IC In Panel, onboard gate driving circuit) technology, i.e., directly by gate driving circuit collection
Cheng Yu includes in the substrate of OLED pixel array, which is known as GIP circuit.As shown in Figure 1, being shown in AMOLED
In screen 1, it will usually neighboring area be set on the outside of OLED pixel region 2, to arrange GIP circuit 3 in the neighboring area.Simultaneously
Encapsulation region is also set up in the neighboring area, to realize encapsulation and be sealed to GIP circuit 3, so that AMOLED display screen
It is whole more beautiful.However, the presence of neighboring area often sees the display area (i.e. pixel region) of AMOLED display screen
Get up smaller.And with the continuous improvement of resolution ratio, GIP circuit occupied area is increasing, so that narrow frame design
Difficulty it is higher and higher.
A solution in the prior art is by a part of circuit (such as driving signal transmitting terminal) of neighboring area
It is produced on outside display panel, is arranged independently of OLED display panel, the other parts (including receiving end) of drive signal circuit are then
It is built in OLED display panel, driving signal transmitting terminal is connect with driving signal receiving end without actual track, passes through wireless parties
Formula connection.By the way that this method save neighboring areas, narrow frame is realized.But complex manufacturing process, it needs to additionally introduce other
Structure.
Summary of the invention
The object of the present invention is to provide a kind of display panel and its manufacturing methods, obtain a kind of narrow frame knot of simplicity
Structure.
In order to solve the above technical problems, the present invention provides a kind of display panel, comprising:
Substrate；
Gate driving circuit on the substrate, the gate driving circuit include using the first thin of bottom grating structure
Film transistor；And
Pixel circuit on the gate driving circuit, the pixel circuit include using the second thin of top gate structure
Film transistor；
Wherein, the polysilicon layer of the first film transistor and second thin film transistor (TFT) is same layer, and described
Gate driving circuit is electrically connected with the pixel circuit.
Optionally, for the display panel, the gate driving circuit further includes first on the substrate
Metal layer.
Optionally, for the display panel, the polysilicon layer is located on the first metal layer and with described
One metal layer part overlapping, in grid of the first metal layer as first film transistor of overlapping.
Optionally, for the display panel, the pixel circuit further includes second on the polysilicon layer
Metal layer, the second metal layer is Chong Die with the Polysilicon layer portions, overlapping second metal layer as the second film
The grid of transistor.
Optionally, further include a connecting path for the display panel, connect described the by the connecting path
One metal layer and the second metal layer.
Optionally, for the display panel, the connecting path includes plug and third metal layer, the third gold
Belong to layer to be electrically connected by the plug with the first metal layer and second metal layer.
The present invention also provides a kind of manufacturing methods of display panel, comprising:
Substrate is provided；
Form gate driving circuit on the substrate, the gate driving circuit includes using the first thin of bottom grating structure
Film transistor；
Form pixel circuit on the gate driving circuit, the pixel circuit includes using the second thin of top gate structure
The polysilicon layer of film transistor, the first film transistor and second thin film transistor (TFT) is same layer；And
Connect the gate driving circuit and the pixel circuit.
Optionally, for the manufacturing method of the display panel, gate driving circuit is formed on the substrate, it is described
Gate driving circuit includes the steps that the first film transistor of bottom grating structure includes:
The first metal layer is formed on the substrate；
The polysilicon layer, the polysilicon layer and the first metal layer part weight are formed on the first metal layer
It is folded, in grid of the first metal layer as first film transistor of overlapping.
Optionally, for the manufacturing method of the display panel, pixel circuit is formed on the gate driving circuit,
The pixel circuit includes the steps that the second thin film transistor (TFT) of top gate structure includes:
Second metal layer is formed on the polysilicon layer, the polysilicon layer partly overlaps with the second metal layer,
In grid of the second metal layer as the second thin film transistor (TFT) of overlapping.
Optionally, for the manufacturing method of the display panel, the gate driving circuit and pixel electricity are connected
The step of road includes:
Plug is formed, the plug includes that a part of one end connection the first metal layer connects second metal layer with one end
Another part；And
Third metal layer is formed, the third metal layer is connected with the other end of the plug.
In display panel provided by the invention and its manufacturing method, by the first film transistor system of gate driving circuit
As bottom grating structure, the second thin film transistor (TFT) of pixel circuit is made as top gate structure, and the first film transistor with
The polysilicon layer of second thin film transistor (TFT) is same layer, and the gate driving circuit is electrically connected with the pixel circuit, real
Show and purpose below pixel circuit is arranged in gate driving circuit, has thereby saved pixel circuit neighboring area, preferably
Realize narrow side structure.And compared with prior art, structure of the invention is simple, and manufacturing method is also relatively convenient.
Detailed description of the invention
Fig. 1 is the top view of display panel in the prior art；
Fig. 2 is the schematic top plan view of the display panel in one embodiment of the invention；
Fig. 3 is the structural schematic diagram in Fig. 2 at dotted line frame A；
Fig. 4 is the cross-sectional view in Fig. 3 of the present invention at dotted line L；
Fig. 5 is the cross-sectional view in Fig. 3 of the present invention at dotted line P；
Cross-sectional view when Fig. 6 provides substrate for present invention display panel shown in Fig. 3 at dotted line L and at P；
Fig. 7 is cross-sectional view when present invention display panel shown in Fig. 3 forms the first metal layer at dotted line L and at P；
Fig. 8 is cross-sectional view when present invention display panel shown in Fig. 3 forms polysilicon layer at dotted line L and at P；
Fig. 9 is section view when present invention display panel shown in Fig. 3 forms first film transistor at dotted line L and at P
Figure；
Figure 10 is cross-sectional view when present invention display panel shown in Fig. 3 forms second metal layer at dotted line L and at P；
Figure 11 is section view when present invention display panel shown in Fig. 3 forms the second thin film transistor (TFT) at dotted line L and at P
Figure.
Specific embodiment
Display panel and its manufacturing method of the invention are described in more detail below in conjunction with schematic diagram, wherein table
Showing the preferred embodiment of the present invention, it should be appreciated that those skilled in the art can modify invention described herein, and still
Realize advantageous effects of the invention.Therefore, following description should be understood as the widely known of those skilled in the art, and
It is not intended as limitation of the present invention.
The present invention is more specifically described by way of example referring to attached drawing in the following passage.It is wanted according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
It is exemplified below the preferred embodiment of the display panel and its manufacturing method, clearly to illustrate in of the invention
Hold, it is understood that, the contents of the present invention are not restricted to following embodiment, other pass through those of ordinary skill in the art's
The improvement of conventional technical means is also within thought range of the invention.
As shown in Fig. 2, display panel 10 includes substrate 11 in the present embodiment；Gate driving on the substrate 11
Circuit 12 and pixel circuit 13, wherein the pixel circuit 13 is set to 12 top of gate driving circuit, it is possible thereby to
It realizes and saves 13 neighboring area of pixel circuit, realize narrow side mount structure.
Specifically, as shown in figure 3, the display panel 10 includes: substrate 11, the gate driving on the substrate 11
Circuit and the pixel circuit on the gate driving circuit, wherein the gate driving circuit includes using bottom gate knot
The first film transistor 20 of structure, the pixel circuit include the second thin film transistor (TFT) 30 using top gate structure, and described first
The polysilicon layer 2030 of thin film transistor (TFT) and second thin film transistor (TFT) is same layer (being located in same structure layer), described
Gate driving circuit is electrically connected with the pixel circuit.
Specifically, the gate driving circuit 12 further includes the first metal layer 121 on the substrate 11.By Fig. 3
As it can be seen that the first metal layer 121 includes multiple strip structures, that is, it is patterned, first can be filled between strip structure
Dielectric layer, in order to form subsequent film layer.The shape of the strip structure and arrangement can be set according to actual circuit demand
Determine, for example, rectangle, between each other can be parallel, or it is vertical.
It is then the polysilicon layer 2030 on the first metal layer 121, the polysilicon layer 2030 and described first
Metal layer 121 partly overlaps, and the polysilicon layer 2030 is Chong Die with the first metal layer 121 to form the first film
Transistor 20.Specifically, the first metal layer 121 is used as grid, 121 surface of the first metal layer in first film transistor 20
The polysilicon layer 2030 of (i.e. overlapping) is used as channel, and the polysilicon layer 2030 of channel two sides is then used as source electrode and drain electrode.Thus
It can learn, grid is located at below source electrode and drain electrode, as the first film transistor 20 of bottom grating structure.The polysilicon layer
2030 are patterned, and are filled by second dielectric layer, in order to form subsequent film layer.
It is then second metal layer 131 on the polysilicon layer 2030, the pixel circuit 13 further includes second gold medal
Belong to layer 131.The second metal layer 131 includes two metal lines, that is, is patterned, and the can be filled between two metal lines
Four dielectric layers, in order to form subsequent film layer.Specifically, this two metal line is parallel, in Fig. 3, shows edge and be parallel to
Two metal lines of paper direction arrangement, wherein the metal wire positioned at downside is as scan signal line (SCAN), positioned at upside
Metal wire as transmitting signal wire (EM).The polysilicon layer 2030 partly overlaps with the second metal layer 131, institute
It is Chong Die with the second metal layer 131 to form the second thin film transistor (TFT) 30 to state polysilicon layer 2030.Specifically, thin second
Second metal layer 131 is used as grid in film transistor 30, the polysilicon layer 2030 of (i.e. overlapping) immediately below second metal layer 131
As channel, the polysilicon layer 2030 of channel two sides is then used as source electrode and drain electrode.It is possible thereby to learn, grid is located at source electrode and leakage
Pole top, as the second thin film transistor (TFT) 30 of top gate structure.
The display panel further includes a connecting path, by the connecting path connect the first metal layer 121 with
The second metal layer 131 to realize being electrically connected for the first metal layer 121 and second metal layer 131, namely realizes described
Gate driving circuit 12 is electrically connected with the pixel circuit 13.Specifically, the connecting path includes plug 125 and third gold
Belong to layer 126, the third metal layer 126 is located at the upper layer of the second metal layer 131, and the third metal layer 126 passes through institute
Plug 125 is stated to be electrically connected with the first metal layer 121 and second metal layer 131.According to actual demand, the third metal layer
126 can also be electrically connected the different strip structures of the first metal layer 121 by the plug 125.
The first film transistor 20 in the present invention is illustrated below with reference to Fig. 4.
As shown in figure 4, being provided with the first metal layer 121 on the substrate 11, is provided on the first metal layer 121
One insulating layer 122, polysilicon layer 2030 are arranged on first insulating layer 122, the first metal layer 121 and polysilicon layer 2030
Partly overlap, then overlapping the first metal layer 121 as grid, then make in the polysilicon layer 2030 of overlapping
For channel, and vertical paper direction shown in Fig. 4, polysilicon layer 2030 is in overlapping two sides as source electrode and drain electrode.By
It is located at the lower section of source electrode and drain electrode in grid, therefore the first film transistor 20 is bottom grating structure.The polysilicon layer
2030 tops are covered by second insulating layer 123, further, are also formed with third dielectric layer in the second insulating layer 123
124。
With continued reference to FIG. 4, the plug 125 through the third dielectric layer 124, the second insulating layer 123 and
First insulating layer 122 realizes that one end is connected with the first metal layer 121, and the other end is then situated between with positioned at the third
Third metal layer 126 on matter layer 124 is connected.
The second thin film transistor (TFT) 30 in the present invention is illustrated below with reference to Fig. 5.
It is provided with first medium layer (not labeled) on the substrate 11, is provided with the first insulating layer on the first medium layer
122, it is provided with the polysilicon layer 2030 on first insulating layer 122, is arranged on the polysilicon layer 2030
State second insulating layer 123, be provided with the second metal layer 131 on the second insulating layer, second metal layer 131 with it is described
Polysilicon layer 2030 partly overlaps, then overlapping second metal layer 131 as grid, in the polysilicon layer of overlapping
2030 as channel, and vertical paper direction shown in Fig. 5, polysilicon layer 2030 overlapping two sides as source electrode and
Drain electrode.Since grid is located at the top of source electrode and drain electrode, second thin film transistor (TFT) 30 is top gate structure.Described second
131 top of metal layer is covered by third insulating layer 132, further, is also formed with the 5th medium on the third insulating layer 132
Layer 133.
It is possible thereby to know, the first film transistor 20 being used in gate driving circuit 12 is designed to bottom in the present invention
The second thin film transistor (TFT) 30 being used in pixel circuit 13 is designed to top gate structure, and first film transistor 20 by grid structure
Polysilicon layer 2030 is shared with the second thin film transistor (TFT) 30, realizes and gate driving circuit 12 is arranged under pixel circuit 13
Side, and then realize narrow side structure.
It is illustrated below with reference to manufacturing method of Fig. 3-Figure 11 to display panel of the invention.
Firstly, the substrate 11 can be the common substrate in display panel as shown in fig. 6, providing a substrate 11, such as
Ltps (low temperature polycrystalline silicon) substrate etc., can handle according to old process, skip over not table herein.
Then, gate driving circuit 12 is formed on the substrate 11, the gate driving circuit 12 includes using bottom gate
The first film transistor 20 of structure.
Specifically, including the first sub-step: as shown in fig. 7, forming the first metal layer 121 and being patterned, being allowed to have
There is desired distribution shape, such as the multiple strip structures illustrated in Fig. 3, specifically, can be rectangle, it is of course also possible to
It is other shapes, such as polyline shaped etc. can be parallel to each other between each strip structure, can also be mutually perpendicular to.Described first
The material of metal layer 121 is, for example, metallic aluminium (Al), thallium (Ta), crome metal (Cr) etc..It is filled in place of patterning removal
First medium layer (i.e. film layer unlabeled on substrate 11 at P in Fig. 7), the material of the first medium layer can for oxide,
Other materials also can be used in nitride or nitrogen oxides, certainly, the first medium layer, and the present invention is to this and not limits.
Second sub-step: as shown in figure 8, forming the first insulation on the first metal layer 121 (and first medium layer)
Layer 122 forms one layer of polysilicon layer 2030 on first insulating layer 122, and carries out pattern to the polysilicon layer 2030
Change, fills second dielectric layer in place of patterning removal.The first metal layer 121 and the polysilicon layer 2030 have part
Overlapping, also, preferably, the first metal layer 121 and the orthogonal thereto overlapping of the polysilicon layer 2030, in order to process, and
The reliability for the thin film transistor (TFT) for ensuring to obtain.In overlapping, the first metal layer 121 is used as grid, the polysilicon layer
2030 be used as channel, and the polysilicon layer 2030 in overlapping two sides as source electrode and drain electrode.It, can also be into according to needing
A certain amount of ion doping of row, such as phosphorus doping etc., to improve conductivity.Then, as shown in figure 9, in the polysilicon layer
Around 2030 and top forms second insulating layer 123, and polysilicon layer 2030 is covered.So far, the formation of first film transistor 20.
It is the first film transistor 20 of bottom grating structure since grid is located at below source electrode and drain electrode.It, can also be according to needing
Third dielectric layer 124 is formed in the second insulating layer 123.First insulating layer 122, second dielectric layer, second insulating layer
123 and the material of third dielectric layer 124 can be oxide, nitride or nitrogen oxides, certainly, first insulating layer
122, other materials also can be used in second dielectric layer, second insulating layer 123 and third dielectric layer 124, and the present invention is to this and refuses
Limitation.
Then, pixel circuit 13 is formed on the gate driving circuit 12, the pixel circuit 13 includes using top-gated
Second thin film transistor (TFT) 30 of structure, the first film transistor 20 and the polysilicon layer of second thin film transistor (TFT) 30 are
Same layer.
Specifically, including: as shown in Figure 10, after second insulating layer 123 covers polysilicon layer 2030, described second
Second metal layer 131 is formed on insulating layer 123.The case where for forming third dielectric layer 124, it can will need to form the second gold medal
Belong to the third dielectric layer 124 at 131 region of layer to remove.Likewise, patterning the second metal layer 131, with institute
Desired shape.The material of the second metal layer 131 is, for example, metallic aluminium (Al), thallium (Ta), crome metal (Cr) etc..?
Patterning removal place fills the 4th dielectric layer.Such as in embodiments of the present invention, the second metal layer 131 includes two gold
Belong to line, specifically, this two metal line is parallel, in Fig. 3, show along two metal lines for being parallel to the arrangement of paper direction,
Wherein, the metal wire positioned at downside is as scan signal line (SCAN), and the metal wire positioned at upside is as transmitting signal wire
(EM).The polysilicon layer 2030 partly overlaps with the second metal layer 131, also, preferably, second metal
Layer 131 and the orthogonal thereto overlapping of the polysilicon layer 2030, in order to process, and the reliability for the thin film transistor (TFT) for ensuring to obtain.
In overlapping, the second metal layer 131 is used as grid, and the polysilicon layer 2030 is used as channel, and the polysilicon layer
2030 in overlapping two sides as source electrode and drain electrode.According to needs, a certain amount of ion doping, such as phosphorus doping can also be carried out
Deng to improve conductivity.Then, as shown in figure 11, third insulating layer is formed with top around the second metal layer 131
132, second metal layer 131 is covered.So far, the second thin film transistor (TFT) 30 formation.Since grid is located above source electrode and drain electrode,
It therefore is the second thin film transistor (TFT) 30 of top gate structure.According to needs, the 5th can also be formed on the third insulating layer 132
Dielectric layer 133.(in view of third insulating layer 132 and 133 main function of the 5th dielectric layer are covering second metal layers, therefore
Third insulating layer 132 and the 5th dielectric layer 133 are not illustrated in Figure 11 at L.) the 4th dielectric layer, third insulating layer 132 and
The material of five dielectric layers 133 can be oxide, nitride or nitrogen oxides, certainly, the 4th dielectric layer, third insulation
Other materials also can be used in layer 132 and the 5th dielectric layer 133, and the present invention is to this and not limits.
Finally, the gate driving circuit 12 is connected with the pixel circuit 13.Specifically, forming plug 125, example
Such as, a part of the plug 125 runs through the third dielectric layer 124, second insulating layer 123 and the first insulating layer 122, realizes
One end is connected to the first metal layer 121, and another part of the plug 125 then runs through the 5th dielectric layer 133, third
Insulating layer 132 realizes that one end is connected to the second metal layer 131；After the formation of plug 125, third metal layer 126 is formed,
The third metal layer 126 is connected with the other end of the plug 125, thus the gate driving circuit 12 and the pixel
Circuit 13 is electrically connected.According to demand, as shown in figure 3, the third metal layer 126 can also be by the plug 125 by first
The different strip structures of metal layer 121 are connected.
In display panel provided by the invention and its manufacturing method, by the first film transistor system of gate driving circuit
As bottom grating structure, the second thin film transistor (TFT) of pixel circuit is made as top gate structure, and the first film transistor with
The polysilicon layer of second thin film transistor (TFT) is same layer, and the gate driving circuit is electrically connected with the pixel circuit, real
Show and purpose below pixel circuit is arranged in gate driving circuit, has thereby saved pixel circuit neighboring area, preferably
Realize narrow side structure.And compared with prior art, structure of the invention is simple, and manufacturing method is also relatively convenient.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (10)
1. a kind of display panel, comprising:
Substrate；
Gate driving circuit on the substrate, the gate driving circuit include brilliant using the first film of bottom grating structure
Body pipe；And
Pixel circuit on the gate driving circuit, the pixel circuit include brilliant using the second film of top gate structure
Body pipe；
Wherein, the polysilicon layer of the first film transistor and second thin film transistor (TFT) is same layer, and the grid
Driving circuit is electrically connected with the pixel circuit.
2. display panel as described in claim 1, which is characterized in that the gate driving circuit further includes being located at the substrate
On the first metal layer.
3. display panel as claimed in claim 2, which is characterized in that the polysilicon layer is located on the first metal layer simultaneously
It partly overlaps with the first metal layer, in grid of the first metal layer as first film transistor of overlapping.
4. display panel as claimed in claim 2, which is characterized in that the pixel circuit further includes being located at the polysilicon layer
On second metal layer, the second metal layer is Chong Die with the Polysilicon layer portions, in the second metal layer conduct of overlapping
The grid of second thin film transistor (TFT).
5. display panel as claimed in claim 4, which is characterized in that further include a connecting path, pass through the connecting path
Connect the first metal layer and the second metal layer.
6. display panel as claimed in claim 5, which is characterized in that the connecting path includes plug and third metal layer,
The third metal layer is electrically connected by the plug with the first metal layer and second metal layer.
7. a kind of manufacturing method of display panel, comprising:
Substrate is provided；
Gate driving circuit is formed on the substrate, and the gate driving circuit includes brilliant using the first film of bottom grating structure
Body pipe；
Pixel circuit is formed on the gate driving circuit, the pixel circuit includes brilliant using the second film of top gate structure
The polysilicon layer of body pipe, the first film transistor and second thin film transistor (TFT) is same layer；And
Connect the gate driving circuit and the pixel circuit.
8. the manufacturing method of display panel as claimed in claim 7, which is characterized in that form gate driving on the substrate
The step of circuit includes:
The first metal layer is formed on the substrate；
The polysilicon layer is formed on the first metal layer, the polysilicon layer partly overlaps with the first metal layer,
In grid of the first metal layer as first film transistor of overlapping.
9. the manufacturing method of display panel as claimed in claim 8, which is characterized in that formed on the gate driving circuit
The step of pixel circuit includes:
Second metal layer is formed on the polysilicon layer, the polysilicon layer partly overlaps with the second metal layer, in weight
Grid of the second metal layer at folded place as the second thin film transistor (TFT).
10. the manufacturing method of display panel as claimed in claim 8, which is characterized in that connect the gate driving circuit with
The step of pixel circuit includes:
Plug is formed, the plug includes that a part of one end connection the first metal layer connects the another of second metal layer with one end
Part；And
Third metal layer is formed, the third metal layer is connected with the other end of the plug.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610901303.XA CN106449706B (en) | 2016-10-17 | 2016-10-17 | Display panel and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610901303.XA CN106449706B (en) | 2016-10-17 | 2016-10-17 | Display panel and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106449706A CN106449706A (en) | 2017-02-22 |
| CN106449706B true CN106449706B (en) | 2019-05-03 |
Family
ID=58174187
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610901303.XA Active CN106449706B (en) | 2016-10-17 | 2016-10-17 | Display panel and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106449706B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102612390B1 (en) | 2018-12-19 | 2023-12-12 | 엘지디스플레이 주식회사 | Display panel and display device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101958339A (en) * | 2009-07-15 | 2011-01-26 | 三星移动显示器株式会社 | Organic light-emitting display device and manufacture method thereof |
| JP2012019122A (en) * | 2010-07-09 | 2012-01-26 | Casio Comput Co Ltd | Transistor structure, method for manufacturing transistor structure, and light emitting device |
| CN103077957A (en) * | 2013-02-22 | 2013-05-01 | 深圳市华星光电技术有限公司 | Active matrix type organic light emitting diode display device and manufacturing method thereof |
| CN104716091A (en) * | 2013-12-13 | 2015-06-17 | 昆山国显光电有限公司 | Array substrate preparation method, array substrate, and organic light-emitting display device |
| CN104752426A (en) * | 2013-12-26 | 2015-07-01 | 昆山国显光电有限公司 | Common-gate stereoscopic CMOS (Complementary Metal-Oxide-Semiconductor Transistor) device, OLED (Organic Light Emitting Diode) device and manufacturing method thereof |
| WO2016013264A1 (en) * | 2014-07-23 | 2016-01-28 | ソニー株式会社 | Display device, method for manufacturing display device, and electronic device |
| CN105514118A (en) * | 2015-12-24 | 2016-04-20 | 昆山国显光电有限公司 | Thin film transistor array substrate, preparation method thereof, display panel and display device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100846968B1 (en) * | 2007-05-21 | 2008-07-17 | 삼성에스디아이 주식회사 | Organic light-emitting display device |
-
2016
- 2016-10-17 CN CN201610901303.XA patent/CN106449706B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101958339A (en) * | 2009-07-15 | 2011-01-26 | 三星移动显示器株式会社 | Organic light-emitting display device and manufacture method thereof |
| JP2012019122A (en) * | 2010-07-09 | 2012-01-26 | Casio Comput Co Ltd | Transistor structure, method for manufacturing transistor structure, and light emitting device |
| CN103077957A (en) * | 2013-02-22 | 2013-05-01 | 深圳市华星光电技术有限公司 | Active matrix type organic light emitting diode display device and manufacturing method thereof |
| CN104716091A (en) * | 2013-12-13 | 2015-06-17 | 昆山国显光电有限公司 | Array substrate preparation method, array substrate, and organic light-emitting display device |
| CN104752426A (en) * | 2013-12-26 | 2015-07-01 | 昆山国显光电有限公司 | Common-gate stereoscopic CMOS (Complementary Metal-Oxide-Semiconductor Transistor) device, OLED (Organic Light Emitting Diode) device and manufacturing method thereof |
| WO2016013264A1 (en) * | 2014-07-23 | 2016-01-28 | ソニー株式会社 | Display device, method for manufacturing display device, and electronic device |
| CN105514118A (en) * | 2015-12-24 | 2016-04-20 | 昆山国显光电有限公司 | Thin film transistor array substrate, preparation method thereof, display panel and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106449706A (en) | 2017-02-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102466933B (en) | Pixel structure of liquid crystal display and method for manufacturing pixel structure | |
| CN104681582B (en) | Organic light emitting display plate and the oganic light-emitting display device for including this display board | |
| CN103941507B (en) | Array substrate, display panel and display device | |
| CN100403576C (en) | Dual panel-type organic electroluminescent display device and method for fabricating the same | |
| CN104600200B (en) | Array substrate and display panel | |
| CN104777653B (en) | Array base palte, liquid crystal display panel and liquid crystal display device | |
| CN105789266A (en) | OLED array substrate, making method thereof and display device | |
| CN104900653B (en) | TFT layout structures | |
| CN103760702B (en) | Display panel | |
| CN209691758U (en) | Display panel and display device | |
| CN102402087B (en) | Pixel structure, active element array substrate and flat display panel | |
| CN105068344B (en) | Display panel and pixel array thereof | |
| CN106409845A (en) | Switch element, the preparation method of the switch element, array substrate and display apparatus | |
| CN104637439A (en) | Organic light emitting display panel and organic light emitting display device including the same | |
| CN104749838B (en) | Thin film transistor base plate and the liquid crystal display device using the thin film transistor base plate | |
| CN104134672B (en) | Thin film transistor substrate and organic light emitting device using the same | |
| CN105304034A (en) | Display apparatus | |
| TWI567950B (en) | Display panels | |
| CN102651403A (en) | Thin film transistor, array substrate and manufacturing method of array substrate and display panel | |
| CN104966721A (en) | Array substrate and manufacturing method thereof, display panel and display apparatus | |
| WO2018040560A1 (en) | Array substrate, display panel and display device | |
| CN102881689B (en) | Array substrate and manufacturing method thereof and LCD panel | |
| CN104409462A (en) | Array substrate, manufacturing method thereof and display device | |
| CN103489892A (en) | Array substrate, preparing method of array substrate and display device of array substrate | |
| CN202126557U (en) | Array substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |