CN106449706A - Display panel and manufacturing method thereof - Google Patents
Display panel and manufacturing method thereof Download PDFInfo
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- CN106449706A CN106449706A CN201610901303.XA CN201610901303A CN106449706A CN 106449706 A CN106449706 A CN 106449706A CN 201610901303 A CN201610901303 A CN 201610901303A CN 106449706 A CN106449706 A CN 106449706A
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- metal layer
- layer
- film transistor
- gate driver
- display floater
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
Abstract
The invention discloses a display panel and a manufacturing method thereof. According to the display panel and the manufacturing method thereof, a first thin-film transistor of a grid drive circuit adopts a bottom-grid structure, a second thin-film transistor of a pixel circuit adopts a top-grid structure, and the first thin-film transistor and the second thin-film transistor share one polycrystalline silicon layer, the grid drive circuit is electrically connected with the pixel circuit, thus the aim of arranging the grid drive circuit below the pixel circuit is achieved, surrounding area of the pixel circuit is saved and a narrow-edge structure is better obtained.
Description
Technical field
The present invention relates to display field, more particularly to a kind of display floater and its manufacture method.
Background technology
Flat-panel display device has that fuselage is thin, power saving, the many merits such as radiationless, be widely used.Existing
Flat-panel display device mainly includes liquid crystal indicator (Liquid Crystal Display, LCD) and Organic Light Emitting Diode
Display device (Organic Light Emitting Display, OLED).
Organic LED display device has self-luminous, driving voltage is low, luminous efficiency is high, response time is short, clear
, with contrast is high, nearly 180 ° of visual angles, use temperature range width, achievable Flexible Displays and large area total colouring etc. are many for clear degree
Advantage, is known as by industry being the display device having development potentiality most.OLED display can be divided into no according to type of drive
Source matrix type OLED (Passive Matrix OLED, PMOLED) and active array type OLED (Active Matrix OLED,
AMOLED) two big class.Wherein, AMOLED has the pixel of the arrangement in array, belongs to active display type, has high contrast
The advantages of degree, wide viewing angle, low-power consumption, thickness are thinner, so be typically considered Display Technique of future generation.
So that AMOLED display screen is attractive in appearance, narrow frame design has become as the trend in display screen field at present.The most normal
It is GIP (Gate Drive IC In Panel, onboard gate driver circuit) technology, that is, directly by gate driver circuit collection
Become in the substrate including OLED pixel array, this gate driver circuit is referred to as GIP circuit.As shown in figure 1, showing in AMOLED
It will usually arrange neighboring area in OLED pixel region 2 outside, to arrange GIP circuit 3 in this neighboring area in screen 1.Simultaneously
Also set up encapsulation region in this neighboring area, to realize encapsulation and GIP circuit 3 sealed, so that AMOLED display screen
Overall more attractive in appearance.However, the presence of neighboring area often makes the viewing area (i.e. pixel region) of AMOLED display screen see
Get up less.And the continuous improvement with resolution, GIP circuit occupied area is increasing, so that narrow frame design
Difficulty more and more higher.
A solution of the prior art is by a part of circuit (such as drive signal transmitting terminal) of neighboring area
It is produced on outside display floater, independent of OLED display panel setting, the other parts (inclusion receiving terminal) of drive signal circuit are then
It is built in OLED display panel, drive signal transmitting terminal is connected with drive signal receiving terminal no actual track, by wireless parties
Formula connects.By this method saving neighboring area, realize narrow frame.But complex manufacturing process, needs to additionally introduce other
Structure.
Content of the invention
It is an object of the invention to, a kind of display floater and its manufacture method are provided, obtain a kind of easy narrow frame knot
Structure.
For solving above-mentioned technical problem, the present invention provides a kind of display floater, including：
Substrate；
Gate driver circuit on described substrate, described gate driver circuit includes first thin using bottom grating structure
Film transistor；And
Image element circuit on described gate driver circuit, described image element circuit includes second thin using top gate structure
Film transistor；
Wherein, described first film transistor and the polysilicon layer of described second thin film transistor (TFT) are same layer, and described
Gate driver circuit is electrically connected with described image element circuit.
Optionally, for described display floater, described gate driver circuit also includes first on described substrate
Metal level.
Optionally, for described display floater, described polysilicon layer is located on described the first metal layer and with described the
One metal layer part is overlapping, overlapping the first metal layer as first film transistor grid.
Optionally, for described display floater, described image element circuit also includes second on described polysilicon layer
Metal level, described second metal layer is overlapping with described Polysilicon layer portions, overlapping second metal layer as the second thin film
The grid of transistor.
Optionally, for described display floater, also include a connecting path, connect described the by described connecting path
One metal level and described second metal layer.
Optionally, for described display floater, described connecting path includes connector and the 3rd metal level, described 3rd gold medal
Belong to layer to electrically connect with described the first metal layer and second metal layer by described connector.
The present invention also provides a kind of manufacture method of display floater, including：
Substrate is provided；
Form gate driver circuit on the substrate, described gate driver circuit includes first thin using bottom grating structure
Film transistor；
Image element circuit is formed on described gate driver circuit, described image element circuit includes second thin using top gate structure
Film transistor, described first film transistor is same layer with the polysilicon layer of described second thin film transistor (TFT)；And
Connect described gate driver circuit and described image element circuit.
Optionally, for the manufacture method of described display floater, form gate driver circuit on the substrate, described
The step that gate driver circuit includes the first film transistor of bottom grating structure includes：
Form the first metal layer on the substrate；
Described polysilicon layer is formed on described the first metal layer, described polysilicon layer is partly weighed with described the first metal layer
Folded, overlapping the first metal layer as first film transistor grid.
Optionally, for the manufacture method of described display floater, described gate driver circuit forms image element circuit,
The step that described image element circuit includes the second thin film transistor (TFT) of top gate structure includes：
Second metal layer is formed on described polysilicon layer, described polysilicon layer is partly overlapped with described second metal layer,
Overlapping second metal layer as the second thin film transistor (TFT) grid.
Optionally, for the manufacture method of described display floater, described gate driver circuit and described pixel electricity are connected
The step on road includes：
Form connector, described connector includes a part for one end connection the first metal layer and one end connects second metal layer
Another part；And
Form the 3rd metal level, described 3rd metal level is connected with the other end of described connector.
In the display floater that the present invention provides and its manufacture method, by the first film transistor system of gate driver circuit
As bottom grating structure, the second thin film transistor (TFT) of image element circuit is made as top gate structure, and described first film transistor with
The polysilicon layer of described second thin film transistor (TFT) is same layer, and described gate driver circuit is electrically connected with described image element circuit, real
Show and gate driver circuit has been arranged on purpose below image element circuit, thereby saving image element circuit neighboring area, preferably
Achieve narrow side structure.And compared to existing technology, the structure of the present invention is simple, and manufacture method is also more convenient.
Brief description
Fig. 1 is the top view of display floater of the prior art；
Fig. 2 is the schematic top plan view of the display floater in one embodiment of the invention；
Fig. 3 is the structural representation at dotted line frame A in Fig. 2；
Fig. 4 is the sectional view at dotted line L in Fig. 3 of the present invention；
Fig. 5 is the sectional view at dotted line P in Fig. 3 of the present invention；
Display floater shown in Fig. 3 of the present invention for the Fig. 6 provides the sectional view at dotted line L and at P during substrate；
Fig. 7 is the sectional view that the display floater shown in Fig. 3 of the present invention forms during the first metal layer at dotted line L and at P；
Fig. 8 is the sectional view that the display floater shown in Fig. 3 of the present invention forms during polysilicon layer at dotted line L and at P；
Fig. 9 is the section view that the display floater shown in Fig. 3 of the present invention forms during first film transistor at dotted line L and at P
Figure；
Figure 10 is the sectional view that the display floater shown in Fig. 3 of the present invention forms during second metal layer at dotted line L and at P；
Figure 11 is the section view that the display floater shown in Fig. 3 of the present invention forms during the second thin film transistor (TFT) at dotted line L and at P
Figure.
Specific embodiment
Below in conjunction with schematic diagram, the display floater of the present invention and its manufacture method are described in more detail, wherein table
Show the preferred embodiments of the present invention it should be appreciated that those skilled in the art can change invention described herein, and still
Realize the advantageous effects of the present invention.Therefore, description below be appreciated that widely known for those skilled in the art, and
It is not intended as limitation of the present invention.
Referring to the drawings the present invention more particularly described below by way of example in the following passage.Will according to following explanation and right
Seek book, advantages and features of the invention will become apparent from.It should be noted that, accompanying drawing is all in the form of very simplification and all using non-
Accurately ratio, only in order to purpose that is convenient, lucidly aiding in illustrating the embodiment of the present invention.
It is exemplified below the preferred embodiment of described display floater and its manufacture method, clearly to illustrate in the present invention
Hold it is understood that, present disclosure is not restricted to following examples, and other pass through those of ordinary skill in the art
The improvement of routine techniquess means is also within the thought range of the present invention.
As shown in Fig. 2 in the present embodiment, display floater 10 includes substrate 11；Raster data model on described substrate 11
Circuit 12 and image element circuit 13, wherein said image element circuit 13 is arranged above described gate driver circuit 12, thus permissible
Realize saving image element circuit 13 neighboring area, realize narrow frame structure.
Specifically, as shown in figure 3, described display floater 10 includes：Substrate 11, the raster data model being located on described substrate 11
Circuit and the image element circuit being located on described gate driver circuit, wherein, described gate driver circuit includes tying using bottom gate
The first film transistor 20 of structure, described image element circuit includes the second thin film transistor (TFT) 30 using top gate structure, and described first
Thin film transistor (TFT) is same layer (being located in same structure layer) with the polysilicon layer 2030 of described second thin film transistor (TFT), described
Gate driver circuit is electrically connected with described image element circuit.
Specifically, described gate driver circuit 12 also includes the first metal layer 121 on described substrate 11.By Fig. 3
It can be seen that, described the first metal layer 121 includes multiple list structures, that is, be patterned, and can fill first between list structure
Dielectric layer, in order to form follow-up film layer.The shape of described list structure and arrangement can set according to side circuit demand
Fixed, for example, rectangle, each other can be parallel, or vertically.
Described the first metal layer 121 is then described polysilicon layer 2030, described polysilicon layer 2030 and described first
Metal level 121 partly overlaps, described polysilicon layer 2030 overlapping with described the first metal layer 121 to define the first film
Transistor 20.Specifically, in first film transistor 20 the first metal layer 121 as grid, directly over the first metal layer 121
, as raceway groove, the polysilicon layer 2030 of raceway groove both sides is then as source electrode and drain electrode for the polysilicon layer 2030 of (i.e. overlapping).Thus
Can learn, grid is located at below source electrode and drain electrode, as the first film transistor 20 of bottom grating structure.Described polysilicon layer
2030 are patterned, and are filled by second dielectric layer, in order to form follow-up film layer.
Described polysilicon layer 2030 is then second metal layer 131, described image element circuit 13 also includes described second gold medal
Belong to layer 131.Described second metal layer 131 includes two metal line, that is, be patterned, and can fill between two metal line
Four dielectric layers, in order to form follow-up film layer.Specifically, this two metal line is parallel, in such as Fig. 3, show along parallel to
Paper direction arrangement two metal line, wherein, the metal wire positioned at downside as scan signal line (SCAN), positioned at upside
Metal wire as transmission signal line (EM).Described polysilicon layer 2030 is partly overlapped with described second metal layer 131, institute
State polysilicon layer 2030 overlapping with described second metal layer 131 to define the second thin film transistor (TFT) 30.Specifically, thin second
In film transistor 30, second metal layer 131 is as grid, the polysilicon layer 2030 of second metal layer 131 underface (i.e. overlapping)
As raceway groove, the polysilicon layer 2030 of raceway groove both sides is then as source electrode and drain electrode.Thus can learn, grid is located at source electrode and leakage
Above pole, the second thin film transistor (TFT) 30 of as top gate structure.
Described display floater also includes a connecting path, by described connecting path connect described the first metal layer 121 with
Described second metal layer 131, thus realizing the electrical connection of the first metal layer 121 and second metal layer 131, namely achieves described
Gate driver circuit 12 and the electrical connection of described image element circuit 13.Specifically, described connecting path includes connector 125 and the 3rd gold medal
Belong to layer 126, described 3rd metal level 126 is located at the upper strata of described second metal layer 131, described 3rd metal level 126 passes through institute
State connector 125 to electrically connect with described the first metal layer 121 and second metal layer 131.According to actual demand, described 3rd metal level
The different list structures of the first metal layer 121 can also be electrically connected by 126 by described connector 125.
With reference to Fig. 4, the first film transistor 20 in the present invention is illustrated.
As shown in figure 4, being provided with the first metal layer 121 on the substrate 11, described the first metal layer 121 is provided with
One insulating barrier 122, polysilicon layer 2030 is arranged on described first insulating barrier 122, the first metal layer 121 and polysilicon layer 2030
Partly overlap, then overlapping the first metal layer 121 as grid, then make in the polysilicon layer 2030 of overlapping
For raceway groove, and in paper direction vertical shown in Fig. 4, polysilicon layer 2030 is in overlapping both sides as source electrode and drain electrode.By
It is located at source electrode and the lower section of drain electrode in grid, therefore described first film transistor 20 is bottom grating structure.Described polysilicon layer
Covered by the second insulating barrier 123 above in the of 2030, further, described second insulating barrier 123 is also formed with the 3rd dielectric layer
124.
Please continue to refer to Fig. 4, described connector 125 run through described 3rd dielectric layer 124, described second insulating barrier 123 and
Described first insulating barrier 122, is realized one end and is connected with described the first metal layer 121, and the other end is then situated between with positioned at the described 3rd
The 3rd metal level 126 on matter layer 124 is connected.
With reference to Fig. 5, the second thin film transistor (TFT) 30 in the present invention is illustrated.
It is provided with first medium layer (non-label) on the substrate 11, described first medium layer is provided with the first insulating barrier
122, described first insulating barrier 122 is provided with described polysilicon layer 2030, described polysilicon layer 2030 is arranged
State the second insulating barrier 123, described second metal layer 131 be provided with described second insulating barrier, second metal layer 131 with described
Polysilicon layer 2030 partly overlaps, then overlapping second metal layer 131 as grid, in the polysilicon layer of overlapping
2030 as raceway groove, and in paper direction vertical shown in Fig. 5, polysilicon layer 2030 overlapping both sides as source electrode and
Drain electrode.Because grid is located at source electrode and the top of drain electrode, therefore described second thin film transistor (TFT) 30 is top gate structure.Described second
Covered by the 3rd insulating barrier 132 above metal level 131, further, described 3rd insulating barrier 132 is also formed with the 5th medium
Layer 133.
Thus could be aware that, in the present invention, the first film transistor 20 being used in gate driver circuit 12 is designed to bottom
Grid structure, the be used in image element circuit 13 second thin film transistor (TFT) 30 is designed to top gate structure, and first film transistor 20
Share polysilicon layer 2030 with the second thin film transistor (TFT) 30 it is achieved that being arranged on gate driver circuit 12 under image element circuit 13
Side, and then realize narrow side structure.
Manufacture method with reference to the display floater to the present invention for Fig. 3-Figure 11 illustrates.
First, as shown in fig. 6, providing a substrate 11, described substrate 11 can be the conventional substrate in display floater, for example
Ltps (low temperature polycrystalline silicon) substrate etc., can be processed according to old process, here skips over not table.
Then, gate driver circuit 12 is formed on described substrate 11, described gate driver circuit 12 includes adopting bottom gate
The first film transistor 20 of structure.
Specifically, including the first sub-step：As shown in fig. 7, forming the first metal layer 121 being patterned, it is allowed to have
There is desired distribution shape, such as the multiple list structures illustrated in Fig. 3, specifically, can be rectangle, it is of course also possible to
It is other shapes, such as polyline shaped etc., can be parallel to each other it is also possible to be mutually perpendicular between each list structure.Described first
The material of metal level 121 is, for example, metallic aluminium (Al), thallium (Ta), crome metal (Cr) etc..Remove part filling in patterning
The first medium layer film layer of non-label (i.e. on substrate 11 at P in Fig. 7), the material of described first medium layer can for oxide,
Nitride or nitrogen oxides, certainly, described first medium layer also can adopt other materials, and the present invention limits to this and not.
Second sub-step：As shown in figure 8, in upper formation the first insulation of described the first metal layer 121 (and first medium layer)
Layer 122, forms one layer of polysilicon layer 2030 on described first insulating barrier 122, and carries out pattern to described polysilicon layer 2030
Change, remove part filling second dielectric layer in patterning.Described the first metal layer 121 and described polysilicon layer 2030 have part
Overlap, and, preferably, described the first metal layer 121 and the orthogonal thereto overlap of described polysilicon layer 2030, in order to process, and
Guarantee the reliability of the thin film transistor (TFT) of acquisition.In overlapping, described the first metal layer 121 as grid, described polysilicon layer
2030 as raceway groove, and described polysilicon layer 2030 in overlapping both sides as source electrode and drain electrode.According to needing, can also enter
A certain amount of ion doping of row, such as phosphorus doping etc., to improve conductivity.Then, as shown in figure 9, in described polysilicon layer
Around 2030 and top forms the second insulating barrier 123, and polysilicon layer 2030 is covered.So far, first film transistor 20 is formed.
Because grid is located at below source electrode and drain electrode, therefore for the first film transistor 20 of bottom grating structure.According to needing, can also be
3rd dielectric layer 124 is formed on described second insulating barrier 123.Described first insulating barrier 122, second dielectric layer, the second insulating barrier
123 and the 3rd the material of dielectric layer 124 can be oxide, nitride or nitrogen oxides, certainly, described first insulating barrier
122nd, second dielectric layer, the second insulating barrier 123 and the 3rd dielectric layer 124 also can adopt other materials, and the present invention to this and refuses
Limit.
Then, image element circuit 13 is formed on described gate driver circuit 12, described image element circuit 13 includes adopting top-gated
Second thin film transistor (TFT) 30 of structure, described first film transistor 20 with the polysilicon layer of described second thin film transistor (TFT) 30 is
Same layer.
Specifically, including：As shown in Figure 10, after the second insulating barrier 123 covers polysilicon layer 2030, described second
Second metal layer 131 is formed on insulating barrier 123.When forming the 3rd dielectric layer 124, can will need to form the second gold medal
Belong to the 3rd dielectric layer 124 at layer 131 region to remove.Likewise, making described second metal layer 131 pattern, to have
Desired shape.The material of described second metal layer 131 is, for example, metallic aluminium (Al), thallium (Ta), crome metal (Cr) etc..?
Patterning removes part filling the 4th dielectric layer.For example in embodiments of the present invention, described second metal layer 131 includes two gold
Belong to line, specifically, this two metal line is parallel, in such as Fig. 3, show along two metal line parallel to the arrangement of paper direction,
Wherein, the metal wire positioned at downside is as scan signal line (SCAN), positioned at upside metal wire as transmission signal line
(EM).Described polysilicon layer 2030 is partly overlapped with described second metal layer 131, and, preferably, described second metal
Layer 131 and the orthogonal thereto overlap of described polysilicon layer 2030, in order to process, and guarantee the reliability of the thin film transistor (TFT) of acquisition.
In overlapping, as grid, described polysilicon layer 2030 is as raceway groove, and described polysilicon layer for described second metal layer 131
2030 in overlapping both sides as source electrode and drain electrode.According to needing, a certain amount of ion doping, such as phosphorus doping can also be carried out
Deng to improve conductivity.Then, as shown in figure 11, form the 3rd insulating barrier with top around described second metal layer 131
132, second metal layer 131 is covered.So far, the second thin film transistor (TFT) 30 is formed.Because grid is located above source electrode and drain electrode,
It is therefore the second thin film transistor (TFT) 30 of top gate structure.According to needing, the 5th can also be formed on described 3rd insulating barrier 132
Dielectric layer 133.(it is to cover second metal layer in view of the 3rd insulating barrier 132 and the 5th dielectric layer 133 Main Function, therefore exists
The 3rd insulating barrier 132 and the 5th dielectric layer 133 is not illustrated at L in Figure 11.) described 4th dielectric layer, the 3rd insulating barrier 132 and
The material of five dielectric layers 133 can be oxide, nitride or nitrogen oxides, certainly, described 4th dielectric layer, the 3rd insulation
Layer 132 and the 5th dielectric layer 133 also can adopt other materials, and the present invention limits to this and not.
Finally, described gate driver circuit 12 is connected with described image element circuit 13.Specifically, connector 125, example are formed
As a part for described connector 125 runs through described 3rd dielectric layer 124, the second insulating barrier 123 and the first insulating barrier 122, realizes
One end connects to described the first metal layer 121, and another part of described connector 125 then runs through described 5th dielectric layer the 133, the 3rd
Insulating barrier 132, realizes one end and connects to described second metal layer 131；After connector 125 is formed, form the 3rd metal level 126,
Described 3rd metal level 126 is connected with the other end of described connector 125, thus described gate driver circuit 12 and described pixel
Circuit 13 electrically connects.According to demand, as shown in figure 3, described 3rd metal level 126 can also be by described connector 125 by first
The different list structures of metal level 121 are connected.
In the display floater that the present invention provides and its manufacture method, by the first film transistor system of gate driver circuit
As bottom grating structure, the second thin film transistor (TFT) of image element circuit is made as top gate structure, and described first film transistor with
The polysilicon layer of described second thin film transistor (TFT) is same layer, and described gate driver circuit is electrically connected with described image element circuit, real
Show and gate driver circuit has been arranged on purpose below image element circuit, thereby saving image element circuit neighboring area, preferably
Achieve narrow side structure.And compared to existing technology, the structure of the present invention is simple, and manufacture method is also more convenient.
Obviously, those skilled in the art can carry out the various changes and modification essence without deviating from the present invention to the present invention
God and scope.So, if these modifications of the present invention and modification belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprise these changes and modification.
Claims (10)
1. a kind of display floater, including：
Substrate；
Gate driver circuit on described substrate, the first film that described gate driver circuit is included using bottom grating structure is brilliant
Body pipe；And
Image element circuit on described gate driver circuit, the second thin film that described image element circuit is included using top gate structure is brilliant
Body pipe；
Wherein, described first film transistor and the polysilicon layer of described second thin film transistor (TFT) are same layer, and described grid
Drive circuit is electrically connected with described image element circuit.
2. display floater as claimed in claim 1 is it is characterised in that described gate driver circuit is also included positioned at described substrate
On the first metal layer.
3. display floater as claimed in claim 2 is it is characterised in that described polysilicon layer is located on described the first metal layer simultaneously
Partly overlap with described the first metal layer, overlapping the first metal layer as first film transistor grid.
4. display floater as claimed in claim 2 is it is characterised in that described image element circuit is also included positioned at described polysilicon layer
On second metal layer, described second metal layer is overlapping with described Polysilicon layer portions, in the second metal layer conduct of overlapping
The grid of the second thin film transistor (TFT).
5. display floater as claimed in claim 4 is it is characterised in that also include a connecting path, by described connecting path
Connect described the first metal layer and described second metal layer.
6. display floater as claimed in claim 5 is it is characterised in that described connecting path includes connector and the 3rd metal level,
Described 3rd metal level is electrically connected with described the first metal layer and second metal layer by described connector.
7. a kind of manufacture method of display floater, including：
Substrate is provided；
Form gate driver circuit on the substrate, the first film that described gate driver circuit is included using bottom grating structure is brilliant
Body pipe；
Image element circuit is formed on described gate driver circuit, the second thin film that described image element circuit is included using top gate structure is brilliant
Body pipe, described first film transistor is same layer with the polysilicon layer of described second thin film transistor (TFT)；And
Connect described gate driver circuit and described image element circuit.
8. the manufacture method of display floater as claimed in claim 7 is it is characterised in that form raster data model on the substrate
The step of circuit includes：
Form the first metal layer on the substrate；
Described polysilicon layer is formed on described the first metal layer, described polysilicon layer is partly overlapped with described the first metal layer,
Overlapping the first metal layer as first film transistor grid.
9. the manufacture method of display floater as claimed in claim 8 is it is characterised in that form on described gate driver circuit
The step of image element circuit includes：
Second metal layer is formed on described polysilicon layer, described polysilicon layer is partly overlapped with described second metal layer, in weight
The second metal layer at folded place is as the grid of the second thin film transistor (TFT).
10. display floater as claimed in claim 8 manufacture method it is characterised in that connect described gate driver circuit with
The step of described image element circuit includes：
Form connector, described connector includes one end and connects a part for the first metal layer and the another of one end connection second metal layer
Part；And
Form the 3rd metal level, described 3rd metal level is connected with the other end of described connector.
Priority Applications (1)
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| CN201610901303.XA CN106449706B (en) | 2016-10-17 | 2016-10-17 | Display panel and its manufacturing method |
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|---|---|---|---|
| CN201610901303.XA CN106449706B (en) | 2016-10-17 | 2016-10-17 | Display panel and its manufacturing method |
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| CN106449706A true CN106449706A (en) | 2017-02-22 |
| CN106449706B CN106449706B (en) | 2019-05-03 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111341279A (en) * | 2018-12-19 | 2020-06-26 | 乐金显示有限公司 | Display panel and display device |
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