CN104730781A - ADS array substrate, manufacturing method thereof, and display device comprising same - Google Patents
ADS array substrate, manufacturing method thereof, and display device comprising same Download PDFInfo
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- CN104730781A CN104730781A CN201510142393.4A CN201510142393A CN104730781A CN 104730781 A CN104730781 A CN 104730781A CN 201510142393 A CN201510142393 A CN 201510142393A CN 104730781 A CN104730781 A CN 104730781A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/13629—Multilayer wirings
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
- G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
- G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
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- Optics & Photonics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention relate to the technical field of liquid crystal display, and discloses an ADS array substrate, a manufacturing method thereof and a display device comprising the same. The ADS array substrate comprises a pixel electrode and a common electrode. A metal line is arranged between at least two adjacent sub pixel areas, and the metal line is connected with the common electrode in parallel, so that the resistance of the common electrode is reduced, the coupling capacitance of the common electrode can be reduced, the problems of level drifting and signal distortion of the common electrode are solved, and the phenomenon of picture yellow discolouration is greatly reduced. The display device comprises the ADS array substrate. The display quality of the pictures is improved.
Description
Technical field
The present invention relates to technical field of liquid crystal display, particularly relate to a kind of ADS array base palte and preparation method thereof, display device.
Background technology
Thin Film Transistor-LCD (Thin Film Transistor-Liquid Crystal Display, be called for short TFT-LCD) feature such as to have volume little, low in energy consumption, radiationless, developed rapidly in recent years, dominate in current flat panel display market.The agent structure of TFT-LCD is liquid crystal panel, and liquid crystal panel comprises thin-film transistor array base-plate to box and color membrane substrates, and liquid crystal molecule is filled between array base palte and color membrane substrates.Liquid crystal panel forms the electric field driving liquid crystal deflecting element by control public electrode and pixel electrode, realize GTG display.Filter layer on color membrane substrates is for realizing colored display.
At present, TFT-LCD can be divided into according to display mode: twisted-nematic (TN, Twisted Nematic) type, plane conversion (IPS, In Plane Switching) type and senior super dimension field switch (ADS, AdvancedSuper Dimension Switch) type.Wherein, the electric field that the electric field that ADS type TFT-LCD is mainly produced by gap electrode edge in same plane and gap electrode layer and plate electrode interlayer produce forms multi-dimensional electric field, make in liquid crystal cell that between gap electrode, directly over electrode, all aligned liquid-crystal molecules can both produce rotation, thus improve liquid crystal work efficiency and increase light transmission efficiency.ADS technology can improve the picture quality of TFT-LCD product, have high resolving power, high permeability, low-power consumption, wide viewing angle, high aperture, low aberration, without advantages such as water of compaction ripples (push Mura).
Because the public electrode of ADS type TFT-LCD and pixel electrode are all formed on array base palte, public electrode is coupled seriously with the signal wire (especially data line) on array base palte, cause common electrode signal serious distortion, cause the general green phenomenon of picture, have impact on picture quality.
Summary of the invention
The invention provides a kind of ADS array base palte and preparation method thereof, in order to solve due to common electrode signal serious distortion, cause the general green problem of picture.
The present invention also provides a kind of display device, comprises above-mentioned ADS array base palte, overcomes the general green problem of picture that common electrode signal serious distortion causes, improves picture quality.
For solving the problems of the technologies described above, providing a kind of ADS array base palte in the embodiment of the present invention, comprising public electrode and multiple subpixel area, wherein, be provided with metal wire between two adjacent at least partly subpixel area, described metal wire is in parallel with public electrode.
ADS array base palte as above, preferably, described metal wire comprises:
The first metal wire that arrange between two adjacent at least partly row subpixel area, that extend in the row direction, and/or,
The second metal wire that arrange between two adjacent at least partly row subpixel area, that extend along column direction.
ADS array base palte as above, preferably, also comprises:
Many grid line groups of cross-distribution and a plurality of data lines, limit multiple pixel region, each pixel region comprises two adjacent in the row direction described subpixel area, and each subpixel area comprises pixel electrode and thin film transistor (TFT), and every bar grid line group comprises two grid lines;
With in a line subpixel area, the thin film transistor (TFT) of the subpixel area of odd column is connected to same grid line, and the thin film transistor (TFT) of the subpixel area of even column is connected to another grid line;
In adjacent two row pixel regions, the thin film transistor (TFT) of two adjacent row subpixel area is connected to same data line;
Described second metal wire is arranged between two row subpixel area in every row pixel region, insulate between described second metal wire and grid line group.
ADS array base palte as above, preferably, described second metal wire comprises source and drain metal level in parallel and grid metal level.
ADS array base palte as above, preferably, on the bearing of trend of described second metal wire, the position of the corresponding grid line group of grid metal level of described second metal wire disconnects, and makes to insulate between described second metal wire and grid line group.
ADS array base palte as above, preferably, described first metal wire is arranged between two grid lines in every bar grid line group, insulate between described first metal wire and grid line group, data line.
ADS array base palte as above, preferably, the material of described first metal wire is source and drain metal, arranges with described grid line group different layers, makes to insulate between described first metal wire and grid line group.
ADS array base palte as above, preferably, on the bearing of trend of described first metal wire, the position of described first metal wire respective data lines disconnects, and makes to insulate between described first metal wire and data line.
A kind of method for making of ADS array base palte as above is also provided in the embodiment of the present invention, comprises the step forming public electrode and the step forming multiple subpixel area, also comprise:
Between two adjacent at least partly subpixel area, form the step of metal wire, described metal wire is in parallel with public electrode.
Method for making as above, preferably, the step forming metal wire comprises:
The first metal wire extended in the row direction is formed between two adjacent at least partly row subpixel area, and/or,
The second metal wire extended along column direction is formed between two adjacent at least partly row subpixel area.
Method for making as above, preferably, described method for making specifically comprises:
Form grid metallic film, carry out patterning processes to described grid metallic film, form the grid metal level of many grid line groups and described second metal wire, every bar grid line group comprises two grid lines;
Form source and drain metallic film, patterning processes is carried out to described source and drain metallic film, the source and drain metal level of formation a plurality of data lines, described second metal wire and described first metal wire, described many grid line groups and a plurality of data lines limit multiple pixel region, and each pixel region comprises two adjacent in the row direction described subpixel area;
Form pixel electrode and thin film transistor (TFT) in each described subpixel area, with in a line subpixel area, the thin film transistor (TFT) of the subpixel area of odd column is connected to same grid line, and the thin film transistor (TFT) of the subpixel area of even column is connected to another grid line; In adjacent two row pixel regions, the thin film transistor (TFT) of two adjacent row subpixel area is connected to same data line;
Specifically between two row subpixel area in every row pixel region, form described second metal wire, on the bearing of trend of described second metal wire, the position of the corresponding described grid line group of grid metal level of described second metal level disconnects, and makes to insulate between described second metal wire and grid line group;
Specifically between two grid lines of described grid line group, form described first metal wire, on the bearing of trend of described first metal wire, the position of described first metal wire respective data lines disconnects, and makes to insulate between described first metal wire and data line.
Also provide a kind of display device in the embodiment of the present invention, comprise ADS array base palte as above.
The beneficial effect of technique scheme of the present invention is as follows:
In technique scheme, ADS array base palte comprises pixel electrode and public electrode, by arranging metal wire between two adjacent at least partly subpixel area, and by parallel with public electrode for described metal wire, to reduce the resistance of public electrode, thus the coupling capacitance of public electrode can be reduced, improve level-shift and the distorted signals problem of public electrode, substantially improve the general green phenomenon of picture, improve the picture display quality of display device.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1-Fig. 4 represents the manufacturing process schematic diagram of ADS array base palte in the embodiment of the present invention.
Embodiment
The invention provides a kind of ADS array base palte and preparation method thereof, cause level-shift and signal serious distortion in order to solve public electrode due to coupling capacitance, cause the general green problem of picture.
Described ADS array base palte comprises public electrode and multiple subpixel area, metal wire is provided with between two adjacent at least partly subpixel area, and by parallel with public electrode for described metal wire, to reduce the resistance of public electrode, thus the coupling capacitance of public electrode can be reduced, improve level-shift and the distorted signals problem of public electrode, substantially improve the general green phenomenon of picture, improve the picture display quality of display device.
Wherein, described subpixel area is defined by grid line and data line, and described coupling capacitance is primarily of public electrode and the overlapping generation of data line.
Specific works principle of the present invention is:
Cause the general green principal element of ADS type TFT-LCD picture to have two: one to be the level-shift of public electrode, another is the distortion attenuation of common electrode signal.The factor affecting level-shift can be expressed as: C × V × r, and wherein, C is the coupling capacitance of public electrode and data line, and V is the variable quantity of voltage on data line, and r is the resolution of display device.The factor affecting distortion attenuation can be expressed as R × C, and R is the resistance of public electrode, and C is the coupling capacitance of public electrode and data line.Known accordingly, the coupling capacitance of public electrode and data line can cause level-shift and the distorted signals of public electrode.
The present invention is exactly the resistance by reducing public electrode, reduces the coupling capacitance of public electrode, improves level-shift and the distorted signals of public electrode, thus greatly improve the general green phenomenon of picture, improves picture display quality.
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples for illustration of the present invention, but are not used for limiting the scope of the invention.
Shown in composition graphs 4, ADS array base palte in the embodiment of the present invention comprises public electrode 5 and multiple subpixel area, and each subpixel area comprises pixel electrode 4, and public electrode 5 is for coordinating with pixel electrode 4, form the electric field driving liquid crystal deflecting element, realize the display of specific grey-scale.Meanwhile, public electrode 5, also for providing reference voltage for array base palte, specifically can arrange the whole viewing area that public electrode 5 covers array base palte.
Metal wire is provided with between two adjacent at least partly subpixel area, described metal wire is in parallel with public electrode 5, for reducing the resistance of public electrode 5, thus the coupling capacitance reduced between public electrode 5 and other signal wires (as data line), improve level-shift and the distorted signals problem of public electrode 5, thus greatly improve the general green phenomenon of picture, improve the picture display quality of display device.
Described metal wire specifically can be in parallel with public electrode 5 by the via hole in the insulation course between described metal wire with public electrode 5.
Technique scheme utilizes the resistance value of multiple resistor coupled in parallel to be less than this principle of resistance value of any one resistance, by arranging metal wire between adjacent two subpixel area, and by mode in parallel with public electrode for described metal wire, reduce the resistance of public electrode, thus reduce the coupling capacitance of public electrode, improve level-shift and the distorted signals problem of public electrode, substantially improve the general green phenomenon of the picture caused thus.Because metal wire is arranged between two adjacent subpixel area, also can not impact aperture opening ratio.
In the embodiment of the present invention, the method for making of ADS array base palte comprises the step forming public electrode and the step forming multiple subpixel area, also be included in the step forming metal wire between two adjacent at least partly subpixel area, described metal wire is in parallel with public electrode.
Concrete, described metal wire comprises:
The first metal wire 30 that arrange between two adjacent at least partly row subpixel area, that extend in the row direction, and/or,
The second metal wire 40 that arrange between two adjacent at least partly row subpixel area, that extend along column direction.
Then, the method for making forming metal wire comprises:
The first metal wire 30 extended in the row direction is formed between two adjacent at least partly row subpixel area, and/or,
The second metal wire 40 extended along column direction is formed between two adjacent at least partly row subpixel area.
ADS array base palte in the embodiment of the present invention also comprises grid line and data line, and grid line and data line transverse and longitudinal cross-distribution, for limiting multiple pixel region.
In a concrete embodiment, described ADS array base palte is double grid line style ADS array base palte, comprises many grid line groups 10 and the data line 20 of transverse and longitudinal cross-distribution, for limiting multiple pixel region, as shown in Figure 3.Wherein, grid line group 10 comprises two grid lines, and described two grid lines the first grid line 11 and the second grid line 12 represent, with data line 20 transverse and longitudinal cross-distribution.Each pixel region that grid line group 10 and data line 20 limit comprises two adjacent in the row direction subpixel area, and each subpixel area comprises pixel electrode 4 and thin film transistor (TFT).With in a line subpixel area, the thin film transistor (TFT) of the subpixel area of odd column is connected to same grid line, the thin film transistor (TFT) of the subpixel area of even column is connected to another grid line, thus in adjacent two row pixel regions, the thin film transistor (TFT) of two adjacent row subpixel area can be connected to same data line 20, shares a data line 20.Concrete principle of work is, useful signal is inputted line by line on every bar first grid line 11 and the second grid line 12, to open corresponding thin film transistor (TFT), when the thin film transistor (TFT) of the odd column of certain row is opened, pixel voltage is inputted by column to every column data line 20, pixel voltage transfers to the odd column subpixel area of this row via thin film transistor (TFT), carries out the display of corresponding GTG.And when the thin film transistor (TFT) of the even column of this row is opened, pixel voltage is inputted by column to every column data line 20, pixel voltage transfers to the even column subpixel area of this row via thin film transistor (TFT), carry out the display of corresponding GTG, thus the thin film transistor (TFT) of adjacent two row can share a data line 20.
For the ease of structural realization, with in a line subpixel area, the thin film transistor (TFT) of the subpixel area of odd column is connected to the second grid line 12 in Article 1 grid line group 10, the thin film transistor (TFT) of the subpixel area of even column is connected to the first grid line 11 in Article 2 grid line group 10, wherein, Article 1, grid line group 10 is adjacent with Article 2 grid line group 10, and the second grid line 12 of Article 1 grid line group 10 is adjacent with the first grid line 11 of Article 2 grid line group 10, as shown in Figure 2.
It should be noted that, thin film transistor (TFT) is connected to grid line and refers to: the gate electrode 1 of thin film transistor (TFT) and the first grid line 11 or the second grid line 12 are electrically connected.Thin film transistor (TFT) is connected to data line and refers to: source electrode 2 and the data line 20 of thin film transistor (TFT) are electrically connected.
In this embodiment, described metal wire comprises the second metal wire 40 extended along column direction.
For double grid line style ADS array base palte, the pixel region that grid line group 10 and data line 20 limit comprises two subpixel area adjacent in the row direction, and data line between subpixel area in each pixel region is default.Preferably, the second newly-increased metal wire 40 is arranged on default linear position data, concrete, often in row pixel region, arranges the second metal wire 40 extended along column direction, and insulate between the second metal wire 40 and grid line group 10 between two row subpixel area.Then, described subpixel area is specifically defined by grid line group 10, data line 20 and the second metal wire 40.
Further, the second metal wire 40 is set and comprises source and drain metal level 42 in parallel and grid metal level 41, to reduce the resistance of the second metal wire 40, thus reduce the resistance of the public electrode 5 in parallel with the second metal wire 40 further.In actual fabrication technique, the grid metal level 41 of the second metal wire 40 is formed by same grid metallic film with the gate electrode 1 of grid line group 10 and thin film transistor (TFT), as shown in Figure 1.Source electrode 2, the drain electrode 3 of source and drain metal level 42 and data line 20 and thin film transistor (TFT) are formed by same source and drain metallic film, as shown in Figure 2.
In order to realize the insulation between the second metal wire 40 and grid line group 10, can be arranged on the bearing of trend of the second metal wire 40, the position of the corresponding grid line group 10 of grid metal level 41 of the second metal wire 40 disconnects, as shown in Figure 1.Certainly, the insulation between the second metal wire 40 and grid line group 10 also can be realized by other means, such as: different layers is arranged, and arranges insulation course between the two layers.
In actual application, between two row subpixel area in all row pixel regions, the second metal wire 40 can be set, also between two row subpixel area only in part rows pixel region, the second metal wire 40 can be set.
As one preferred embodiment, the metal wire in parallel with public electrode 5 not only comprises the second metal wire 40 extended along column direction, also comprises the first metal wire 30 extended in the row direction.
Continue to be described for double grid line style ADS array base palte, illustrated before and how on double grid line style ADS array base palte, to have increased the second metal wire 40 extended along column direction newly, do not repeat them here.
For the first metal wire 30 extended in the row direction, it can be arranged between the first grid line 11 in every bar grid line group 10 and the second grid line 12, and the first metal wire 30 and grid line group 10, insulating between data line 20 is arranged.Concrete, the material arranging the first metal wire 30 is source and drain metal, arranges with grid line group 10 different layers, to realize the insulation between the first metal wire 30 and grid line group 10.And on the bearing of trend of the first metal wire 30, the position of the first metal wire 30 respective data lines 20 disconnects, to realize the insulation between the first metal wire 30 and data line 20, as shown in Figure 2.In the manufacture craft of reality, source electrode 2, the drain electrode 3 of the first metal wire 30 and data line 20 and thin film transistor (TFT) are formed by same source and drain metallic film.
In the embodiment of the present invention, the first metal wire 30 extended in the row direction also only can be set, and the second metal wire 40 extended along column direction is not set.For double grid line style ADS array base palte, preferably arrange between first grid line 11 of the first metal wire 30 in grid line group 10 and the second grid line 12, and and the first metal wire 30 and grid line group 10, insulating between data line 20 is arranged.
It should be noted that, when arranging the first metal wire 30 extended in the row direction, first metal wire 30 can be set between the first grid line 11 of all grid line groups 10 and the second grid line 12, also only the first metal wire 30 can be set between first grid line 11 and the second grid line 12 of part grid line group 10.
As shown in Figure 4, in the embodiment of the present invention, ADS array base palte specifically comprises:
Many grid line groups 10 of transverse and longitudinal cross-distribution and a plurality of data lines 20, for limiting multiple pixel region, each pixel region comprises two adjacent in the row direction subpixel area, and every bar grid line group 10 is made up of the first grid line 11 and the second grid line 12 two grid lines;
Each subpixel area comprises thin film transistor (TFT) and tabular pixel electrode 4, with in a line subpixel area, the gate electrode 1 of the thin film transistor (TFT) of odd column subpixel area is the integrative-structure that same layer is arranged with material with the second grid line 12 of Article 1 grid line group 10, the gate electrode 1 of the thin film transistor (TFT) of odd column subpixel area is the integrative-structure that same layer is arranged with material with the first grid line 11 of Article 2 grid line group 10, Article 1, grid line group 10 is adjacent with Article 2 grid line group 10, and the second grid line 12 of Article 1 grid line group 10 is adjacent with the first grid line 11 of Article 2 grid line group 10.Thus in adjacent two row pixel regions, source electrode 2 and the same data line 20 of the thin film transistor (TFT) of two adjacent row subpixel area are the integrative-structure that same layer is arranged with material, share a data line 20.Pixel electrode 4 is overlapped on the drain electrode 3 of thin film transistor (TFT);
Often in row pixel region, the second metal wire 40 is provided with between two row subpixel area, second metal wire 40 comprises grid metal level 41 in parallel and source and drain metal level 42, on the bearing of trend of the second metal wire 40, the position of the corresponding grid line group 10 of grid metal level 41 of the second metal wire 40 disconnects, as shown in Figure 1, make to insulate between the second metal wire 40 and grid line group 10;
The first grid line 11 in every bar grid line group 10 and to be provided with the first metal wire 30, first metal wire 30 between the second grid line 12 be source and drain metal, arranges with grid line group 10 different layers, makes to insulate between the first metal wire 30 and grid line group 10.On the bearing of trend of the first metal wire 30, the position of the first metal wire 30 respective data lines 20 disconnects, and as shown in Figure 3, makes to insulate between the first metal wire 30 and data line 20;
Slit public electrode 5, in parallel with the first metal wire 30 and the second metal wire 40 by insulation course via hole.
Wherein, pixel electrode 4 and public electrode 5 are transparent conductive material.Insulation course is provided with between adjacent conductive Thinfilm pattern (as: grid metal thin film patterns and source and drain metal thin film patterns, source and drain metal thin film patterns and transparent conductive film pattern), not shown.First metal wire 30 and the source and drain metal level 42 of data line 20, second metal wire 40, the source electrode 2 of thin film transistor (TFT) and drain electrode 3 are for arrange with material with layer.The grid metal level 41 of the second metal wire 40 and the gate electrode 1 of grid line group 10, thin film transistor (TFT) are for arrange with material with layer.
Shown in composition graphs 1-Fig. 4, in the embodiment of the present invention, the method for making of ADS array base palte specifically comprises:
Form grid metallic film, patterning processes is carried out to described grid metallic film, forms the grid metal level 41 of many grid line groups 10, second metal wire, the pipe gate electrode 1 of film crystal, as shown in Figure 1;
Grid metal thin film patterns forms gate insulation layer, not shown;
Gate insulation layer is formed the active layer pattern of thin film transistor (TFT), and not shown, the material of active layer pattern is silicon semiconductor or metal-oxide semiconductor (MOS);
Active layer pattern is formed source and drain metallic film, patterning processes is carried out to described source and drain metallic film, form source and drain metal level 42, first metal wire 30 of a plurality of data lines 20, second metal wire, the source electrode 2 of thin film transistor (TFT) and drain electrode 3, as shown in Figure 2, many grid line groups 10 and a plurality of data lines 20 limit multiple pixel region, each pixel region comprises two adjacent in the row direction subpixel area, thin film transistor (TFT) is positioned at described subpixel area, and described subpixel area is limited by grid line group 10, data line 20 and the second metal wire 40.In adjacent two row pixel regions, the thin film transistor (TFT) of two adjacent row subpixel area is connected to same data line 20.With in a line subpixel area, the thin film transistor (TFT) of the subpixel area of odd column is connected to the second grid line 12 of Article 1 grid line group 10, the thin film transistor (TFT) of the subpixel area of even column is connected to the Article 1 grid line 11 of Article 2 grid line group 10, and Article 1 grid line group 10 is adjacent with Article 2 grid line group 10.Second metal wire 40 comprises grid metal level 41 in parallel and source and drain metal level 42, between two row subpixel area in every row pixel region, on the bearing of trend of the second metal wire 40, the position of the corresponding grid line group 10 of grid metal level 41 of the second metal level 40 disconnects, and makes to insulate between the second metal wire 40 and grid line group 10.First metal wire 30 is between first grid line 11 and the second grid line 12 of grid line group 10, first metal wire 30 is source and drain metal, arrange with grid line group 10 different layers, make to insulate between the first metal wire 30 and grid line group 10, on the bearing of trend of the first metal wire 30, the position of the first metal wire 30 respective data lines 20 disconnects, and makes to insulate between the first metal wire 30 and data line 20;
Form tabular pixel electrode 4 in each subpixel area, pixel electrode 4 is overlapped on thin film transistor (TFT) drain electrode 3, as shown in Figure 3;
Pixel electrode 4 forms passivation layer, not shown;
Form slit public electrode 5 over the passivation layer, as shown in Figure 4, public electrode 5 is in parallel with the first metal wire 30 by the via hole in passivation layer, in parallel with the second metal wire 40 by the via hole run through in passivation layer and gate insulation layer.
For double grid line style ADS array base palte in the embodiment of the present invention, specifically introduce technical scheme of the present invention, but technical scheme of the present invention is also applicable to single grid line type ADS array base palte, or the ADS array base palte of other types.
Also provide a kind of display device in the embodiment of the present invention, comprise the ADS array base palte in the embodiment of the present invention, in order to improve the display quality of picture.
Described display device is liquid crystal indicator, Ke Yiwei: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, mobile phone, panel computer, televisor, display, notebook computer, digital album (digital photo frame), navigating instrument.
In technical scheme of the present invention, ADS array base palte comprises pixel electrode and public electrode, by arranging metal wire between two adjacent at least partly subpixel area, and by parallel with public electrode for described metal wire, to reduce the resistance of public electrode, thus the coupling capacitance of public electrode can be reduced, improve level-shift and the distorted signals problem of public electrode, substantially improve the general green phenomenon of picture, improve the picture display quality of display device.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite not departing from the technology of the present invention principle; can also make some improvement and replacement, these improve and replace and also should be considered as protection scope of the present invention.
Claims (12)
1. an ADS array base palte, comprises public electrode and multiple subpixel area, it is characterized in that, be provided with metal wire between two adjacent at least partly subpixel area, described metal wire is in parallel with public electrode.
2. ADS array base palte according to claim 1, is characterized in that, described metal wire comprises:
The first metal wire that arrange between two adjacent at least partly row subpixel area, that extend in the row direction, and/or,
The second metal wire that arrange between two adjacent at least partly row subpixel area, that extend along column direction.
3. ADS array base palte according to claim 2, is characterized in that, also comprise:
Many grid line groups of cross-distribution and a plurality of data lines, limit multiple pixel region, each pixel region comprises two adjacent in the row direction described subpixel area, and each subpixel area comprises pixel electrode and thin film transistor (TFT), and every bar grid line group comprises two grid lines;
With in a line subpixel area, the thin film transistor (TFT) of the subpixel area of odd column is connected to same grid line, and the thin film transistor (TFT) of the subpixel area of even column is connected to another grid line;
In adjacent two row pixel regions, the thin film transistor (TFT) of two adjacent row subpixel area is connected to same data line;
Described second metal wire is arranged between two row subpixel area in every row pixel region, insulate between described second metal wire and grid line group.
4. ADS array base palte according to claim 3, is characterized in that, described second metal wire comprises source and drain metal level in parallel and grid metal level.
5. ADS array base palte according to claim 4, is characterized in that, on the bearing of trend of described second metal wire, the position of the corresponding grid line group of grid metal level of described second metal wire disconnects, and makes to insulate between described second metal wire and grid line group.
6. ADS array base palte according to claim 3, is characterized in that, described first metal wire is arranged between two grid lines in every bar grid line group, insulate between described first metal wire and grid line group, data line.
7. ADS array base palte according to claim 6, is characterized in that, the material of described first metal wire is source and drain metal, arranges with described grid line group different layers, makes to insulate between described first metal wire and grid line group.
8. ADS array base palte according to claim 7, is characterized in that, on the bearing of trend of described first metal wire, the position of described first metal wire respective data lines disconnects, and makes to insulate between described first metal wire and data line.
9. a method for making for the ADS array base palte described in any one of claim 1-8, comprises the step forming public electrode and the step forming multiple subpixel area, it is characterized in that, also comprise:
Between two adjacent at least partly subpixel area, form the step of metal wire, described metal wire is in parallel with public electrode.
10. method for making according to claim 9, is characterized in that, the step forming metal wire comprises:
The first metal wire extended in the row direction is formed between two adjacent at least partly row subpixel area, and/or,
The second metal wire extended along column direction is formed between two adjacent at least partly row subpixel area.
11. method for makings according to claim 10, is characterized in that, described method for making specifically comprises:
Form grid metallic film, carry out patterning processes to described grid metallic film, form the grid metal level of many grid line groups and described second metal wire, every bar grid line group comprises two grid lines;
Form source and drain metallic film, patterning processes is carried out to described source and drain metallic film, the source and drain metal level of formation a plurality of data lines, described second metal wire and described first metal wire, described many grid line groups and a plurality of data lines limit multiple pixel region, and each pixel region comprises two adjacent in the row direction described subpixel area;
Form pixel electrode and thin film transistor (TFT) in each described subpixel area, with in a line subpixel area, the thin film transistor (TFT) of the subpixel area of odd column is connected to same grid line, and the thin film transistor (TFT) of the subpixel area of even column is connected to another grid line; In adjacent two row pixel regions, the thin film transistor (TFT) of two adjacent row subpixel area is connected to same data line;
Specifically between two row subpixel area in every row pixel region, form described second metal wire, on the bearing of trend of described second metal wire, the position of the corresponding described grid line group of grid metal level of described second metal level disconnects, and makes to insulate between described second metal wire and grid line group;
Specifically between two grid lines of described grid line group, form described first metal wire, on the bearing of trend of described first metal wire, the position of described first metal wire respective data lines disconnects, and makes to insulate between described first metal wire and data line.
12. 1 kinds of display device, is characterized in that, comprise the ADS array base palte described in any one of claim 1-8.
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| CN201510142393.4A CN104730781A (en) | 2015-03-27 | 2015-03-27 | ADS array substrate, manufacturing method thereof, and display device comprising same |
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Application publication date: 20150624 |