CN104049430A - Array substrate, display device and manufacturing method of array substrate - Google Patents

Array substrate, display device and manufacturing method of array substrate Download PDF

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Publication number
CN104049430A
CN104049430A CN201410274667.0A CN201410274667A CN104049430A CN 104049430 A CN104049430 A CN 104049430A CN 201410274667 A CN201410274667 A CN 201410274667A CN 104049430 A CN104049430 A CN 104049430A
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electrode
pixel
public electrode
base palte
array base
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CN201410274667.0A
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Chinese (zh)
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CN104049430B (en
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王海宏
马群刚
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南京中电熊猫液晶显示科技有限公司
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Abstract

The invention discloses an array substrate, a display device and a manufacturing method of the array substrate. According to the array substrate, the display device and the manufacturing method of the array substrate, the array substrate is provided with pixel regions defined by first common electrode wires and second common electrode wires; scanning lines and data lines are arranged on central lines of the pixel regions, and active elements are formed in intersection regions of the scanning lines and the data lines; pixel electrodes are connected to storage electrodes and common electrodes of a first metal layer through contact holes to form storage capacitors; after the pixel electrodes are formed, a black organic insulating layer is formed on the array substrate; through the halftone mask plate photoetching process or the gray tone mask plate photoetching process, a first height pattern and a second height pattern are formed, wherein the first height pattern is a supporting post, and the second height pattern is a black matrix. The display device further comprises a color filter substrate and a display medium clamped between the array substrate and the color filter substrate. Through the manufacturing method, one manufacturing process can be omitted, the process cost is lowered, and the percentage of pass of products is increased.

Description

A kind of array base palte, display device and manufacture method thereof

Technical field

The present invention relates to display technique field, especially relate to a kind of array base palte, display device and manufacture method thereof.

Background technology

As shown in Figure 1, Thin Film Transistor-LCD (TFT-LCD) is jointly to be formed by array base palte 11, colored filter substrate 13 and the liquid crystal 13 that riddles between these two substrates, backlight 14, from array base palte 11 1 side incidents, posts respectively array side Polarizer 115 and colored filter lateral deviation tabula rasa 124 on array base palte 11 and colored filter substrate.On array base palte 11, generally comprise 5-6 the film-forming process such as gate metal layer 111, gate insulator, semiconductor layer 112, source leakage metal level 113, source source/drain insulation layer, organic insulator, pixel electrode layer 114; Colored filter side comprises black-matrix layer 121, color blocking layer 122 (green color blocking layer, red color resistance layer, blue color blocking layer), common electrode layer 123, general 6 film-forming process of support column layer (hereinafter referred to as PS).

Many one-time process engineering, will increase the probability of the defective generation of panel.In addition, after film forming completes, the Anawgy accuracy of colored filter substrate and array base palte also can affect the qualification rate of product, and the bad meeting of fitting causes product light leak.

Summary of the invention

Share by effective merging production process and material, can reduce bad reducing costs.Part rete on color membrane substrates and array base palte is shared, can reduce membrane formation times, save material, reduce costs.

One embodiment of the invention provides a kind of array base palte, it comprises: a substrate, disposes the first metal layer, metal dielectric layer, semiconductor layer, the second metal level, protection insulation course, transparent organic insulating film, pixel electrode layer, black organic insulator successively on it; Wherein, the first metal layer, it comprises: multi-strip scanning line, described in each, sweep trace is arranged on the horizontal central line of each this pixel region, and with many data line settings intersected with each other; Multiple storage electrodes, be disposed at pixel electrode below, and overlapping with the view field of the first public electrode and the second public electrode, and this storage electrode is by the second contact hole and the electric connection of this pixel electrode; The second metal level, it comprises: many first public electrode wires, have the discontinuous distributing line that is uniformly distributed gap; Many the second public electrode wires, surround pixel region array with these many first public electrode wire cross connections; Many data lines, described in each, data line is arranged on the median vertical line of each this pixel region, and through this gap to should the first public electrode wire; Active member, is arranged at each this data line and each this sweep trace intersection region; Multiple pixel electrodes, each this pixel electrode is electrically connected by the first contact hole and this active member; Black organic insulator, forms the first elevational pattern and the second elevational pattern, and wherein, the first elevational pattern is support column, and the second elevational pattern is black matrix".

Preferably, this first elevational pattern and this second elevational pattern form by intermediate tone mask version or the exposure of gray tone mask plate.

Preferably, this black matrix" covers this sweep trace, this storage electrode, this data line, this first and second public electrode wire, this active member; This support column is evenly arranged in this sweep trace and data line intersection region and/or this first and second public power polar curve intersection region.

The present invention also provides a kind of display device, and it comprises the array base palte described in above-described embodiment, also comprises a counter substrate, and this substrate is the glass substrate that is coated with ITO; Between this array base palte and this counter substrate, be folded with display dielectric layer.

The present invention also provide a kind of as comprise as described in above-described embodiment as described in the manufacture method of array base palte, it comprises the following steps:

A. on this substrate, form the first metal layer, it comprises sweep trace and pixel storage electrode;

B. form semiconductor figure, semiconductor material is amorphous silicon, polysilicon or metal oxide;

C. form source, drain electrode, data line, first and second public electrode wire;

D. form protection insulation course, transparent organic insulating film;

E. form contact hole;

F. form pixel electrode;

G. form black organic insulator, by intermediate tone mask version or gray tone mask plate, form the first elevational pattern and the second elevational pattern, wherein, the first elevational pattern is support column, and the second elevational pattern is black matrix".

Preferably, this protection insulation course is SiO2, SiNx or Al2O3, and the thickness of this protection insulation course is 1000A-4000A, and the thickness of this organic insulator is at 1um-3um.

The present invention compared with prior art, its advantage is: by black organic insulation is set, form black matrix" and support column simultaneously, can effectively reduce the technological process of liquid crystal panel, the qualification rate that improves product, because black matrix" is positioned on array base palte, colored filter substrate and array base palte do not have aligning accuracy requirement in addition, therefore, the qualification rate of product also can be further improved.

Brief description of the drawings

Fig. 1 is the diagrammatic cross-section of display device in prior art

Fig. 2 is the structural representation of display device of the present invention;

Fig. 3 is the dot structure schematic diagram on array base palte in Fig. 2 of the present invention;

Fig. 4 (a) is the planimetric map of the first metal layer pattern of dot structure in Fig. 3 of the present invention;

Fig. 4 (b) is the sectional view of the first metal layer pattern AA ' direction of dot structure in Fig. 3 of the present invention;

Fig. 5 (a) is the planimetric map of the semiconductor layer pattern of dot structure in Fig. 3 of the present invention;

Fig. 5 (b) is the sectional view of the semiconductor layer pattern AA ' direction of dot structure in Fig. 3 of the present invention;

Fig. 6 (a) is the planimetric map of the second metal layer pattern of dot structure in Fig. 3 of the present invention;

Fig. 6 (b) is the sectional view of second metal layer pattern AA ' direction of dot structure in Fig. 3 of the present invention;

Fig. 7 (a) is the planimetric map of the contact hole pattern of dot structure in Fig. 3 of the present invention;

Fig. 7 (b) is the sectional view of the contact hole pattern AA ' direction of dot structure in Fig. 3 of the present invention;

Fig. 8 (a) is the planimetric map of the pixel electrode pattern of dot structure in Fig. 3 of the present invention;

Fig. 8 (b) is the sectional view of the pixel electrode pattern AA ' direction of dot structure in Fig. 3 of the present invention;

Fig. 9 (a) is the planimetric map of the black organic insulation layer pattern of dot structure in Fig. 3 of the present invention;

Fig. 9 (b) is the sectional view of the black organic insulation layer pattern AA ' direction of dot structure in Fig. 3 of the present invention;

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.

Fig. 2 is the structural representation of display device of the present invention.As shown in Figure 2, the invention provides a kind of display device, it comprises: array basal plate 21, pattern, protection insulation course 215, transparent organic insulating film 216, contact hole 217, pixel electrode 218, the black organic insulator 219 of the first metal layer that the sweep trace 211 that distributes successively on this array base palte 21, storage electrode form, gate insulator 212, semiconductor layer 213, the second metal level of being formed by first and second public electrode wire, source-drain electrode, data line 214; Also comprise a counter substrate 22, as colored filter substrate, transparent ito surface electrode 221 distributes on it.In black organic insulator, form the first elevational pattern and the second elevational pattern, wherein, the first elevational pattern is support column, the second elevational pattern is black matrix".

Fig. 3 is the dot structure schematic diagram on array base palte in Fig. 2 of the present invention.As shown in Figure 3, the present invention also provides array basal plate, it comprises: a substrate (not shown), disposes the first metal layer, metal dielectric layer, semiconductor layer, the second metal level, protection insulation course, transparent organic insulating film, pixel electrode layer, black organic insulator successively on it; Wherein, the first metal layer, it comprises: multi-strip scanning line 31, described in each, sweep trace is arranged on the horizontal central line of each this pixel region, and with many data line settings intersected with each other; Multiple storage electrodes 32, be disposed at pixel electrode below, and overlap to form storage electrode with the view field of the first public electrode and the second public electrode, and this storage electrode 32 is by the second contact hole and the electric connection of this pixel electrode; The second metal level, it comprises: many first public electrode wires 35, have the discontinuous distributing line that is uniformly distributed gap; Many the second public electrode wires 35, surround pixel region array with these many first public electrode wire cross connections; Many data lines 34, described in each, data line is arranged on the median vertical line of each this pixel region, and through this gap to should the first public electrode wire; Active member, it comprises and comprises semiconductor layer 33, source electrode 34, drain electrode 36, and is arranged at each this data line 34 and each these sweep trace 31 intersection region; Multiple pixel electrodes 38, each this pixel electrode 38 is electrically connected by the first contact hole 37 and this active member; Black organic insulator, forms the first elevational pattern and the second elevational pattern, and wherein, the first elevational pattern is that support column 30, the second elevational pattern are black matrix" 39.

As an embodiment, dot structure that this embodiment provides and preparation method thereof is only with the difference of above-described embodiment: below this pixel electrode, and the view field of this first area of this storage electrode and this first public electrode wire and this second public electrode wire formation memory capacitance that partly overlaps.

As a preferred embodiment, dot structure that this embodiment provides and preparation method thereof is only with the difference of above-described embodiment: below this pixel electrode, the view field of this first area of this storage electrode and this first public electrode and this second public electrode overlaps to form memory capacitance completely.

The present invention is surrounded and is formed by the public electrode wire of four border configuration shadings in pixel, can significantly improve the aperture opening ratio of pixel.The memory capacitance that storage electrode and public electrode wire overlap to form can be in the time there is skew in upper lower metal layer the size of auto-compensation memory capacitance.

Wherein, this first elevational pattern and this second elevational pattern form by intermediate tone mask version or the exposure of gray tone mask plate.

Wherein, this black matrix" covers this sweep trace, this storage electrode, this data line, this first and second public electrode wire, this active member; This support column is evenly arranged in this sweep trace and data line intersection region and/or this first and second public power polar curve intersection region.

In the prior art, black-matrix layer on colored filter substrate and PS layer need to adopt two mask plate twice manufacturing process to form, and adopt array base palte of the present invention, by being set, black organic insulation layer pattern forms black-matrix layer and support column layer simultaneously, therefore, can reduce a mask plate with together with technique, thereby save process costs.In addition, black organic insulator of the present invention is except playing the interception of black matrix", and also as organic insulator, the electricity between isolated pixel electrode and metal wire is disturbed.

The method for making that the invention provides array base palte described in above-described embodiment, it comprises following making step:

Step a, on array base palte 40, sputter forms the first metal layer, and the first metal layer can be metal or the alloys such as Ti, Al, Cu, Mo, and the thickness of the first metal layer is utilize first mask plate, the technique such as coating by photoresist, exposure, development, etching forms the pattern as shown in Fig. 4 (a).In Fig. 4 (a), middle pattern is sweep trace 41, and the pattern in the lower left corner and the upper right corner is storage electrode 42.The cross-section structure of corresponding diagram 4 (a) dotted line AA ' is as shown in Fig. 4 (b).

Step b, on the pattern of the first metal layer, forms transparent gate insulator 50 by chemical vapor deposition method.Deposited semiconductor film above gate insulator 50, semiconductor material can be amorphous silicon, polysilicon or oxide semiconductor etc., thickness is extremely utilize second mask plate, the technique such as coating by photoresist, exposure, development, etching forms the pattern as shown in Fig. 5 (a).In Fig. 5 (a), the pattern of sweep trace top is semiconductor channel layer 51.The cross-section structure of corresponding diagram 5 (a) dotted line AA ' is as shown in Fig. 5 (b).

Step c, on the pattern of semiconductor layer, sputter forms second layer metal film.The second metal level can be metal or the alloys such as Ti, Al, Cu, Mo, and the thickness that metal level is leaked in source is utilize the 3rd mask plate, the technique such as coating by photoresist, exposure, development, etching forms the pattern as shown in Fig. 6 (a).In Fig. 6 (a), the middle pattern running through is up and down data line 61, and the pattern that left and right is run through is up and down public electrode wire main line 63, and what on public electrode wire main line, extended left and right is the subordinate line 64 of public electrode wire.In the overlapping region of data line 61 and sweep trace, above semiconductor layer, form TFT switch.The grid of TFT switch is sweep trace, and the source electrode of TFT switch is data line 61, the drain electrode 62 of TFT switch and the same layer of data line 61.If metal wire upper strata is Al, need to be U-shaped by contact hole place metal designs.The cross-section structure of corresponding diagram 6 (a) dotted line AA ' is as shown in Fig. 6 (b).

Steps d, on the pattern of the second metal level, forms transparent protection insulation course 70 by chemical vapor deposition method.Protection insulation course can be SiO2, SiNx or Al2O3 etc., and the thickness of protection insulation course is above protection insulation course 70, be coated with the organic insulating film 71 of layer of transparent.The thickness of organic insulating film 71 is 2um.Utilize the 4th mask plate, the technique such as coating by photoresist, exposure, development, etching forms the pattern as shown in Fig. 7 (a).In Fig. 7 (a), the contact hole 72 of drain electrode top, TFT switch left and right is for connecting pixel electrode; The contact hole 73 of upper and lower storage electrode top is for connecting pixel electrode.Be connected with pixel electrode with contact hole 73 by contact hole 72, the drain signal of TFT switch passes to pixel electrode and storage electrode simultaneously simultaneously.The cross-section structure of corresponding diagram 7 (a) dotted line AA ' is as shown in Fig. 7 (b).

Step e, above organic film and contact hole, sputter forms ITO transparent conductive film.The thickness of ito thin film is extremely utilize the 5th mask plate, the technique such as coating by photoresist, exposure, development, etching forms the pattern as shown in Fig. 8 (a).In Fig. 8 (a), ITO transparent conductive film covers the top in pixel openings district, forms pixel electrode 81 regions, has the overlapping region of 2um at the surrounding of pixel electrode 81 and public electrode wire.The cross-section structure of corresponding diagram 8 (a) dotted line AA ' is as shown in Fig. 8 (b).

Step f is coated with the organic insulating film of one deck black above pixel electrode.The thickness of the organic insulating film of black is 0.5~2um.Utilize the 6th mask plate, form the pattern as shown in Fig. 9 (a) by techniques such as exposure, developments.The 4th mask plate is intermediate tone mask version or gray tone mask plate, uses the organic insulation film figure of the different black of intermediate tone mask version or gray tone mask plate height of formation.In Fig. 9 (a), TFT device top is the support column 91 that thickness is relatively high, and the top of other metal wires is the relatively low black matrix" of thickness 92.The cross-section structure of corresponding diagram 9 (a) dotted line AA ' is as shown in Fig. 9 (b).As another embodiment, dot structure that this embodiment provides and preparation method thereof is only with the difference of above-described embodiment: this storage electrode is disposed at this first public electrode wire and the upper left corner of this second public electrode wire view field and the first area in the lower right corner, and this storage electrode configures the second projection region at non-this projection lap, on it form this second contact hole, for and this pixel electrode between equipotential be connected.

The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, any be familiar with those skilled in the art the present invention disclose technical scope in; can expect easily changing or replacing, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.

Claims (10)

1. an array base palte, it comprises:
One substrate, disposes the first metal layer, metal dielectric layer, semiconductor layer, the second metal level, protection insulation course, transparent organic insulating film, pixel electrode layer, black organic insulator successively on it;
Wherein, the first metal layer, it comprises:
Multi-strip scanning line, described in each, sweep trace is arranged on the horizontal central line of each this pixel region, and with many data line settings intersected with each other;
Multiple storage electrodes, are disposed at the below of pixel electrode, and overlapping with the first public electrode and the second public electrode view field, and this storage electrode is by the second contact hole and the electric connection of this pixel electrode;
The second metal level, it comprises:
Many the first public electrode wires, have the discontinuous distributing line that is uniformly distributed gap;
Many the second public electrode wires, surround pixel region array with these many first public electrode wire cross connections;
Many data lines, described in each, data line is arranged on the median vertical line of each this pixel region, and through this gap to should the first public electrode wire;
Active member, is arranged at each this data line and each this sweep trace intersection region;
Multiple pixel electrodes, each this pixel electrode is electrically connected by the first contact hole and this active member;
Black organic insulator, is disposed at this pixel electrode top, and forms the first elevational pattern and the second elevational pattern, and wherein, the first elevational pattern is support column, and the second elevational pattern is black matrix".
2. the array base palte as described in claim 1, wherein, this first elevational pattern and this second elevational pattern form by intermediate tone mask version or the exposure of gray tone mask plate.
3. the array base palte as described in claim 1, wherein, this black matrix" covers this sweep trace, this storage electrode, this data line, this first and second public electrode wire, this active member; This support column is evenly arranged in this sweep trace and data line intersection region and/or this first and second public power polar curve intersection region.
4. array base palte as claimed in claim 1, it is characterized in that: this storage electrode is disposed at this first public electrode wire and the upper left corner of this second public electrode wire view field and the first area in the lower right corner, and this storage electrode configures the second projection region at non-this projection lap, on it form this second contact hole, for and this pixel electrode between equipotential be connected.
5. array base palte as claimed in claim 1, it is characterized in that: this storage electrode is disposed at the lower left corner and the first area, the upper right corner of this first public electrode wire and this second public electrode wire view field, and this storage electrode configures the second projection region at non-this projection lap, on it form this second contact hole, for and this pixel electrode between equipotential be connected.
6. the array base palte as described in claim 4 or 5, is characterized in that: below this pixel electrode, and the view field of this first area of this storage electrode and this first public electrode wire and this second public electrode wire formation memory capacitance that partly overlaps.
7. the dot structure as described in claim 4 or 5, is characterized in that: below this pixel electrode, the view field of this first area of this storage electrode and this first public electrode and this second public electrode overlaps to form memory capacitance completely.
8. a display device, the array base palte that it comprises as described in claim 1, also comprises a counter substrate, this substrate is the glass substrate that is coated with ITO; Between this array base palte and this counter substrate, be folded with display dielectric layer.
9. a manufacture method for array base palte as claimed in claim 1, it comprises the following steps:
A. on this substrate, form the first metal layer, it comprises sweep trace and pixel storage electrode;
B. form semiconductor figure, semiconductor material is amorphous silicon, polysilicon or metal oxide;
C. form source, drain electrode, data line, first and second public electrode wire;
D. form protection insulation course, transparent organic insulating film;
E. form contact hole;
F. form pixel electrode;
G. form black organic insulator, by intermediate tone mask version or gray tone mask plate, form the first elevational pattern and the second elevational pattern, wherein, the first elevational pattern is support column, and the second elevational pattern is black matrix".
10. the manufacture method of the array base palte as described in claim 9, wherein, this protection insulation course is SiO2, SiNx or Al2O3, and the thickness of this protection insulation course is the thickness of this organic insulator is at 1um-3um.
CN201410274667.0A 2014-06-18 2014-06-18 Array substrate, display device and manufacturing method of array substrate CN104049430B (en)

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CN104485349A (en) * 2014-12-26 2015-04-01 昆山工研院新型平板显示技术中心有限公司 Frame-free display screen device
CN104576655A (en) * 2014-12-01 2015-04-29 深圳市华星光电技术有限公司 COA substrate and manufacturing method thereof
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CN106019745A (en) * 2016-06-21 2016-10-12 上海纪显电子科技有限公司 Display device, array substrate and production method of array substrate
CN107357076A (en) * 2017-08-16 2017-11-17 深圳市华星光电半导体显示技术有限公司 Transmitting/reflecting LCD and preparation method thereof

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