CN103560114A - TFT array substrate, manufacturing method thereof and display device - Google Patents
TFT array substrate, manufacturing method thereof and display device Download PDFInfo
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- CN103560114A CN103560114A CN201310573218.1A CN201310573218A CN103560114A CN 103560114 A CN103560114 A CN 103560114A CN 201310573218 A CN201310573218 A CN 201310573218A CN 103560114 A CN103560114 A CN 103560114A
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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Abstract
The embodiment of the invention provides a TFT array substrate, a manufacturing method thereof and a display device, and relates to the display technical field. The manufacturing process of a vertical-structure TFT can be simplified, and the using number of a composition technology is decreased. The array substrate comprises a drain electrode pattern formed on the surface of the substrate, a semiconductor active layer pattern is formed on the surface of the drain electrode pattern in a semiconductor processing mode, and an active electrode pattern is formed on the surface of the semiconductor active layer pattern. The drain electrode pattern, the semiconductor active layer pattern and a source electrode pattern are formed through the one-time composition technology.
Description
Technical field
The present invention relates to Display Technique field, relate in particular to a kind of tft array substrate and manufacture method thereof, display unit.
Background technology
Develop rapidly along with Display Technique, TFT-LCD(Thin Film Transistor LiquidCrystal Display, Thin Film Transistor-LCD) as a kind of panel display apparatus, because it has the features such as little, low in energy consumption, the radiationless and cost of manufacture of volume is relatively low, and be applied to more and more in the middle of high-performance demonstration field.
TFT-LCD consists of array base palte and color membrane substrates.A plurality of dot structures that the array base palte of TFT-LCD of the prior art is arranged by matrix form conventionally form, its typical structure as shown in Figure 1, the grid line 10 and the data wire 11 that comprise transverse and longitudinal intersection are divided a plurality of pixel cells 12 that form, and at grid line 10, are provided with thin-film transistor (TFT) with the crossover location place of data wire 11.The size of TFT region is relevant with the pixel aperture ratio of array base palte, and TFT region is larger, and pixel aperture ratio is just less, therefore can reduce the light emission rate of light, thereby affect the display effect of display.
In order to improve the aperture opening ratio of pixel, in prior art, can adopt the vertical TFT structure of a kind of top gate type, as shown in Figure 2.A kind of like this TFT of structure, its drain electrode 13 and source electrode 14 adopt overlapping mode to make, therefore compare with the TFT with parallel source, drain electrode, the TFT region of this top gate type vertical stratification is relatively little, thereby can be so that pixel region can access larger aperture area, thereby improve pixel aperture ratio.
Yet in prior art, as shown in Figure 2, in making the process of top gate type vertical stratification TFT, first, at the substrate surface that is formed with pixel electrode 15 patterns, apply a kind of metal material and by composition technique, form again the pattern of drain electrode 13, then be formed with the substrate surface deposited semiconductor material of above-mentioned pattern, thereby by composition technique, forming the pattern of semiconductor active layer 16; At the substrate surface that is formed with semiconductor active layer 16 patterns, again apply another kind of metal material afterwards, thereby by composition technique, form the pattern of source electricity level 14; Next at the substrate surface that forms active electrode 14 patterns, by composition technique, form successively the pattern of grid 17, passivation layer 18 and public electrode 19.So, in manufacturing process, owing to repeatedly adopting coating or depositing operation to make to make manufacturing procedure complexity, cause production efficiency low, production cost improves.And repeatedly the use of composition technique can cause the stack of mismachining tolerance, thereby reduced product quality.
Summary of the invention
Embodiments of the invention provide a kind of tft array substrate and manufacture method thereof, display unit.Can simplify the production process of vertical stratification TFT, reduce composition technique access times.
For achieving the above object, embodiments of the invention adopt following technical scheme:
The one side of the embodiment of the present invention provides a kind of manufacture method of tft array substrate, comprising:
At substrate surface, form the first metal layer;
Surface at described the first metal layer is processed and is formed semiconductor active layer by semiconductor transformation;
On the surface of described semiconductor active layer, form the second metal level;
By composition technique, form the pattern that comprises drain electrode, described semiconductor active layer, source electrode.
The embodiment of the present invention a kind of tft array substrate is provided on the other hand, comprising:
Be formed on the pattern of the drain electrode of substrate surface;
The pattern that is formed with semiconductor active layer is processed on the surface of the pattern of described drain electrode by semiconductor transformation;
The surface of the pattern of described semiconductor active layer forms the pattern of active electrode.
The another aspect of the embodiment of the present invention provides a kind of display unit, comprises any one tft array substrate as above.
The invention provides a kind of tft array substrate and manufacture method thereof, display unit.The method is included in the pattern that substrate surface forms drain electrode, the pattern that forms semiconductor active layer is processed on surface at the pattern of drain electrode by semiconductor transformation, at the pattern of formation source, the surface electrode of the pattern of this semiconductor active layer, wherein the pattern of drain electrode, semiconductor active layer, source electrode forms by a composition technique.So, can simplify production process, reduce manufacture craft.Thereby enhance productivity, reduce production costs.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
A kind of tft array substrate structure vertical view that Fig. 1 provides for prior art;
A kind of tft array substrate structural representation that Fig. 2 provides for prior art;
The manufacture method flow chart of a kind of tft array substrate that Fig. 3 provides for the embodiment of the present invention;
Structure and the manufacture method schematic diagram of a kind of tft array substrate that Fig. 4 provides for the embodiment of the present invention;
The manufacture method schematic diagram of a kind of tft array substrate that Fig. 5 provides for the embodiment of the present invention;
The structural representation of the another kind of tft array substrate that Fig. 6 provides for the embodiment of the present invention;
The structural representation of another tft array substrate that Fig. 7 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
The embodiment of the present invention provides a kind of manufacture method of tft array substrate, as shown in Figure 3, Figure 4, comprising:
S101, on substrate 01 surface, form the first metal layer 03.Wherein, substrate 01 is transparency carrier, can adopt clear glass or transparent resin material to make.
S102, on the surface of the first metal layer 03, by semiconductor transformation, process and form semiconductor active layer 16.
S103, on the surface of semiconductor active layer 16, form the second metal level 04.
S104, by composition technique, form the pattern comprise drain electrode 13, semiconductor active layer 16, source electrode 14.
It should be noted that, in the present invention, composition technique can refer to comprise photoetching process, or, comprise photoetching process and etch step, can also comprise printing, ink-jet etc. other are used to form the technique of predetermined pattern simultaneously; Photoetching process, refers to that utilize photoresist, mask plate, the exposure machine etc. of technical processs such as comprising film forming, exposure, development form the technique of figure.The corresponding composition technique of formed structure choice in can be according to the present invention.
The invention provides a kind of manufacture method of tft array substrate.The method is included in the pattern that substrate surface forms drain electrode, the pattern that forms semiconductor active layer is processed on surface at the pattern of drain electrode by semiconductor transformation, at the pattern of formation source, the surface electrode of the pattern of this semiconductor active layer, wherein the pattern of drain electrode, semiconductor active layer, source electrode forms by a composition technique.So, can simplify production process, reduce manufacture craft.Thereby enhance productivity, reduce production costs.
Further, above-mentioned semiconductor transformation is processed and can be comprised:
By oxidation technology, the first metal layer 03 is oxidized and forms the metal oxide layer with characteristic of semiconductor.
Wherein, described oxidation technology comprises Implantation mode or electrochemical means.Preferably, the first metal layer 03 and the second metal level 04 all can adopt metallic copper to form.By metallic copper is oxidized, form cuprous oxide semiconductive thin film, so semiconductor active layer 16 can be above-mentioned cuprous oxide semiconductive thin film.
Concrete, when the first metal layer 03 and the second metal level 04 employing metallic copper formation, can by Implantation mode, make it change cuprous nano film on the first metal layer 03 surface; Or the oxygen atmosphere that the first metal layer 03 is placed in to high temperature makes the surface of the first metal layer 03 form cuprous nano film; Or, the first metal layer 03 is placed in and under ethanol environment, makes the surface of the first metal layer 03 form cuprous nano film.Then using above-mentioned cuprous nano film as semiconductor active layer 16.On the surface of above-mentioned semiconductor active layer 16, deposit again layer of metal copper again and form the second metal level 04.So,, as long as the processing conditions that can be oxidized the first metal layer 03 is provided, just can forms the structure of above-mentioned copper-cuprous oxide film-copper, and form said structure without techniques such as Multiple through then out coating, sputter or depositions.Thereby simplification manufacture craft, reduces difficulty of processing and production cost.Certainly, above-mentionedly only the first metal layer is carried out to illustrating of semiconductor transformation processing, other modes here illustrate no longer one by one, but all should belong to protection scope of the present invention.
It should be noted that, the oxide of metallic copper can be cupric oxide and cuprous oxide, and they have characteristic of semiconductor, at normal temperatures its electric conductivity between conductor (conductor) and insulator (insulator).The cuprous pattern as forming semiconductor active layer 16 of embodiment of the present invention preferential oxidation.Certainly; in embodiments of the present invention; the metallic copper of take is illustrated the first metal layer 03, semiconductor active layer 16 and the second metal level 04 as example; other corresponding metal of oxide with characteristic of semiconductor is here given an example no longer one by one, but all should belong to protection scope of the present invention.
Further, above-mentioned composition technique can comprise:
Between substrate 01 and the first metal layer 03, form electrode layer 02.
Adopt intermediate tone mask plate by mask exposure technique, to form successively the stepped stacked structure that comprises the first transparency electrode 20, drain electrode 13, semiconductor active layer 16, source electrode 14 patterns.
Wherein, the area of drain electrode 13, semiconductor active layer 16 and source electrode 14 patterns is less than the area of the first transparency electrode 20 patterns.
Concrete, as shown in Figure 5, at the substrate surface that is formed with successively electrode layer 02, the first metal layer 03, semiconductor active layer 16, the second metal level 04, apply photoresist 05, by intermediate tone mask plate, photoresist 05 is carried out to exposure-processed, form unexposed area P1, half exposure area P2 and full exposure area P3.Then photoresist 05 is developed, the photoresist that is positioned at exposure area P1 is retained completely; The photoresist that is positioned at half exposure area P2 is partly removed; The photoresist that is positioned at full exposure area P3 is removed completely.Wherein as shown in Figure 5, unexposed area P1 is corresponding with the position of drain electrode 13, semiconductor active layer 16, source electrode 14 regions; Half exposure area is corresponding with the position of the first transparency electrode 20 regions; On substrate, remainder is corresponding with the position of full exposure area.
Photoresist is being carried out after mask exposure, first by etching technics, removing and the corresponding electrode layer 02 of complete exposure area P3, the first metal layer 03, semiconductor active layer 16, the second metal level 04; Photoresist 05 is carried out to ashing processing, to remove all photoresists 05 of half exposure area P2 and the part photoresist of unexposed area P1, then by etching technics, remove the corresponding the first metal layer 03 of half exposure area P2, semiconductor active layer 16, the second metal level 04; Finally the photoresist of unexposed area P1 is removed completely, on substrate 01, formed the pattern that comprises the first transparency electrode 20, drain electrode 13, semiconductor active layer 16, source electrode 14.So, adopt half-tone mask plate can realize by a composition technique and on substrate 01, form successively the pattern that comprises the first transparency electrode 20, drain electrode 13, semiconductor active layer 16, source electrode 14.
Further, as shown in Figure 6, the method can also comprise:
Substrate surface at the source of formation electrode 14 patterns forms the pattern of gate insulator 21, grid 17 successively by composition technique.Thereby complete the making of tft array substrate.
Concrete, the pattern of the pattern of grid 17 and semiconductor active layer 16 lays respectively at the both sides of gate insulator 21 patterns.And the pattern of grid 17 is positioned at the side away from substrate 01, drain electrode 13, active layer 16, source electrode 14 and grid 17 are successively along stacking the forming of direction perpendicular to substrate 01.So, just can form the tft array substrate of top gate type vertical stratification.A kind of like this TFT of structure, its drain electrode 13 and source electrode 14 adopt overlapping mode to make, therefore compare with traditional TFT structure with raceway groove, the TFT region of this top gate type vertical stratification is relatively little, thereby can be so that pixel region can access larger aperture area, thereby improve pixel aperture ratio.
Further, as shown in Figure 7, before the step that forms semiconductor active layer 16 patterns, also comprise:
Form the pattern of reflecting electrode 22; Reflecting electrode 22 and the same material of drain electrode 13 same layer.
Wherein, the area of reflecting electrode 22 is less than the area of the first transparency electrode 20.That is, this reflecting electrode 22 can not cover in the first transparency electrode 20 completely.For example, for the array base palte of half-reflection and half-transmission structure, the part that the area of the reflector space that reflecting electrode 22 forms is pixel region, and the regional transmission that another part of pixel region unlapped the first transparency electrode 20 that is above-mentioned reflecting electrode 22 forms.
Concrete, can this adopt aforesaid mask exposure technique to form on substrate to form in drain electrode 13 with this drain electrode 13 with layer the reflecting electrode 22 with material.So, just can complete the making of Transflective array base palte.Without the extra technique of making reflecting electrode that increases, thereby simplify manufacturing procedure, boost productivity.
It should be noted that, adopt display that the array base palte of this half-reflection and half-transmission formula processes can using at its transmission region the light that backlight sends and show as light source, and reflector space can be usingd after injecting the reflection of display natural daylight and shown as light source.So, Transflective display can be saved electric power and can under night or low-light environment, use again.
Further, as shown in Figure 7, the manufacture method of this tft array substrate can also comprise:
At the substrate surface that is formed with gate insulator 21, grid 17 patterns, by composition technique, form successively the pattern of passivation layer 18, the second transparency electrode 23.
It should be noted that, the array base palte that the embodiment of the present invention provides goes for TN(Twist Nematic, twisted-nematic) type, AD-SDS(Advanced-Super Dimensional Switching, referred to as ADS, senior super dimension field switch) type, IPS(In Plane Switch, the transverse electric field effect) production of the liquid crystal indicator of the type such as type.Above-mentioned which kind of liquid crystal indicator all comprises color membrane substrates and the array base palte that box is shaped.Different, the public electrode of TN type display unit is arranged on color membrane substrates, and pixel electrode is arranged on array base palte; Public electrode and the pixel electrode of ADS type display unit and IPS type display unit are all arranged on array base palte.
As shown in Figure 7, the first transparency electrode 20 and the second transparency electrode 23 are all arranged on array base palte.Optionally, the first transparency electrode 20 is pixel electrode, and the second transparency electrode 23 is public electrode; Or,
The first transparency electrode 20 can also be public electrode, and the second transparency electrode 23 can also be pixel electrode.Concrete, can form the first transparency electrode 20 and conductive electrode structure by electrode layer 02 is carried out to composition PROCESS FOR TREATMENT simultaneously, wherein the first transparency electrode 20 and conductive electrode are not electrically connected to, and this conductive electrode is connected with drain electrode 13.When the first transparency electrode 20 is public electrode, when the second transparency electrode 23 is pixel electrode, this pixel electrode can be by being positioned at the via hole and drain electrode 13(or conductive electrode on gate insulator 21 and passivation layer 18) be electrically connected to.Certainly, above is only also to the illustrating of concrete electrode structure in the present invention, and the restriction of not the present invention being done.
Concrete, the first transparency electrode 20 can be planar structure, the second transparency electrode 23 can be the narrow slit structure of space; Or the first transparency electrode 20 and the second transparency electrode 23 can be all narrow slit structure.
For example, the array base palte that the embodiment of the present invention provides goes for AD-SDS(Advanced-Super Dimensional Switching, referred to as ADS, senior super dimension field switch) production of the liquid crystal indicator of type.The electrode that the first transparency electrode 20 and the second transparency electrode 23 be spaced narrow slit structure of take is example, a kind of like this array base palte of structure is often used as the production of ADS type liquid crystal indicator, the longitudinal electric field that ADS technology produces by parallel electric field that in same plane, pixel electrode edge produces and pixel electrode layer and public electrode interlayer forms multi-dimensional electric field, make between the interior pixel electrode of liquid crystal cell, directly over electrode, all aligned liquid-crystal molecules can both produce rotation conversion, compare with the display unit of other types, ADS type liquid crystal indicator has further improved planar orientation to be liquid crystal operating efficiency and to have increased light transmission efficiency.
In the array base palte of ADS type display unit, public electrode and pixel electrode can be different layer arrange, the electrode that is wherein positioned at upper strata comprises a plurality of slit-type electrodes, the electrode that is positioned at lower floor comprises a plurality of slit-type electrodes or is plate-shaped electrode.
Different layer arranges at least two kinds of patterns, and at least two kinds of different layer settings of pattern refer to, at least double-layer films forms at least two kinds of patterns by composition technique respectively.For two kinds of different layer settings of pattern, refer to, by composition technique, by double-layer films, respectively form a kind of pattern.For example, the different layer setting of public electrode and pixel electrode refers to: by ground floor transparent conductive film, by composition technique, form lower electrode, by second layer transparent conductive film, by composition technique, form upper electrode, wherein, lower electrode is public electrode (or pixel electrode), and upper electrode is pixel electrode (or public electrode).
In the array base palte of IPS type display unit, public electrode and pixel electrode arrange with layer, and public electrode comprises a plurality of slit-type electrodes, and pixel electrode comprises a plurality of slit-type electrodes, and between a plurality of slit-type electrodes, interval arranges.
With layer, arrange at least two kinds of patterns; At least two kinds of patterns refer to layer setting: same film is formed at least two kinds of patterns by composition technique.For example, public electrode and pixel electrode refer to layer setting: by same transparent conductive film, by composition technique, form pixel electrode and public electrode.Wherein, pixel electrode refers to the electrode for example, being electrically connected to data wire by switch element (, can be thin-film transistor), and public electrode refers to the electrode being electrically connected to public electrode wire.
The embodiment of the present invention provides a kind of tft array substrate, as shown in Figure 4, comprising:
Be formed on the pattern of the drain electrode 13 on substrate 01 surface.Wherein, substrate 01 is transparency carrier, can adopt clear glass or transparent resin material to make.
The pattern that is formed with semiconductor active layer 16 is processed on the surface of the pattern of drain electrode 13 by semiconductor transformation.
The surface of the pattern of semiconductor active layer 16 forms the pattern of active electrode 14.
It should be noted that, in the present invention, composition technique can refer to comprise photoetching process, or, comprise photoetching process and etch step, can also comprise printing, ink-jet etc. other are used to form the technique of predetermined pattern simultaneously; Photoetching process, refers to that utilize photoresist, mask plate, the exposure machine etc. of technical processs such as comprising film forming, exposure, development form the technique of figure.The corresponding composition technique of formed structure choice in can be according to the present invention.
It should be noted that, above-mentioned semiconductor transformation is processed and can be comprised:
By oxidation technology, the first metal layer 03 is oxidized and forms the metal oxide layer with characteristic of semiconductor.
Wherein, described oxidation technology comprises Implantation mode or electrochemical means.Preferably, the first metal layer 03 and the second metal level 04 all can adopt metallic copper to form.By metallic copper is oxidized, form cuprous oxide semiconductive thin film, so semiconductor active layer 16 can be above-mentioned cuprous oxide semiconductive thin film.
Concrete, when the first metal layer 03 and the second metal level 04 employing metallic copper formation, can by Implantation mode, make it change cuprous nano film on the first metal layer 03 surface; Or the oxygen atmosphere that the first metal layer 03 is placed in to high temperature forms cuprous nano film; Or, thereby the first metal layer 03 is placed in to formation cuprous nano film under ethanol environment.Then using above-mentioned cuprous nano film as semiconductor active layer 16.On the surface of above-mentioned semiconductor active layer 16, deposit again layer of metal copper again and form the second metal level 04.So,, as long as the processing conditions that can be oxidized the first metal layer 03 is provided, just can forms the structure of above-mentioned copper-cuprous oxide film-copper, and form said structure without techniques such as Multiple through then out coating, sputter or depositions.Thereby simplification manufacture craft, reduces difficulty of processing and production cost.Certainly, above-mentionedly only the first metal layer is carried out to illustrating of semiconductor transformation processing, other modes here illustrate no longer one by one, but all should belong to protection scope of the present invention.
It should be noted that, the oxide of metallic copper can be cupric oxide and cuprous oxide, and they have characteristic of semiconductor, at normal temperatures its electric conductivity between conductor (conductor) and insulator (insulator).The cuprous pattern as forming semiconductor active layer 16 of embodiment of the present invention preferential oxidation.Certainly; in embodiments of the present invention; the metallic copper of take is illustrated the first metal layer 03, semiconductor active layer 16 and the second metal level 04 as example; other corresponding metal of oxide with characteristic of semiconductor is here given an example no longer one by one, but all should belong to protection scope of the present invention.
The invention provides a kind of tft array substrate.This array base palte is included in the pattern of the drain electrode of substrate surface formation, the pattern that is formed with semiconductor active layer is processed on surface at the pattern of drain electrode by semiconductor transformation, the pattern that forms active electrode on the surface of the pattern of this semiconductor active layer, wherein the pattern of drain electrode, semiconductor active layer, source electrode forms by a composition technique.So, can simplify production process, reduce manufacture craft.Thereby enhance productivity, reduce production costs.
Further, as shown in Figure 4, between substrate 01 and drain electrode 13, be formed with the first transparency electrode 20.
The first transparency electrode 20, drain electrode 13, semiconductor active layer 16, source electrode 14 patterns are stepped stacked structure.
Wherein, the area of drain electrode 13, semiconductor active layer 16 and source electrode 14 patterns is less than the area of the first transparency electrode 20 patterns.Above-mentioned stepped stacked structure can adopt intermediate tone mask plate to form by a composition technique, thereby can reduce the composition technique of making array base palte.
Further, as shown in Figure 6, this tft array substrate also comprises:
The surface of source electrode 14 patterns is formed with the pattern of gate insulator 21;
The surface of gate insulating layer pattern 21 is formed with the pattern of grid 17.
Wherein, the pattern of the pattern of grid 17 and semiconductor active layer 16 lays respectively at the both sides of gate insulator 21 patterns.So, just can form the tft array substrate of top gate type vertical stratification.A kind of like this TFT of structure, its drain electrode 13 and source electrode 14 adopt overlapping mode to make, therefore compare with traditional TFT structure with raceway groove, the TFT region of this top gate type vertical stratification is relatively little, thereby can be so that pixel region can access larger aperture area, thereby improve pixel aperture ratio.
The embodiment of the present invention provides a kind of display unit, comprises any one tft array substrate as above.The identical beneficial effect of array base palte providing with previous embodiment of the present invention is provided, because array base palte has been described in detail in the aforementioned embodiment, repeats no more herein.
This display unit is specifically as follows any liquid crystal display product or parts with Presentation Function such as liquid crystal display, LCD TV, DPF, mobile phone, panel computer.
The invention provides a kind of display unit.This display unit comprises tft array substrate.This tft array substrate is included in the pattern of the drain electrode of substrate surface formation, the pattern that is formed with semiconductor active layer is processed on surface at the pattern of drain electrode by semiconductor transformation, the pattern that forms active electrode on the surface of the pattern of this semiconductor active layer, wherein the pattern of drain electrode, semiconductor active layer, source electrode forms by a composition technique.So, can simplify production process, reduce manufacture craft.Thereby enhance productivity, reduce production costs.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (15)
1. a manufacture method for tft array substrate, is characterized in that, comprising:
At substrate surface, form the first metal layer;
Surface at described the first metal layer is processed and is formed semiconductor active layer by semiconductor transformation;
On the surface of described semiconductor active layer, form the second metal level;
By composition technique, form the pattern that comprises drain electrode, described semiconductor active layer, source electrode.
2. the manufacture method of tft array substrate according to claim 1, is characterized in that, semiconductor transformation is processed and comprised:
By oxidation technology, the first metal layer is oxidized and forms the metal oxide layer with characteristic of semiconductor.
3. the manufacture method of tft array substrate according to claim 2, is characterized in that,
Described the first metal layer and described the second metal level all adopt metallic copper to make;
Described semiconductor active layer is cuprous oxide semiconductive thin film.
4. the manufacture method of tft array substrate according to claim 1 and 2, is characterized in that, described composition technique comprises:
Between described substrate and described the first metal layer, form electrode layer;
Adopt intermediate tone mask plate by mask exposure technique, to form successively the stepped stacked structure that comprises the first transparency electrode, described drain electrode, described semiconductor active layer, described source electrode pattern;
Wherein, the area of described drain electrode, described semiconductor active layer and described source electrode pattern is less than the area of described the first transparent electrode pattern.
5. the manufacture method of tft array substrate according to claim 1 and 2, is characterized in that, described method also comprises:
Substrate surface at the source of formation electrode pattern forms the pattern of gate insulator, grid successively by composition technique.
6. the manufacture method of tft array substrate according to claim 5, is characterized in that, the pattern of described grid and the pattern of described semiconductor active layer lay respectively at the both sides of described gate insulating layer pattern.
7. the manufacture method of tft array substrate according to claim 6, is characterized in that, before the step that forms described semiconductor active layer pattern, also comprises:
Form the pattern of reflecting electrode; Described reflecting electrode and described drain electrode are with the same material of layer;
Wherein, the area of described reflecting electrode is less than the area of described the first transparency electrode.
8. the manufacture method of tft array substrate according to claim 7, is characterized in that, also comprises:
At the substrate surface that is formed with described gate insulator, described gate pattern, by composition technique, form successively the pattern of passivation layer, the second transparency electrode.
9. the manufacture method of tft array substrate according to claim 8, is characterized in that,
Described the first transparency electrode is pixel electrode, and the second transparency electrode is public electrode; Or,
Described the first transparency electrode is public electrode; The second transparency electrode is pixel electrode.
10. the manufacture method of tft array substrate according to claim 3, is characterized in that, described oxidation technology comprises: Implantation mode or electrochemical means.
11. 1 kinds of tft array substrates, is characterized in that, comprising:
Be formed on the pattern of the drain electrode of substrate surface;
The pattern that is formed with semiconductor active layer is processed on the surface of the pattern of described drain electrode by semiconductor transformation;
The surface of the pattern of described semiconductor active layer forms the pattern of active electrode.
12. tft array substrates according to claim 11, is characterized in that,
Between described substrate and described drain electrode, be formed with the first transparency electrode;
Described the first transparency electrode, described drain electrode, described semiconductor active layer, described source electrode pattern are stepped stacked structure;
Wherein, the area of described drain electrode, described semiconductor active layer and described source electrode pattern is less than the area of described the first transparent electrode pattern.
13. tft array substrates according to claim 12, is characterized in that, also comprise:
The surface of described source electrode pattern is formed with the pattern of gate insulator;
The surface of described gate insulating layer pattern is formed with the pattern of grid.
14. tft array substrates according to claim 13, is characterized in that, also comprise:
The pattern of described grid and the pattern of described semiconductor active layer lay respectively at the both sides of described gate insulating layer pattern.
15. 1 kinds of display unit, is characterized in that, comprise the tft array substrate as described in claim 11-14 any one.
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