JP2011124562A - Nonlinear element, display device with the nonlinear element, and electronic apparatus with the display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonlinear element, such as diodes, using an oxide semiconductor and having good rectification characteristics. <P>SOLUTION: A transistor having an oxide semiconductor of ≤5×10<SP>19</SP>/cm<SP>3</SP>in hydrogen concentration is configured to satisfy ϕms>χ≥ϕmd, where ϕms represents a work function of a source electrode in contact with the oxide semiconductor, ϕmd represents a work function of a drain electrode in contact with the oxide semiconductor and χ represents electron affinity of the oxide semiconductor, and is characterized in that the gate and drain of the transistor are electrically connected to each other. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

One embodiment of the present invention relates to a nonlinear element (e.g., a diode) using an oxide semiconductor and a semiconductor device such as a display device including the nonlinear element. Furthermore, it is related with the electronic device which has these.

Among semiconductor devices, diodes are required to have a high breakdown voltage and a low reverse saturation current. In order to satisfy such a demand, a diode using silicon carbide (SiC) has been studied. In other words, silicon carbide as a semiconductor material has a forbidden band width of 3 eV or more, excellent controllability of electrical conductivity at high temperatures, and has a dielectric breakdown electric field that is about an order of magnitude higher than that of silicon. Application to high-diode is being studied. For example, a Schottky barrier diode using silicon carbide that has a reduced leakage current in the reverse direction is known (see Patent Document 1).

However, silicon carbide has a problem that it is difficult to obtain a high-quality crystal, and the process temperature when manufacturing a device is high. For example, an ion implantation method is used to form an impurity region in silicon carbide, but heat treatment at 1500 ° C. or higher is required to activate a dopant and recover crystal defects induced by ion implantation.

Further, since carbon is contained as a component, there is a problem that a high-quality insulating layer cannot be produced by thermal oxidation. Furthermore, since silicon carbide is extremely stable chemically, it has a problem that normal wet etching is difficult.

Japanese Unexamined Patent Publication No. 2000-133819

As described above, a diode using silicon carbide is expected to achieve a high withstand voltage and a small reverse saturation current. However, in order to actually manufacture this diode, a great number of problems are inherent. Realization is extremely difficult.

In view of the above, an object of one embodiment of the present invention is to provide a non-linear element such as a diode having high breakdown voltage and good rectification characteristics. Another object of the present invention is to manufacture a non-linear element such as a diode having a low reverse saturation current at a low process temperature (for example, 800 ° C. or lower).

According to one embodiment of the present invention, a hydrogen concentration detected by a first ion formed over a substrate and secondary ion mass spectrometry formed in contact with the first electrode is 5 × 10 ¹⁹ / cm ^3. An oxide semiconductor layer, a second electrode formed on and in contact with the oxide semiconductor layer, a gate insulating layer covering the first electrode, the oxide semiconductor layer, and the second electrode, and gate insulation A first electrode, an oxide semiconductor layer, and a plurality of third electrodes opposed to each other via the second electrode, and the plurality of third electrodes includes the second electrode and the second electrode The work function φms of the first electrode, the electron affinity χ of the oxide semiconductor layer, and the work function φmd of the second electrode are configured to satisfy φms ≦ χ ≧ φmd.

In addition, according to one embodiment of the present invention, the first electrode formed over the substrate and the hydrogen concentration detected by secondary ion mass spectrometry formed in contact with the first electrode are 5 × 10 ¹⁹ / an oxide semiconductor layer having a thickness of cm ³ or less; a second electrode formed over and in contact with the oxide semiconductor layer; a gate insulating layer covering the first electrode, the oxide semiconductor layer, and the second electrode; A plurality of third electrodes which are formed in contact with the gate insulating layer and are opposed to each other with the first electrode, the oxide semiconductor layer, and the second electrode interposed therebetween; The work function φms of the first electrode, the electron affinity χ of the oxide semiconductor layer, and the work function φmd of the second electrode are connected to the electrode so that φms> χ ≧ φmd. is there.

Specifically, the concentration of hydrogen contained in the oxide semiconductor layer is 5 × 10 ¹⁹ / cm ³ or less, preferably 5 × 10 ¹⁸ / cm ³ or less, more preferably 5 × 10 ¹⁷ / cm ³ or less, or 1 Hydrogen or OH groups contained in the oxide semiconductor layer are removed so that the density is less than × 10 ¹⁶ / cm ³ , and the carrier concentration is less than 1 × 10 ¹² / cm ³ , preferably less than 1 × 10 ¹¹ / cm ^3. An oxide semiconductor layer is used.

In addition, the energy gap of the oxide semiconductor is set to 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more, impurities such as hydrogen forming a donor are reduced as much as possible, and the carrier concentration is set to 1 × 10 ¹² / cm. ^It should be less than ³ , preferably less than 1 × 10 ¹¹ / cm ³ .

When the electron affinity χ of the oxide semiconductor is 4.3 eV, as an electrode material having a work function larger than that of the oxide semiconductor, tungsten (W), molybdenum (Mo), chromium (Cr), iron (Fe), gold (Au), platinum (Pt), copper (Cu), cobalt (Co), nickel (Ni), beryllium (Be), indium tin oxide (ITO), or the like can be used.

Further, when the electron affinity χ of the oxide semiconductor is 4.3 eV, as an electrode material having a work function equal to or lower than the electron affinity χ of the oxide semiconductor, titanium (Ti), yttrium (Y), aluminum (Al), zirconium (Zr), magnesium (Mg), silver (Ag), manganese (Mn), tantalum (Ta), tantalum nitride, titanium nitride, or the like can be used.

Note that in this specification, the impurity concentration is determined by secondary ion mass spectrometry (hereinafter also referred to as SIMS). However, this is not the case when there is a particular description such as when other measurement methods are mentioned.

One embodiment of the present invention provides a nonlinear element such as a diode that can be miniaturized and includes a transistor with high on-state current and low off-state current, which can be manufactured at a low process temperature.

A diode that can be miniaturized and has excellent rectification characteristics can be obtained. A diode in which an avalanche breakdown phenomenon does not easily occur (that is, a high breakdown voltage) can be manufactured.

4A and 4B are a top view and cross-sectional views illustrating a diode which is one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a diode which is one embodiment of the present invention. FIG. 10 illustrates a diode which is one embodiment of the present invention. It is a band figure explaining an energy barrier. It is a figure which shows the simulation result of the diode which is 1 aspect of this invention. 4A and 4B are a top view and cross-sectional views illustrating a diode which is one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a diode which is one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a diode which is one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a diode which is one embodiment of the present invention. 10A to 10D are cross-sectional views illustrating a method for manufacturing a diode which is one embodiment of the present invention. 10A to 10D are cross-sectional views illustrating a method for manufacturing a diode which is one embodiment of the present invention. FIG. 10 illustrates a display device which is one embodiment of the present invention. FIG. 10 illustrates a protection circuit which is one embodiment of the present invention. FIG. 10 illustrates a protection circuit which is one embodiment of the present invention. FIG. 11 illustrates an electronic device which is one embodiment of the present invention.

A transistor is a kind of semiconductor element, and can realize amplification of current and voltage, switching operation for controlling conduction or non-conduction, and the like. Various forms of transistors such as bipolar transistors and field effect transistors have been devised. Field effect transistors are also called FETs (Field Effect Transistors), IGFETs (Insulated Gate FETs), MISFETs (Metal Insulator Semiconductor FETs), and the like. In particular, a field effect transistor using an oxide insulating layer as a gate insulating layer is a MOSFET (Metal Oxide). This is referred to as a Semiconductor FET). A transistor formed in a thin film shape on a substrate such as glass, quartz, or plastic using a thin film forming technique such as a vacuum evaporation method, a sputtering method, or a CVD method is called a thin film transistor (TFT). It is.

Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

Note that in each drawing described in this specification, the size, the layer thickness, or the region of each component is exaggerated for simplicity in some cases. Therefore, it is not necessarily limited to the scale.

Further, the terms such as first, second, and third used in this specification are given for avoiding confusion between components, and are not limited numerically. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”.

Further, the voltage refers to a potential difference between two points, and the potential refers to electrostatic energy (electric potential energy) possessed by a unit charge in an electrostatic field at a certain point. However, generally, a potential difference between a potential at a certain point and a reference potential (for example, ground potential) is simply referred to as a potential or a voltage, and the potential and the voltage are often used as synonyms. Therefore, in this specification, unless otherwise specified, the potential may be read as a voltage, or the voltage may be read as a potential.

(Embodiment 1)
In this embodiment, a diode including a transistor including an oxide semiconductor as one embodiment of a nonlinear element will be described with reference to FIGS. 1 to 3 in the case where the transistor is n-type. In the diode described in this embodiment, a gate electrode is connected to a source electrode or a drain electrode of a transistor.

In general, a diode has two terminals, an anode and a cathode. When the potential of the anode is higher than the potential of the cathode, a current flows, that is, a conductive state, and the potential of the anode is higher than the potential of the cathode. When it is low, it has a property that almost no current flows, that is, a non-conductive state (insulated state).

This property of the diode is called a rectification characteristic, and the direction in which the diode is in a conductive state is referred to as the forward direction, and the direction in which the diode is in a non-conductive state is referred to as the reverse direction. The voltage in the forward direction is called a forward voltage or forward bias, and the current in the forward direction is called a forward current. Further, the voltage in the reverse direction is referred to as a reverse voltage, and the current in the reverse direction is referred to as a reverse current.

In the diode illustrated in FIG. 1, the wiring 125 is connected to the third electrode 113 and the third electrode 115, and further to the second electrode 109, and the second electrode 109 is connected to the oxide semiconductor layer 107. It is connected to the first electrode 105. The first electrode 105 is connected to the wiring 131.

1A is a top view of the diode-connected transistor 133, and FIG. 1B corresponds to a cross-sectional view taken along dashed-dotted line AB in FIG. 1A.

As illustrated in FIG. 1B, the first electrode 105, the oxide semiconductor layer 107, and the second electrode 109 are stacked over the insulating layer 103 formed over the substrate 101. A gate insulating layer 111 is provided so as to cover the first electrode 105, the oxide semiconductor layer 107, and the second electrode 109. A third electrode 113 and a third electrode 115 are provided over the gate insulating layer 111. An insulating layer 117 functioning as an interlayer insulating layer is provided over the gate insulating layer 111, the third electrode 113, and the third electrode 115. An opening is formed in the insulating layer 117, and the wiring 131 (see FIG. 1A) connected to the first electrode 105 in the opening, the second electrode 109, the third electrode 113, and the third A wiring 125 connected to the electrode 115 is formed. The first electrode 105 functions as one of a source electrode and a drain electrode of the transistor. The second electrode 109 functions as the other of the source electrode and the drain electrode of the transistor. The third electrode 113 and the third electrode 115 function as gate electrodes of the transistor.

The transistor in this embodiment is a vertical transistor, and the third electrode 113 functioning as a gate electrode and the third electrode 115 are separated from each other, and the first electrode 105 and the oxide semiconductor layer 107 are separated. And the second electrode 109 are opposed to each other.

Note that a transistor is an element having at least three terminals including a gate (gate electrode), a drain (drain electrode or drain region), and a source (source electrode or source region), and a channel between the drain and the source. A formation region is provided, and current can flow through the drain, the channel formation region, and the source. Here, since the source and the drain vary depending on the structure and operating conditions of the transistor, it is difficult to limit which is the source or the drain. Thus, a region functioning as a source and a drain may not be called a source or a drain. In that case, as an example, there are cases where they are respectively referred to as a first terminal and a second terminal. Alternatively, they may be referred to as a first electrode and a second electrode, respectively. Alternatively, they may be referred to as a first area and a second area.

The substrate 101 needs to have at least heat resistance enough to withstand subsequent heat treatment. As the substrate 101, a glass substrate such as barium borosilicate glass or alumino borosilicate glass can be used.

As the glass substrate, a glass substrate having a strain point of 730 ° C. or higher is preferably used when the temperature of the subsequent heat treatment is high. For the glass substrate, for example, a glass material such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass is used. Note that a more practical heat-resistant glass can be obtained by containing more barium oxide (BaO) than boron oxide (B ₂ O ₃ ). For this reason, it is preferable to use a glass substrate containing more BaO than B ₂ O ₃ .

Note that a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used instead of the glass substrate. In addition, crystallized glass or the like can be used.

The insulating layer 103 is formed using an oxide insulating layer such as silicon oxide or silicon oxynitride, or a nitride insulating layer such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide. The insulating layer 103 may have a stacked structure, for example, a stacked structure including one or more of the nitride insulating layers described above from the substrate 101 side and one or more of the oxide insulating layers described above. Can do.

The first electrode 105 and the second electrode 109 are formed of aluminum (Al), chromium (Cr), iron (Fe), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten ( W), yttrium (Y), silver (Ag), or an alloy containing the above elements as a component, an alloy combining the above elements, or the like. One or more materials selected from manganese (Mn), magnesium (Mg), zirconium (Zr), beryllium (Be), and thorium (Th) can be used. The first electrode 105 and the second electrode 109 can have a single-layer structure or a stacked structure including two or more layers. For example, a single layer structure of aluminum containing silicon (Si), a two-layer structure in which a titanium layer is stacked on an aluminum layer, a two-layer structure in which a titanium layer is stacked on a tungsten layer, a titanium layer, and an overlay on the titanium layer And a three-layer structure in which an aluminum layer is stacked and a titanium layer is further formed thereon.

In addition, hillocks and whiskers formed in an aluminum layer such as titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc) are formed on aluminum (Al). It is possible to improve heat resistance by using an aluminum material to which an element for preventing the generation of oxygen is added.

The first electrode 105 and the second electrode 109 may be formed using a conductive metal oxide. Examples of the conductive metal oxide include indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium oxide tin oxide alloy (In ₂ O ₃ —SnO ₂ , abbreviated as ITO), An indium oxide-zinc oxide alloy (In ₂ O ₃ —ZnO) or a metal oxide material containing silicon or silicon oxide can be used.

As the oxide semiconductor layer 107, an In—Sn—Ga—Zn—O-based film that is a quaternary metal oxide, an In—Ga—Zn—O-based film that is a ternary metal oxide, In—Sn, or the like. -Zn-O-based film, In-Al-Zn-O-based film, Sn-Ga-Zn-O-based film, Al-Ga-Zn-O-based film, Sn-Al-Zn-O-based film, and binary In—Zn—O-based film, Sn—Zn—O-based film, Al—Zn—O-based film, Zn—Mg—O-based film, Sn—Mg—O-based film, In—Mg— An oxide semiconductor layer such as an O-based film, an In-Ga-O-based film, an In-O-based film, a Sn-O-based film, or a Zn-O-based film can be used. Further, the oxide semiconductor layer may include SiO ₂ .

For the oxide semiconductor layer 107, a thin film represented by InMO ₃ (ZnO) _m (m> 0) can be used. Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. For example, M includes Ga, Ga and Al, Ga and Mn, or Ga and Co. Among oxide semiconductor layers having a structure represented by InMO ₃ (ZnO) _m (m> 0), an oxide semiconductor having a structure containing Ga as M is referred to as an In—Ga—Zn—O-based oxide semiconductor. The thin film is also referred to as an In—Ga—Zn—O-based film.

In the oxide semiconductor layer 107 used in this embodiment, the concentration of hydrogen contained in the oxide semiconductor layer is 5 × 10 ¹⁹ / cm ³ or less, preferably 5 × 10 ¹⁸ / cm ³ or less, more preferably 5 × 10. ^{It is 17} / cm ³ or less or less than 1 × 10 ¹⁶ / cm ³ , and hydrogen contained in the oxide semiconductor layer is reduced. That is, the oxide semiconductor layer is highly purified so that impurities other than the main component of the oxide semiconductor layer are not included as much as possible. The carrier concentration of the oxide semiconductor layer 107 is less than 1 × 10 ¹² / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ . That is, the carrier concentration of the oxide semiconductor layer is as close to zero as possible. The energy gap is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. Note that the hydrogen concentration in the oxide semiconductor layer may be measured by secondary ion mass spectrometry (SIMS). The carrier concentration can be measured by Hall effect measurement.

The thickness of the oxide semiconductor layer 107 is preferably greater than or equal to 30 nm and less than or equal to 3000 nm. By reducing the thickness of the oxide semiconductor layer 107, the channel length of the transistor can be reduced, so that a transistor with high on-state current and high field-effect mobility can be manufactured. On the other hand, by increasing the thickness of the oxide semiconductor layer 107, which is typically greater than or equal to 100 nm and less than or equal to 3000 nm, a high-power semiconductor device can be manufactured.

The gate insulating layer 111 can be formed using a single layer or a stack of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or aluminum oxide. The portion of the gate insulating layer 111 that is in contact with the oxide semiconductor layer 107 preferably contains oxygen, and is particularly preferably formed using silicon oxide. By using silicon oxide, oxygen can be supplied to the oxide semiconductor layer 107, whereby characteristics can be improved. The thickness of the gate insulating layer 111 is preferably greater than or equal to 50 nm and less than or equal to 500 nm. By reducing the thickness of the gate insulating layer 111, a transistor with high field-effect mobility can be manufactured, and a driver circuit can be manufactured over the same substrate. On the other hand, by increasing the thickness of the gate insulating layer 111, gate leakage current can be reduced.

As the gate insulating layer 111, hafnium silicate (HfSixOy (x> 0, y> 0)), nitrogen-added HfSixOy (x> 0, y> 0), nitrogen-added hafnium aluminate (HfAlxOy ( x> 0, y> 0)), and using a high-k material such as hafnium oxide or yttrium oxide can reduce the gate leakage current. Furthermore, a stacked structure of a high-k material and any one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, and aluminum oxide can be employed.

The third electrode 113 and the third electrode 115 functioning as gate electrodes are elements selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, or alloys containing the above elements as components. An alloy film combined with elements can be used. One or more materials selected from manganese, magnesium, zirconium, and beryllium may be used. The third electrode 113 and the third electrode 115 may have a single-layer structure or a stacked structure including two or more layers. For example, a single layer structure of aluminum containing silicon, a two-layer structure in which a titanium layer is laminated on an aluminum layer, a titanium layer, and a three layer in which an aluminum layer is laminated on the titanium layer and a titanium layer is further formed thereon There are structures. Alternatively, aluminum may be an alloy film or a nitride film in which any one or a combination of elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium is used.

The oxide semiconductor layer according to this embodiment is purified by removing hydrogen, which is an n-type impurity, from the oxide semiconductor layer so that impurities other than the main components of the oxide semiconductor layer are included as much as possible. Intrinsic (i-type) or intrinsic type. That is, it is characterized by not being made i-type by adding impurities, but by removing impurities such as hydrogen, water, hydroxyl group or hydride as much as possible to obtain highly purified i-type (intrinsic semiconductor) or close to it. Yes. By doing so, the Fermi level (Ef) can be brought to the same level as the intrinsic Fermi level (Ei).

As described above, by removing impurities as much as possible, for example, even when the channel width W of the transistor is 1 × 10 ⁴ μm and the channel length is 3 μm, the off current is as low as 10 ⁻¹³ A or less, Further, the subthreshold swing value (S value) is set to 0.1 V / dec. (Gate insulating layer thickness 100 nm) or less.

As described above, the operation of the transistor is improved by increasing the purity so that impurities other than the main component of the oxide semiconductor layer, typically hydrogen, water, hydroxyl, or hydride, are not included as much as possible. can do. In particular, off-state current can be reduced.

By the way, in a lateral transistor in which a channel is formed substantially parallel to a substrate, it is necessary to provide a source and a drain in addition to the channel, and the area occupied by the transistor on the substrate becomes large, which prevents miniaturization. However, in the vertical transistor, since the source, the channel, and the drain are stacked, the occupied area on the substrate surface can be reduced. As a result, the transistor can be miniaturized. Note that this embodiment can be applied to a horizontal transistor if there is no restriction such as miniaturization.

In addition, since the channel length of the vertical transistor can be controlled by the thickness of the oxide semiconductor layer, the transistor with a small channel length can be obtained by reducing the thickness of the oxide semiconductor layer 107. By reducing the channel length, the series resistance of the source, the channel, and the drain can be reduced, so that the on-state current and field-effect mobility of the transistor can be increased. In addition, a transistor including a highly purified oxide semiconductor with a reduced hydrogen concentration has an extremely low off-state current and an insulating state in which almost no current flows when the transistor is off. Therefore, even when the thickness of the oxide semiconductor layer is reduced and the channel length of the vertical transistor is reduced, a transistor with almost no off-state current in a non-conductive state can be obtained.

In this manner, by using a highly purified oxide semiconductor with a reduced hydrogen concentration, it is suitable for high definition, has a high operation speed, can flow a large current when turned on, and hardly flows a current when turned off. A transistor can be manufactured. In this embodiment, a diode is formed using a transistor including a highly purified oxide semiconductor with reduced hydrogen concentration.

Note that the diode of this embodiment is not limited to that shown in FIG. In the diode illustrated in FIG. 1, current flows from the second electrode 109 to the first electrode 105 in the oxide semiconductor layer 107, but as illustrated in FIG. 2, the first electrode 105 flows in the oxide semiconductor layer 107. A current may flow from the first electrode 109 to the second electrode 109.

In the diode illustrated in FIG. 2, the wiring 125 is connected to the third electrode 113 and the third electrode 115, and further connected to the first electrode 105. The first electrode 105 is connected to the second electrode 109 through the oxide semiconductor layer 107. The second electrode 109 is connected to the wiring 129.

In the diode shown in FIG. 2, since the wiring 125 is provided so as not to overlap with other electrodes and the like, it can be operated while suppressing parasitic capacitance generated between the wiring 125 and these electrodes. .

By electrically connecting the source or drain of the transistor including the highly purified oxide semiconductor with reduced hydrogen concentration to the gate, a diode with extremely low reverse current can be obtained. Therefore, a diode in which an avalanche breakdown phenomenon hardly occurs (that is, a high breakdown voltage) can be manufactured.

The work function of the conductive material in contact with the oxide semiconductor layer 107 of the first electrode 105 is φmd, the work function of the conductive material in contact with the oxide semiconductor layer 107 of the second electrode 109 is φms, and the oxide By setting the electron affinity of the semiconductor layer 107 to χ and satisfying Equation 1, the energy barrier at the junction interface between the first electrode 105 and the second electrode 109 and the oxide semiconductor layer 107 can be obtained. The diode can be reduced and particularly excellent in forward current characteristics.
φms ≦ χ ≧ φmd Formula 1

FIG. 3 shows a circuit symbol of a diode using the n-type transistor including an oxide semiconductor (OS) described with reference to FIGS. FIG. 3A is a circuit symbol of a diode using the n-type transistor including the oxide semiconductor (OS) described in FIG. 1, and the second electrode 109 is connected to the third electrode 113 through the wiring 125. And the state connected to the 3rd electrode 115 is shown. When a voltage (positive voltage) higher than that of the first electrode 105 is applied to the second electrode 109, a positive voltage is also applied to the third electrode 113 and the third electrode 115 that function as gate electrodes. Therefore, the transistor 133 is turned on, and a current flows between the first electrode 105 and the second electrode 109.

On the other hand, when a voltage (negative voltage) lower than that of the first electrode 105 is applied to the second electrode 109, the transistor 133 is turned off, so that the first electrode 105 and the second electrode 109 are not connected. Almost no current flows. In this manner, the transistor 133 including a highly purified oxide semiconductor with reduced hydrogen concentration can function as a diode in which the second electrode 109 is an anode and the first electrode 105 is a cathode.

FIG. 3B is a circuit symbol of a diode using the n-type transistor including the oxide semiconductor (OS) described in FIG. 2, and the first electrode 105 is connected to the third electrode 113 through the wiring 125. And the state connected to the 3rd electrode 115 is shown. When a voltage (positive voltage) higher than that of the second electrode 109 is applied to the first electrode 105, a positive voltage is also applied to the third electrode 113 and the third electrode 115 that function as gate electrodes. Therefore, the transistor 133 is turned on, and a current flows between the first electrode 105 and the second electrode 109.

On the other hand, when a voltage (negative voltage) lower than that of the second electrode 109 is applied to the first electrode 105, the transistor 133 is turned off, so that the first electrode 105 and the second electrode 109 are not connected to each other. Almost no current flows. In this manner, the transistor 133 including a highly purified oxide semiconductor with a reduced hydrogen concentration can function as a diode having the first electrode 105 as an anode and the second electrode 109 as a cathode.

By using this embodiment mode, a diode that has excellent rectification characteristics and is unlikely to cause an avalanche breakdown phenomenon (that is, has a high breakdown voltage) can be manufactured. In particular, it is possible to obtain a diode having excellent characteristics during forward bias.

(Embodiment 2)
In this embodiment, a structure in which the rectification characteristics of the diode described in Embodiment 1 are further increased will be described with reference to FIGS.

In the first embodiment, the configuration of a diode having excellent forward characteristics has been described. In the present embodiment, the configuration of a diode having excellent reverse characteristics will be described. By using this embodiment, a diode with a smaller reverse current can be obtained.

Specifically, the relationship between the work function of the conductive material used for the first electrode 105 of the transistor 133, the electron affinity of the oxide semiconductor layer 107, and the work function of the conductive material used for the second electrode 109. By devising the above, the transistor 133 can function as a diode with a smaller reverse current.

Here, an energy barrier at the junction of a metal having a work function φM and an oxide semiconductor having an electron affinity χ will be described with reference to FIG.

FIG. 4A shows a band structure in a thermal equilibrium state when φM is larger than χ, and shows a state where the metal 801 and the oxide semiconductor 802 are bonded at the bonding interface 800. The oxide semiconductor 802 represents an intrinsic semiconductor, and the Fermi level 823 of the oxide semiconductor 802 is located approximately at the center of the conduction band 822 and the valence band 824. The work function φM of the metal 801 is an energy difference between the vacuum level 820 and the Fermi level 821 of the metal 801, and is shown as a work function 803 in the drawing. The electron affinity χ of the oxide semiconductor 802 is an energy difference between the vacuum level 820 and the conduction band 822 of the oxide semiconductor 802, and is shown as an electron affinity 804 in the drawing.

At the junction interface 800, the Fermi level 821 of the metal 801 and the Fermi level 823 of the oxide semiconductor 802 coincide with each other. In addition, the conduction band 822 and the valence band 824 are bent in the vicinity of the junction interface 800 in accordance with the energy difference between φM and χ.

The energy barrier 805 is an energy difference (φM−χ) between the work function 803 (φM) and the electron affinity 804 (χ). In FIG. 4A, the work function 803 (φM) is the electron affinity of the oxide semiconductor 802. Since it is larger than 804 (χ), the energy barrier 805 has a positive value. Therefore, electrons existing in the metal 801 are blocked by the energy barrier 805 and hardly move to the conduction band 822 of the oxide semiconductor 802. That is, it becomes difficult for current to flow.

FIG. 4B shows a band structure in a thermal equilibrium state when φM is smaller than χ. In FIG. 4B, since the work function 803 (φM) is smaller than the electron affinity 804 (χ) of the oxide semiconductor 802, the energy barrier 805 has a negative value. Therefore, electrons present in the metal 801 can easily move to the conduction band 822 of the oxide semiconductor 802. That is, the current easily flows.

Note that in the case where the work function 803 (φM) and the electron affinity 804 (χ) are equal, the energy barrier 805 does not exist; thus, electrons existing in the metal 801 can easily move to the conduction band 822 of the oxide semiconductor 802. Can do. That is, the current easily flows as in the case where the energy barrier 805 has a negative value.

Next, by applying the energy barrier described in FIG. 4A to the transistor 133, a structure of a transistor that effectively reduces a reverse current and realizes a diode with excellent rectification characteristics is illustrated in FIGS. 2 will be described.

In the transistor 133 described with reference to FIG. 1, the second electrode 109 is connected to the third electrode 113 and the third electrode 115. Therefore, the transistor 133 functions as a diode having the second electrode 109 as an anode and the first electrode 105 as a cathode.

In the transistor 133 described in FIG. 2, the first electrode 105 is connected to the third electrode 113 and the third electrode 115. Therefore, the transistor 133 functions as a diode having the first electrode 105 as an anode and the second electrode 109 as a cathode.

Of the first electrode 105 or the second electrode 109, the work function of the conductive material in contact with the oxide semiconductor layer 107 of the electrode serving as the anode is φ md, and among the first electrode 105 or the second electrode 109, The work function of the conductive material in contact with the oxide semiconductor layer 107 of the electrode serving as the cathode is φms, the electron affinity of the oxide semiconductor layer 107 is χ, and these are configured to satisfy Equation 2.
φms> χ ≧ φmd Expression 2

For example, when the electron affinity χ of the oxide semiconductor is 4.3 eV, examples of the conductive material having a work function larger than the electron affinity of the oxide semiconductor include tungsten (W), molybdenum (Mo), and chromium (Cr). Iron (Fe), gold (Au), platinum (Pt), copper (Cu), cobalt (Co), nickel (Ni), beryllium (Be), indium tin oxide (ITO), or the like can be used.

In addition, when the electron affinity χ of the oxide semiconductor is 4.3 eV, examples of the conductive material having a work function equal to or lower than the electron affinity of the oxide semiconductor include titanium (Ti), yttrium (Y), and aluminum (Al). Zirconium (Zr), magnesium (Mg), silver (Ag), manganese (Mn), tantalum (Ta), tantalum nitride, titanium nitride, or the like can be used.

As described in Embodiment 1, the first electrode 105 or the second electrode 109 can have a single-layer structure or a stacked structure including two or more layers. In this case, the layer in contact with the oxide semiconductor may have a relationship satisfying Expression 2. For example, in the case where the first electrode 105 functioning as the cathode has a three-layer structure of molybdenum, aluminum, and titanium, tungsten is used for a layer in contact with the oxide semiconductor, and aluminum is sandwiched between molybdenum and titanium. Since aluminum has a lower resistivity than molybdenum and titanium, the effect of reducing the wiring resistance can be realized. In addition, aluminum migration can be prevented by sandwiching aluminum between molybdenum and titanium.

FIG. 5 shows the device simulation results of the reverse current when the diode described in FIG. 1 is configured to satisfy Equation 1 and when it is configured to satisfy Equation 2. FIG. The device simulation was performed using software “Atlas” manufactured by Silvaco. As a precondition, the distance between the anode and the cathode (the thickness of the oxide semiconductor layer) is 500 nm, the contact area between the anode and the cathode and the oxide semiconductor layer is 1 μm ² (1 μm × 1 μm), and the electron affinity of the oxide semiconductor layer ( χ) was set to 4.3 eV, and the work function (φmd) of the conductive layer serving as the anode was set to 4.3 eV. In addition, the work function (φms) of the conductive layer serving as the cathode was 4.3 eV in the case of the configuration satisfying Equation 1, and 4.7 eV in the case of the configuration satisfying Equation 2. In addition, simulation was performed with a gate insulating layer of a transistor used as a diode having a thickness of 100 nm and a relative dielectric constant of 4.0.

The horizontal axis of FIG. 5 represents the anode-cathode (drain-source) voltage (Vds) during reverse bias. The vertical axis represents the current (Ids) between the anode and cathode (between drain and source). A curve 851 indicates the reverse current-voltage characteristic of the diode configured to satisfy Expression 1, and a curve 852 indicates the reverse current-voltage characteristic of the diode configured to satisfy Expression 2. From FIG. 5, it can be confirmed that both the diodes configured to satisfy Equation 1 and Equation 2 have less reverse current, but the diode configured to satisfy Equation 2 has a smaller reverse current. Can be confirmed.

In this manner, by using a transistor including an oxide semiconductor, the relationship between the electron affinity of the oxide semiconductor and the work function of the electrode material satisfies Equation 2, so that the rectification characteristics are further improved and the avalanche breakdown phenomenon is reduced. A diode that does not easily occur (that is, has a high breakdown voltage) can be manufactured. In particular, a diode with a low reverse current (leakage current) can be obtained.

(Embodiment 3)
In this embodiment, an example of a diode that is one embodiment of a nonlinear element and a structure different from those in Embodiments 1 and 2 will be described with reference to FIGS. In the diode described in this embodiment, a gate electrode is electrically connected to a source electrode or a drain electrode of a transistor.

In the diode illustrated in FIG. 6, the wiring 131 is connected to the first electrode 105 and the third electrode 113, and the wiring 132 is connected to the first electrode 106 and the third electrode 115. The first electrode 105 and the first electrode 106 are connected to the second electrode 109 through the oxide semiconductor layer 107. The second electrode 109 is connected to the wiring 129.

6A is a top view of the diode-connected transistors 141 and 143, and FIG. 6B corresponds to a cross-sectional view taken along dashed-dotted line AB in FIG. 6A.

As illustrated in FIG. 6B, the first electrode 105, the first electrode 106, the oxide semiconductor layer 107, and the second electrode 109 are stacked over the insulating layer 103 formed over the substrate 101. The A gate insulating layer 111 is provided so as to cover the first electrode 105, the first electrode 106, the oxide semiconductor layer 107, and the second electrode 109. A third electrode 113 and a third electrode 115 are provided over the gate insulating layer 111. An insulating layer 117 functioning as an interlayer insulating layer is provided over the gate insulating layer 111, the third electrode 113, and the third electrode 115. An opening is formed in the insulating layer 117, and a wiring 131 connected to the first electrode 105 and the third electrode 113 and a wiring 132 connected to the first electrode 106 and the third electrode 115 in the opening. A wiring 129 connected to the second electrode 109 is formed (see FIG. 6A).

The first electrode 105 functions as one of a source electrode and a drain electrode of the transistor 141. The first electrode 106 functions as one of a source electrode and a drain electrode of the transistor 143. The second electrode 109 functions as the other of the source electrode and the drain electrode of the transistors 141 and 143. The third electrode 113 functions as the gate electrode of the transistor 141. The third electrode 115 functions as a gate electrode of the transistor 143.

In this embodiment mode, the first electrode 105 and the first electrode 106 are separated from each other. Further, the transistor 141 and the transistor 143 are connected in parallel by the second electrode 109 and the wiring 129.

Alternatively, the transistor 141 and the second transistor 143 may be connected in series. In this case, the first electrode 105 functions as one of the source electrode and the drain electrode of the transistor 141 (for example, a source). The second electrode 109 functions as the other of the source electrode and the drain electrode of the transistor 141 (for example, the drain). The third electrode 113 functions as the gate electrode of the transistor 141. The second electrode 109 functions as one of the source electrode and the drain electrode of the transistor 143 (for example, a source). The first electrode 106 functions as the other of the source electrode and the drain electrode of the transistor 143 (for example, the drain). The third electrode 115 functions as a gate electrode of the transistor 143.

That is, the transistor 141 and the second transistor 143 are connected in series by the second electrode 109. In this case, the wiring 129 is not necessarily provided.

As in the first and second embodiments, the transistor 141 and the transistor 143 in this embodiment use oxide semiconductor layers with reduced hydrogen concentration and high purity. Therefore, the operation of the transistor can be improved. In particular, off-state current can be reduced. As a result, a transistor which is suitable for high definition, has a high operation speed, can flow a large current when turned on, and hardly flows a current when turned off can be manufactured.

Note that the diode of this embodiment is not limited to that shown in FIG. In the diode illustrated in FIG. 6, current flows from the first electrode 105 to the second electrode 109 in the oxide semiconductor layer 107, but as illustrated in FIG. 7, the second electrode 109 flows in the oxide semiconductor layer 107. A current may flow from the first electrode 105 to the first electrode 105.

In the diode illustrated in FIG. 7, the wiring 125 is connected to the third electrode 113 and the third electrode 115 and further to the second electrode 109, and the second electrode 109 is connected to the oxide semiconductor layer 107. It is connected to the first electrode 105. The first electrode 105 is connected to the wiring 131 and the wiring 132.

Note that in the diode illustrated in FIG. 7, the wiring 125 is provided so as to overlap with the transistors 141 and 143. However, the present invention is not limited to this, and the wiring 125 does not overlap with the transistors 141 and 143 as in FIG. In the case where the wiring 125 does not overlap with the transistor 141 and the transistor 143, operation can be performed while suppressing parasitic capacitance generated between the wiring 125 and these electrodes.

In this way, by electrically connecting the source electrode or the drain electrode of the transistor to the gate electrode, a diode with extremely low reverse current can be obtained. Accordingly, it is possible to manufacture a diode in which a breakdown phenomenon hardly occurs (that is, a high breakdown voltage).

(Embodiment 4)
In this embodiment, an example of a diode that is one embodiment of a nonlinear element and a structure different from those in Embodiments 1 and 2 will be described with reference to FIGS. In the diode described in this embodiment, a gate is connected to a source electrode or a drain electrode of a transistor.

In the diode illustrated in FIG. 8, the wiring 131 is connected to the first electrode 105 and the third electrode 113. The first electrode 105 is connected to the second electrode 109 through the oxide semiconductor layer 107. The second electrode 109 is connected to the wiring 129.

8A is a top view of the diode-connected transistor 145, and FIG. 8B corresponds to a cross-sectional view taken along dashed-dotted line AB in FIG. 8A.

As illustrated in FIG. 8B, the first electrode 105, the oxide semiconductor layer 107, and the second electrode 109 are stacked over the insulating layer 103 formed over the substrate 101. A gate insulating layer 111 is provided so as to cover the first electrode 105, the oxide semiconductor layer 107, and the second electrode 109. A third electrode 113 is provided over the gate insulating layer 111. An insulating layer 117 serving as an interlayer insulating layer is provided over the gate insulating layer 111 and the third electrode 113.
An opening is formed in the insulating layer 117, and the third electrode 113 and the wiring 131 are connected to the opening. In addition, an opening is formed in the insulating layer 117 and the gate insulating layer 111, and the first electrode 105 and the wiring 131 are connected to each other in the opening, and the second electrode 109 and the wiring are connected in different openings. 129 is connected. (See FIG. 8A).

The first electrode 105 functions as one of a source electrode and a drain electrode of the transistor 145. The second electrode 109 functions as the other of the source electrode and the drain electrode of the transistor 145. The third electrode 113 functions as a gate electrode of the transistor 145.

In this embodiment mode, the third electrode 113 functioning as a gate electrode is annular. By forming the third electrode 113 functioning as a gate electrode into a ring shape, the channel width of the transistor can be increased. Therefore, the on-state current of the transistor can be increased.

As in the first embodiment, the transistor 141 and the transistor 143 in this embodiment use oxide semiconductors with reduced hydrogen concentration and high purity. Therefore, the operation of the transistor can be improved. In particular, off-state current can be reduced. As a result, a transistor which is suitable for high definition, has a high operation speed, can flow a large current when turned on, and hardly flows a current when turned off can be manufactured.

Note that the diode of this embodiment is not limited to that shown in FIG. In the diode illustrated in FIG. 8, current flows from the first electrode 105 to the second electrode 109 in the oxide semiconductor layer 107, but as illustrated in FIG. 9, the second electrode 109 flows in the oxide semiconductor layer 107. A current may flow from the first electrode 105 to the first electrode 105.

In the diode illustrated in FIG. 9, the wiring 129 is connected to the second electrode 109 and the third electrode 113. The second electrode 109 is connected to the first electrode 105 through the oxide semiconductor layer 107. The first electrode 105 is connected to the wiring 131.

By electrically connecting the source electrode or the drain electrode of such a transistor to the gate electrode, a diode with very little reverse current can be obtained. Accordingly, it is possible to manufacture a diode in which a breakdown phenomenon hardly occurs (that is, a high breakdown voltage).

(Embodiment 5)
In this embodiment, a manufacturing process of the diode-connected transistor illustrated in FIG. 1 will be described with reference to FIGS.

As shown in FIG. 10A, the insulating layer 103 is formed over the substrate 101, and the first electrode 105 is formed over the insulating layer 103. The first electrode 105 functions as one of a source electrode and a drain electrode of the transistor.

The insulating layer 103 can be formed by a sputtering method, a CVD method, a coating method, or the like.

Note that in the case where the insulating layer 103 is formed by a sputtering method, it is preferable to form the insulating layer 103 while removing hydrogen, water, hydroxyl groups, hydride, or the like remaining in the treatment chamber. This is to prevent the insulating layer 103 from containing hydrogen, water, a hydroxyl group, hydride, or the like. In order to remove hydrogen, water, hydroxyl groups, hydride, or the like remaining in the treatment chamber, an adsorption-type vacuum pump is preferably used. As the adsorption-type vacuum pump, for example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. The exhaust means may be a turbo pump provided with a cold trap. In the treatment chamber exhausted using a cryopump, hydrogen, water, hydroxyl, hydride, or the like is exhausted; therefore, when the insulating layer 103 is formed in the treatment chamber, the concentration of impurities contained in the insulating layer 103 can be reduced.

The sputtering gas used when forming the insulating layer 103 is preferably a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed to a concentration of about ppm and a concentration of about ppb.

The sputtering method includes an RF sputtering method using a high frequency power source as a sputtering power source, a DC sputtering method using a direct current power source, and a pulse DC sputtering method for applying a bias in a pulsed manner. The RF sputtering method is mainly used when an insulating layer is formed, and the DC sputtering method is mainly used when a metal film is formed.

There is also a multi-source sputtering apparatus in which a plurality of targets of different materials can be installed. The multi-source sputtering apparatus can be formed by stacking films of different materials in the same chamber, or by simultaneously discharging a plurality of types of materials in the same chamber.

Further, there are a sputtering apparatus using a magnetron sputtering method having a magnet mechanism inside a chamber, and a sputtering apparatus using an ECR sputtering method using plasma generated using microwaves without using glow discharge.

In addition, as a sputtering method, a reactive sputtering method in which a target material and a sputtering gas component are chemically reacted during film formation to form a compound thin film thereof, or a bias sputtering method in which a voltage is applied to the substrate during film formation is used. You can also

In the sputtering of this specification, the above-described sputtering apparatus and sputtering method can be used as appropriate.

In this embodiment mode, the substrate 101 is transferred to the treatment chamber, a sputtering gas containing high-purity oxygen from which hydrogen, water, a hydroxyl group, hydride, or the like is removed is introduced, and an insulating layer is formed on the substrate 101 using a silicon target. As 103, silicon oxide is formed. Note that the substrate 101 may be heated when the insulating layer 103 is formed.

For example, quartz (preferably synthetic quartz) is used, the substrate temperature is 100 ° C., the distance between the substrate and the target (distance between TS) is 60 mm, the pressure is 0.4 Pa, the high-frequency power supply power is 1.5 kW, oxygen and argon. Silicon oxide is formed by an RF sputtering method in an atmosphere (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1: 1). The film thickness is preferably 100 nm, for example. Note that a silicon target can be used instead of quartz (preferably synthetic quartz). Note that oxygen or a mixed gas of oxygen and argon is used as a sputtering gas.

In the case where the insulating layer 103 is formed in a stacked structure, for example, nitridation is performed using a sputtering target containing high-purity nitrogen from which hydrogen, water, a hydroxyl group, hydride, or the like is removed between a silicon oxide and a substrate and a silicon target. Silicon is formed. Also in this case, it is preferable to form silicon nitride while removing hydrogen, water, hydroxyl group, hydride, or the like remaining in the treatment chamber, as in the case of silicon oxide. Note that in this step, the substrate 101 may be heated.

In the case where silicon nitride and silicon oxide are stacked as the insulating layer 103, silicon nitride and silicon oxide can be formed in the same treatment chamber using a common silicon target. First, a sputtering gas containing nitrogen is introduced, silicon nitride is formed using a silicon target mounted in the processing chamber, and then silicon oxide is formed using the same silicon target by switching to a sputtering gas containing oxygen. . Since silicon nitride and silicon oxide can be continuously formed without being exposed to the air, it is possible to prevent impurities such as hydrogen, water, a hydroxyl group, or hydride from adsorbing to the silicon nitride surface.

For the first electrode 105, a conductive layer is formed over the substrate 101 by a sputtering method, a CVD method, or a vacuum evaporation method, a resist mask is formed over the conductive layer by a photolithography process, and the first electrode 105 is conductive using the resist mask. The layer can be formed by etching. Alternatively, the number of steps can be reduced by forming the first electrode 105 by a printing method or an inkjet method without using a photolithography step. Note that a tapered end portion of the first electrode 105 is preferable because coverage with a gate insulating layer formed later is improved. By setting the angle formed between the end portion of the first electrode 105 and the insulating layer 103 to 30 ° to 60 ° (preferably 40 ° to 50 °), the coverage of a gate insulating layer to be formed later is increased. Can be improved.

In this embodiment, as the conductive layer to be the first electrode 105, a titanium layer with a thickness of 50 nm is formed by a sputtering method, an aluminum layer with a thickness of 100 nm is formed, and a titanium layer with a thickness of 50 nm is formed. Next, etching is performed using a resist mask formed by a photolithography process, so that the first electrode 105 is formed. Note that the material of the first electrode 105 in contact with the oxide semiconductor layer to be formed later can be selected in consideration of the relationship between the electron affinity and the work function described in Embodiment 2.

Next, as illustrated in FIG. 10B, the oxide semiconductor layer 107 and the second electrode 109 are formed over the first electrode 105. The oxide semiconductor layer 107 functions as a channel formation region of the transistor, and the second electrode 109 functions as the other of the source electrode and the drain electrode of the transistor.

Here, a method for manufacturing the oxide semiconductor layer 107 and the second electrode 109 is described.

An oxide semiconductor layer is formed over the substrate 101 and the first electrode 105 by a sputtering method. Next, a conductive layer is formed over the oxide semiconductor layer.

In order to prevent hydrogen from being contained in the oxide semiconductor layer 107 as much as possible, as a pretreatment, the substrate 101 over which the first electrode 105 is formed is preliminarily heated and adsorbed to the substrate 101 in a preheating chamber of a sputtering apparatus. It is preferable that impurities such as hydrogen, water, hydroxyl group or hydride are desorbed and exhausted. Note that a cryopump is preferable as an exhaustion unit provided in the preheating chamber. Note that this preheating treatment can be omitted. This preheating may be performed on the substrate 101 before the formation of the gate insulating layer 111 to be formed later, or may be performed on the substrate 101 before the formation of the third electrode 113 and the third electrode 115 to be formed later. .

Note that before the oxide semiconductor layer is formed by a sputtering method, reverse sputtering that generates plasma by introducing argon gas is performed to remove dust or an oxide layer attached to the surface of the first electrode 105. Thus, resistance at the interface between the first electrode 105 and the oxide semiconductor layer can be reduced, which is preferable. Reverse sputtering is a method of modifying the surface by forming a plasma near the substrate by applying a voltage using a high frequency power source on the substrate side in an argon atmosphere without applying a voltage to the target side. Note that nitrogen, helium, or the like may be used instead of the argon atmosphere.

In this embodiment, the oxide semiconductor layer is formed by a sputtering method using an In—Ga—Zn—O-based metal oxide target. The oxide semiconductor layer can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. In the case of using a sputtering method, a target containing 2 wt% or more and 10 wt% or less of SiO ₂ may be used.

As a sputtering gas used for forming the oxide semiconductor layer, a high-purity gas from which impurities such as hydrogen, water, a hydroxyl group, or hydride are removed to a concentration of about ppm and a concentration of ppb is preferably used.

As a target for forming the oxide semiconductor layer by a sputtering method, a metal oxide target containing zinc oxide as a main component can be used. As another example of the metal oxide target, a metal oxide target containing In, Ga, and Zn (composition ratio: In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 1 [mol Number ratio], In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 2 [mol number ratio]). As a metal oxide target containing In, Ga, and Zn, In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 2: 2: 1 [molar ratio], or In ₂ O ₃ : Ga ₂ O ₃ : A target having a composition ratio of ZnO = 1: 1: 4 [molar ratio] can also be used. The filling rate of the metal oxide target is 90% to 100%, preferably 95% to 99.9%. An oxide semiconductor formed using a metal oxide target with a high filling rate becomes a dense film.

A substrate is held in a processing chamber held under reduced pressure, and while removing moisture remaining in the processing chamber, a sputtering gas from which hydrogen, water, hydroxyl group, hydride, or the like is removed is introduced, and a metal oxide is used as a target. An oxide semiconductor layer is formed over the substrate 101. In order to remove hydrogen, water, hydroxyl groups, hydride, or the like remaining in the treatment chamber, an adsorption-type vacuum pump is preferably used. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. The exhaust means may be a turbo pump provided with a cold trap. In the treatment chamber exhausted using a cryopump, for example, hydrogen, water, a hydroxyl group, a hydride, or the like (more preferably, a compound including a carbon atom) is exhausted, so the concentration of impurities contained in the oxide semiconductor layer Can be reduced. Alternatively, the oxide semiconductor layer may be formed while the substrate is heated.

In this embodiment, as an example of the deposition conditions of the oxide semiconductor layer, the substrate temperature is room temperature, the distance between the substrate and the target is 110 mm, the pressure is 0.4 Pa, the direct current (DC) power supply power is 0.5 kW, oxygen, Conditions under an atmosphere of argon (oxygen flow rate 15 sccm: argon flow rate 30 sccm) are applied. Note that a pulsed direct current (DC) power source is preferable because powder substances (particles and dust) generated during film formation can be reduced and the film thickness can be uniform. The oxide semiconductor layer is preferably 30 nm or more. The appropriate thickness differs depending on the oxide semiconductor layer material to be applied, and the thickness may be selected as appropriate depending on the material.

Note that as the sputtering method for forming the oxide semiconductor layer, the sputtering method described for the insulating layer 103 can be used as appropriate.

For the conductive layer to be the second electrode 109, the material and method of the first electrode 105 can be used as appropriate. As described in Embodiment 2, the first electrode 105 and the second electrode 109 can be different materials depending on the work function of the material used and the electron affinity of the oxide semiconductor layer. Here, as a conductive layer to be the second electrode 109, a titanium layer with a thickness of 50 nm, an aluminum layer with a thickness of 100 nm, and a titanium layer with a thickness of 50 nm are sequentially stacked.

Next, a resist mask is formed over the conductive layer by a photolithography step, and the conductive layer to be the second electrode 109 and the oxide semiconductor layer to be the oxide semiconductor layer 107 are etched using the resist mask. The second electrode 109 and the oxide semiconductor layer 107 are formed. Note that the number of steps can be reduced by forming a resist mask using an inkjet method instead of a resist mask formed by a photolithography process. By the etching, the angle formed between the end portion of the second electrode 109 and the oxide semiconductor layer 107 and the first electrode 105 is set to 30 ° to 60 ° (preferably 40 ° to 50 °). Therefore, it is preferable because coverage with a gate insulating layer formed later can be improved.

Note that the etching of the conductive layer and the oxide semiconductor layer here may be dry etching or wet etching, or both may be used. In order to form the oxide semiconductor layer 107 and the second electrode 109 having desired shapes, etching conditions (such as an etchant, etching time, and temperature) are adjusted as appropriate depending on the material.

Note that in the case where the etching rate of the conductive layer and the oxide semiconductor layer to be the second electrode 109 is different from that of the first electrode 105, the etching rate of the first electrode 105 is low and the second electrode 109 is formed. Conditions under which the etching rate of the conductive layer and the oxide semiconductor layer are high are selected. Alternatively, after the etching rate of the oxide semiconductor layer is low and the conductive layer to be the second electrode 109 is selected to have a high etching rate, the conductive layer to be the second electrode 109 is etched, and then the first electrode A condition where the etching rate of 105 is low and the etching rate of the oxide semiconductor layer is high is selected.

As an etchant for wet-etching the oxide semiconductor layer, a mixed solution of phosphoric acid, acetic acid, and nitric acid, ammonia perwater (31 wt% hydrogen peroxide solution: 28 wt% ammonia water: water = 5: 2: 2 volume ratio) ) Etc. can be used. Moreover, ITO-07N (manufactured by Kanto Chemical Co., Inc.) may be used.

In addition, the etchant after the wet etching is removed by cleaning together with the etched material. The waste solution of the etching solution containing the removed material may be purified and the contained material may be reused. By recovering and reusing materials such as indium contained in the oxide semiconductor from the waste liquid after the etching, resources can be effectively used and costs can be reduced.

An etching gas used for dry etching is a gas containing chlorine (chlorine-based gas such as chlorine (Cl ₂ ), boron trichloride (BCl ₃ ), silicon tetrachloride (SiCl ₄ ), carbon tetrachloride (CCl ₄ ). Etc.) is preferable.

Gas containing fluorine (fluorine-based gas such as carbon tetrafluoride (CF ₄ ), sulfur hexafluoride (SF ₆ ), nitrogen trifluoride (NF ₃ ), trifluoromethane (CHF ₃ ), etc.), bromide Hydrogen (HBr), oxygen (O ₂ ), a gas obtained by adding a rare gas such as helium (He) or argon (Ar) to these gases, or the like can be used.

As the dry etching method, a parallel plate RIE (Reactive Ion Etching) method or an ICP (Inductively Coupled Plasma) etching method can be used. Etching conditions (such as the amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, and the electrode temperature on the substrate side) are adjusted as appropriate so that the desired processed shape can be etched.

In this embodiment, ammonia peroxide is used as an etchant and the conductive layer to be the second electrode 109 is etched, and then the oxide semiconductor layer is etched with a mixed solution of phosphoric acid, acetic acid, and nitric acid. A semiconductor layer 107 is formed.

Next, in this embodiment, first heat treatment is performed. The temperature of the first heat treatment is 400 ° C. or higher and 750 ° C. or lower, preferably 400 ° C. or higher and lower than the strain point of the substrate. Here, after the substrate is introduced into an electric furnace which is one of heat treatment apparatuses, the oxide semiconductor layer is subjected to heat treatment at 450 ° C. for one hour in an inert gas atmosphere such as nitrogen or a rare gas. By preventing exposure to the atmosphere by preventing entry of hydrogen, water, hydroxyl groups, hydrides, etc. into the oxide semiconductor layer, the hydrogen concentration is reduced and the purity is increased, and i-type or substantially i-type is obtained. Thus obtained oxide semiconductor layer can be obtained. That is, at least one of dehydration and dehydrogenation of the oxide semiconductor layer 107 can be performed by the first heat treatment.

Note that in the first heat treatment, it is preferable that hydrogen, water, a hydroxyl group, hydride, or the like be not contained in nitrogen or a rare gas such as helium, neon, or argon. Alternatively, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm). Or less, preferably 0.1 ppm or less).

Further, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized to be a microcrystalline film or a polycrystalline film. For example, the oxide semiconductor layer may be a microcrystalline oxide semiconductor layer with a crystallization rate of 90% or more, or 80% or more. Further, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, an amorphous oxide semiconductor layer which does not include a crystal component may be formed. In some cases, the amorphous oxide semiconductor layer includes an oxide semiconductor layer in which a microcrystalline portion (a particle size of 1 nm to 20 nm (typically 2 nm to 4 nm)) is mixed.

The first heat treatment of the oxide semiconductor layer may be performed on the oxide semiconductor layer before the island-shaped oxide semiconductor layer is formed. In that case, after the first heat treatment, the substrate is taken out of the heating apparatus and a photolithography process is performed.

Note that heat treatment that exerts an effect of dehydration and dehydrogenation on the oxide semiconductor layer is performed after the oxide semiconductor layer is formed, the conductive layer to be the second electrode is stacked over the oxide semiconductor layer, This may be performed after the gate insulating layer is formed over the first electrode, the oxide semiconductor layer, and the second electrode, or after the gate electrode is formed.

Next, as illustrated in FIG. 10C, the gate insulating layer 111 is formed over the first electrode 105, the oxide semiconductor layer 107, and the second electrode 109.

An oxide semiconductor layer that is i-type or substantially i-type by removing impurities (a highly purified oxide semiconductor layer with reduced hydrogen concentration) is extremely sensitive to interface states and interface charges. Therefore, the interface with the gate insulating layer 111 is important. Therefore, the gate insulating layer 111 in contact with the highly purified oxide semiconductor layer is required to have high quality.

For example, it is preferable because a high-quality insulating layer having a high density and high withstand voltage can be formed by high-density plasma CVD using μ-wave (2.45 GHz). This is because when the high-purity oxide semiconductor layer with a reduced hydrogen concentration is in close contact with the high-quality gate insulating layer, the interface state can be reduced and interface characteristics can be improved.

Needless to say, another film formation method such as a sputtering method or a plasma CVD method can be used as long as a high-quality insulating layer can be formed as the gate insulating layer. Alternatively, an insulating layer in which the film quality of the gate insulating layer and the interface characteristics with the oxide semiconductor layer are modified by heat treatment after the formation of the gate insulating layer may be used. In any case, any film can be used as long as it can reduce the interface state density with the oxide semiconductor layer and form a favorable interface as well as the film quality as the gate insulating layer is good.

Further, in the gate bias / thermal stress test (BT test) for 12 hours at 85 ° C., 2 × 10 ⁶ V / cm, when impurities are added to the oxide semiconductor layer, the impurities and the main oxide semiconductor layer The bond with the component is broken by a strong electric field (B: bias) and a high temperature (T: temperature), and the generated dangling bond induces a threshold voltage (Vth) drift.

On the other hand, by removing impurities from the oxide semiconductor layer, particularly hydrogen and water as much as possible, and improving the interface characteristics with the gate insulating layer as described above, a transistor that is stable against the BT test can be obtained. It is possible to get.

By forming the gate insulating layer 111 by a sputtering method, the hydrogen concentration in the gate insulating layer 111 can be reduced. In the case where silicon oxide is formed by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas.

The gate insulating layer 111 can have a structure in which silicon oxide and silicon nitride are stacked from the first electrode 105, the oxide semiconductor layer 107, and the second electrode 109 side. For example, silicon oxide (SiO _x (x> 0)) having a thickness of 5 nm to 300 nm is formed as the first gate insulating layer, and the second gate insulating layer is formed by a sputtering method over the first gate insulating layer. A gate insulating layer having a thickness of 100 nm may be formed by stacking silicon nitride (SiN _y (y> 0)) with a thickness of 50 nm to 200 nm. In this embodiment, silicon oxide with a thickness of 100 nm is formed by RF sputtering in an atmosphere of pressure 0.4 Pa, high-frequency power supply power 1.5 kW, oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1: 1). .

Next, second heat treatment (preferably 200 ° C. to 400 ° C., for example, 250 ° C. to 350 ° C.) may be performed in an inert gas atmosphere or an oxygen gas atmosphere. Note that the second heat treatment may be performed after the third electrode 113 and the third electrode 115 to be formed later, the insulating layer 117, or the wiring 125 is formed. By the heat treatment, oxygen vacancies in the oxide semiconductor layer generated by the first heat treatment are supplemented with oxygen in the gate insulating layer or oxygen in the heat treatment atmosphere, so that the oxide is more i-type. A semiconductor layer can be obtained.

Next, the third electrode 113 and the third electrode 115 functioning as gate electrodes are formed over the gate insulating layer 111.

The third electrode 113 and the third electrode 115 are formed by forming a conductive layer to be the third electrode 113 and the third electrode 115 over the gate insulating layer 111 by a sputtering method, a CVD method, or a vacuum evaporation method. A resist mask can be formed over the conductive layer by a photolithography process, and the conductive layer can be etched using the resist mask. The conductive film to be the third electrode 113 and the third electrode 115 can be formed using a material similar to that of the first electrode 105.

In this embodiment, after a titanium layer with a thickness of 150 nm is formed by a sputtering method, the third electrode 113 and the third electrode 115 are formed by etching using a resist mask formed by a photolithography process.

Through the above steps, the transistor 133 including the highly purified oxide semiconductor layer 107 with reduced hydrogen concentration can be formed.

Next, as illustrated in FIG. 10D, after an insulating layer 117 is formed over the gate insulating layer 111, the third electrode 113, and the third electrode 115, the contact hole 119, the contact hole 121, and the contact hole are formed. 123 is formed.

As the insulating layer 117, an oxide insulating layer such as silicon oxide, silicon oxynitride, aluminum oxide, or aluminum oxynitride, or a nitride insulating layer such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide is used. Alternatively, a stack of an oxide insulating layer and a nitride insulating layer can be used.

The insulating layer 117 is formed by a sputtering method, a CVD method, or the like. Note that in the case where the insulating layer 117 is formed by a sputtering method, the substrate 101 is heated to a temperature of 100 ° C. to 400 ° C., and a sputtering gas containing high-purity nitrogen from which hydrogen, water, hydroxyl, hydride, or the like is removed is introduced. The insulating layer may be formed using a silicon target. Even in this case, it is preferable to form the insulating layer while removing hydrogen, water, hydroxyl groups, hydride, or the like remaining in the treatment chamber.

Note that after the insulating layer 117 is formed, heat treatment may be performed in the air at 100 ° C to 200 ° C for 1 hour to 30 hours. Through this heat treatment, a normally-off transistor can be obtained. Therefore, the reliability of the semiconductor device can be improved.

For the contact hole 119, the contact hole 121, and the contact hole 123, a resist mask is formed by a photolithography process, and selective etching is performed to remove part of the gate insulating layer 111 and the insulating layer 117. A contact hole 119, a contact hole 121, and a contact hole 123 that reach the electrode 109, the third electrode 113, and the third electrode 115 are formed. Although not shown in FIG. 10, part of the gate insulating layer 111 and the insulating layer 117 is removed, and a contact hole reaching the first electrode 105 is also formed (see FIG. 1).

Next, a conductive layer is formed over the gate insulating layer 111, the insulating layer 117, the contact hole 119, the contact hole 121, and the contact hole 123, and then etched using a resist mask formed by a photolithography process, so that the wiring 125 is formed. The wiring 131 (not shown in FIG. 10) is formed. Note that the resist mask may be formed by an inkjet method. When the resist mask is formed by an inkjet method, a photomask is not used, so that manufacturing costs can be reduced.

The wiring 125 and the wiring 131 can be formed in a manner similar to that of the first electrode 105.

Note that a planarization insulating layer for planarization may be provided between the third electrode 113 and the third electrode 115, the wiring 125, and the wiring 131. As a typical example of the planarization insulating layer, an organic material having heat resistance such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, or epoxy resin can be used. In addition to the above organic materials, there are low dielectric constant materials (low-k materials), siloxane-based resins, PSG (phosphorus glass), BPSG (phosphorus boron glass), and the like. Note that the planarization insulating layer may be formed by stacking a plurality of insulating layers formed using these materials.

Note that the siloxane-based resin corresponds to a resin including a Si—O—Si bond formed using a siloxane-based material as a starting material. Siloxane resins may use organic groups (for example, alkyl groups and aryl groups) and fluoro groups as substituents. The organic group may have a fluoro group.

The formation method of the planarization insulating layer is not particularly limited, and according to the material, sputtering method, SOG method, spin coating, dip, spray coating, droplet discharge method (ink jet method, screen printing, offset printing, etc.), A doctor knife, roll coater, curtain coater, knife coater or the like can be used.

As described above, the concentration of hydrogen in the oxide semiconductor layer can be reduced and the oxide semiconductor layer can be highly purified. Accordingly, stabilization of the oxide semiconductor layer can be achieved. In addition, an oxide semiconductor layer with an extremely small number of minority carriers and a wide band gap can be formed by heat treatment at a glass transition temperature or lower. Thus, a transistor can be manufactured using a large-area substrate, so that mass productivity can be improved. In addition, by using a highly purified oxide semiconductor layer with reduced hydrogen concentration, it is suitable for high definition, has a high operation speed, can flow a large current when turned on, and hardly flows a current when turned off. A transistor can be manufactured.

By connecting the source electrode or the drain electrode of the transistor to the gate electrode in this manner, a diode with very little reverse current can be obtained. Accordingly, it is possible to manufacture a diode in which a breakdown phenomenon hardly occurs (that is, a high breakdown voltage).

Note that a halogen element (eg, fluorine or chlorine) is included in an insulating layer provided in contact with the oxide semiconductor layer, or plasma treatment is performed in a gas atmosphere containing a halogen element with the oxide semiconductor layer exposed. A halogen element is included in the oxide semiconductor layer, and hydrogen, moisture, a hydroxyl group, or a hydride (also referred to as a hydrogen compound) that can exist at the interface with the oxide semiconductor layer or the insulating layer provided in contact with the oxide semiconductor layer. ) And other impurities may be excluded. In the case where a halogen element is contained in the insulating layer, the halogen element concentration in the insulating layer may be about 5 × 10 ¹⁸ atoms / cm ³ or more and about 1 × 10 ²⁰ atoms / cm ³ or less.

Note that as described above, a halogen element is included in the oxide semiconductor layer or at the interface between the oxide semiconductor layer and the insulating layer in contact with the oxide semiconductor layer, and the insulating layer provided in contact with the oxide semiconductor layer is an oxide insulating layer. In some cases, the oxide insulating layer that is not in contact with the oxide semiconductor layer is preferably covered with a nitride insulating layer. That is, silicon nitride or the like may be provided in contact with the oxide insulating layer in contact with the oxide semiconductor layer. With such a structure, impurities such as hydrogen, moisture, a hydroxyl group, or hydride can be prevented from entering the oxide insulating layer.

Note that the diodes shown in FIGS. 2 and 6 to 9 can be formed similarly.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 6)
In this embodiment, a diode-connected transistor including an oxide semiconductor layer which is different from that in Embodiment 5 and a manufacturing method thereof will be described with reference to FIGS.

As in Embodiment 5, as illustrated in FIG. 10A, the insulating layer 103 and the first electrode 105 are formed over the substrate 101. Next, as illustrated in FIG. 10B, the oxide semiconductor layer 107 and the second electrode 109 are formed over the first electrode 105.

Next, first heat treatment is performed. The first heat treatment in this embodiment is different from the first heat treatment in the above embodiment, and crystal grains are formed on the surface as shown in FIG. 11A by the heat treatment. The oxide semiconductor layer 151 to be formed can be formed. In this embodiment, the first heat treatment is performed using an apparatus for heating an object to be processed by at least one of heat conduction and heat radiation from a heating element such as a resistance heating element. Here, the temperature of the heat treatment is preferably 500 ° C. or higher and 700 ° C. or lower, preferably 650 ° C. or higher and 700 ° C. or lower. Note that the upper limit of the heat treatment temperature needs to be within the heat resistance range of the substrate 101. The heat treatment time is preferably 1 minute or more and 10 minutes or less. By applying RTA treatment, heat treatment can be performed in a short time, so that the influence of heat on the substrate 101 can be reduced. That is, the upper limit of the heat treatment temperature can be increased as compared with the case where the heat treatment is performed for a long time. In addition, crystal grains having a predetermined structure can be selectively formed in the vicinity of the surface of the oxide semiconductor layer.

Examples of the heating apparatus that can be used in this embodiment include a rapid thermal annealing (RTA) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus and an LRTA (Lamp Rapid Thermal Anneal) apparatus. The LRTA apparatus is an apparatus that heats an object to be processed by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the gas, an inert gas that does not react with an object to be processed by heat treatment, such as nitrogen or a rare gas such as argon, is used.

For example, as the first heat treatment, the substrate is moved to an inert gas atmosphere such as nitrogen or a rare gas heated to a high temperature of 650 ° C. or higher and 700 ° C. or lower, heated for several minutes, and then in an inert gas heated to a high temperature. GRTA for taking out the substrate from the substrate may be performed. When GRTA is used, high-temperature heat treatment can be performed in a short time.

Note that in the first heat treatment, it is preferable that hydrogen, water, a hydroxyl group, hydride, or the like be not contained in nitrogen or a rare gas such as helium, neon, or argon. Alternatively, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm). Or less, preferably 0.1 ppm or less).

Note that the above heat treatment may be performed at any timing after the oxide semiconductor layer 107 is formed; however, in order to promote dehydration or dehydrogenation, the surface of the oxide semiconductor layer 107 is used. It is preferable to perform this before providing other components. Further, the above heat treatment is not limited to once, and may be performed a plurality of times.

Here, an enlarged view of the chain line portion 153 in FIG. 11A is shown in FIG.

The oxide semiconductor layer 151 includes an amorphous region 155 mainly composed of amorphous material and crystal grains 157 formed on the surface of the oxide semiconductor layer 151. The crystal grains 157 are formed in a region (near the surface) whose distance (depth) from the surface is up to 20 nm. However, this is not the case when the thickness of the oxide semiconductor layer 151 is increased. For example, in the case where the thickness of the oxide semiconductor layer 151 is 200 nm or more, “the vicinity of the surface (near the surface)” means that the distance (depth) from the surface is 10% of the thickness of the oxide semiconductor layer. An area that is:

Here, the amorphous region 155 mainly includes an amorphous oxide semiconductor layer. Note that “main” means, for example, a state that occupies 50% or more, and in this case, an amorphous oxide semiconductor layer occupies 50% or more by volume% (or weight%). To do. That is, in addition to the amorphous oxide semiconductor layer, a crystal of the oxide semiconductor layer may be included, and the content is preferably less than 50% by volume (or weight%). It need not be limited to a range.

In the case where an In—Ga—Zn—O-based oxide semiconductor is used as a material for the oxide semiconductor layer, the amorphous region 155 has a Zn content (atomic%) of In or Ga. It is preferable that the amount is less than the amount (atomic%). This is because such a composition makes it easy to form crystal grains 157 having a predetermined composition.

After that, as in Embodiment 5, a transistor is manufactured by forming a gate insulating layer and a third electrode functioning as a gate electrode.

Since the surface of the oxide semiconductor layer 151 is in contact with the gate insulating layer, a channel is formed. By having crystal grains in a region to be a channel, resistance between the source, the channel, and the drain is reduced, and carrier mobility is increased. Thus, the field-effect mobility of the transistor including the oxide semiconductor layer 151 is increased, and favorable electrical characteristics can be realized.

Further, since the crystal grain 157 is more stable than the amorphous region 155, the crystal grain 157 is included in the vicinity of the surface of the oxide semiconductor layer 151, so that impurities (eg, hydrogen, water, hydroxyl group) are included in the amorphous region 155. Or hydride or the like) can be reduced. Therefore, the reliability of the oxide semiconductor layer 151 can be improved.

Through the above steps, the concentration of hydrogen in the oxide semiconductor layer can be reduced and the oxide semiconductor layer can be highly purified. Accordingly, stabilization of the oxide semiconductor layer can be achieved. In addition, an oxide semiconductor layer with an extremely small number of minority carriers and a wide band gap can be formed by heat treatment at a glass transition temperature or lower. Thus, a transistor can be manufactured using a large-area substrate, so that mass productivity can be improved. In addition, by using a highly purified oxide semiconductor layer with reduced hydrogen concentration, it is suitable for high definition, has a high operation speed, can flow a large current when turned on, and hardly flows a current when turned off. A transistor can be manufactured.

In this manner, by electrically connecting one of the source electrode and the drain electrode of the transistor to the gate electrode, a diode with extremely low reverse current can be obtained. Therefore, according to this embodiment, a diode in which a breakdown phenomenon hardly occurs (that is, with a high breakdown voltage) can be manufactured.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 7)
In this embodiment mode, a process for manufacturing the diode-connected transistor illustrated in FIG. 1, which is different from that in Embodiment Mode 5, will be described with reference to FIGS.

As in Embodiment 5, a first electrode 105 is formed over a substrate 101 as illustrated in FIG.

Next, as illustrated in FIG. 10B, the oxide semiconductor layer 107 and the second electrode 109 are formed over the first electrode 105.

Note that before the oxide semiconductor layer is formed by a sputtering method, reverse sputtering that generates plasma by introducing argon gas is performed to remove dust or an oxide layer attached to the surface of the first electrode 105. Thus, resistance at the interface between the first electrode 105 and the oxide semiconductor layer can be reduced, which is preferable. Note that nitrogen, helium, or the like may be used instead of the argon atmosphere.

An oxide semiconductor layer is formed over the substrate 101 and the first electrode 105 by a sputtering method. Next, a conductive layer is formed over the oxide semiconductor layer.

In this embodiment, the oxide semiconductor layer is formed by a sputtering method using an In—Ga—Zn—O-based metal oxide target. In this embodiment mode, the substrate is held in a processing chamber held in a reduced pressure state, and the substrate is heated to room temperature or a temperature lower than 400 ° C. Then, while removing hydrogen, water, hydroxyl group, hydride, or the like remaining in the treatment chamber, a sputtering gas from which hydrogen, water, hydroxyl group, hydride, or the like has been removed is introduced, and the substrate 101 and the first substrate are formed using a metal oxide as a target. An oxide semiconductor layer is formed over one electrode 105. In order to remove hydrogen, water, hydroxyl groups, hydride, or the like remaining in the treatment chamber, an adsorption-type vacuum pump is preferably used. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. The exhaust means may be a turbo pump provided with a cold trap. In the treatment chamber exhausted using a cryopump, for example, hydrogen, water, a hydroxyl group, hydride (more preferably, a compound containing a carbon atom), or the like is exhausted; therefore, the oxide semiconductor layer formed in the treatment chamber The concentration of impurities contained can be reduced. In addition, by performing sputter formation while removing hydrogen, water, hydroxyl groups, hydrides, etc. remaining in the processing chamber by a cryopump, even if the substrate temperature is from room temperature to less than 400 ° C., oxidation such as hydrogen atoms and water is reduced. A physical semiconductor layer can be formed.

In the present embodiment, the film formation conditions are applied under the condition where the distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa, the direct current (DC) power source is 0.5 kW, and the oxygen (oxygen flow rate is 100%). The Note that a pulse direct current (DC) power source is preferable because powder substances (also referred to as particles or dust) generated in film formation can be reduced and the film thickness can be made uniform. The oxide semiconductor layer is preferably 30 nm to 3000 nm. Note that an appropriate thickness differs depending on an oxide semiconductor layer material to be used, and the thickness may be selected as appropriate depending on the material.

Note that as the sputtering method for forming the oxide semiconductor layer, the sputtering method described for the insulating layer 103 can be used as appropriate.

Next, a conductive layer to be the second electrode 109 is formed using the material and method of the first electrode 105. Further, as described in Embodiment Mode 2, the first electrode 105 and the second electrode 109 can be made of different materials depending on the work function of the material to be used.

Next, as in Embodiment 5, the second electrode 109 and the oxide semiconductor layer 107 are formed by etching the conductive layer to be the second electrode 109 and the oxide semiconductor layer to be the oxide semiconductor layer 107. To do. In order to form the oxide semiconductor layer 107 and the second electrode 109 having desired shapes, etching conditions (such as an etchant, etching time, and temperature) are adjusted as appropriate depending on the material.

Next, as illustrated in FIG. 10C, a gate insulating layer 111 is formed over the first electrode 105, the oxide semiconductor layer 107, and the second electrode 109 as in Embodiment 5. The gate insulating layer 111 preferably has favorable interface characteristics with the oxide semiconductor layer 107. By forming the gate insulating layer 111 by high-density plasma CVD using μ waves (2.45 GHz), This is preferable because a high-quality insulating layer having a high density and high withstand voltage can be formed. In addition, as long as a high-quality insulating layer can be formed as the gate insulating layer, other formation methods such as a sputtering method and a plasma CVD method can be applied.

Note that before the gate insulating layer 111 is formed, reverse sputtering may be performed to remove at least a resist residue or the like attached to the surface of the oxide semiconductor layer 107.

In addition, hydrogen, water, a hydroxyl group, or a hydride attached to the surface of the oxide semiconductor layer exposed by plasma treatment using a gas such as N ₂ O, N ₂ , or Ar before the gate insulating layer 111 is formed. Etc. may be removed. Further, plasma treatment may be performed using a mixed gas of oxygen and argon. In the case where plasma treatment is performed, the gate insulating layer 111 in contact with part of the oxide semiconductor layer is preferably formed without exposure to the air.

In order to prevent the gate insulating layer 111 from containing hydrogen, water, a hydroxyl group, hydride, or the like as much as possible, as a pretreatment, the first electrode 105 to the second electrode 109 are used in a preheating chamber of a sputtering apparatus. It is preferable to preheat the substrate 101 formed so as to desorb and exhaust impurities such as hydrogen, water, hydroxyl group, or hydride adsorbed on the substrate 101. Alternatively, after the gate insulating layer 111 is formed, the substrate 101 is preheated in a preheating chamber of a sputtering apparatus, and impurities such as hydrogen, water, hydroxyl, or hydride adsorbed on the substrate 101 can be desorbed and exhausted. preferable. Note that the preheating temperature is 100 ° C. or higher and 400 ° C. or lower, preferably 150 ° C. or higher and 300 ° C. or lower. Note that a cryopump is preferable as an exhaustion unit provided in the preheating chamber. Note that this preheating treatment can be omitted.

The gate insulating layer 111 can have a structure in which silicon oxide and silicon nitride are stacked from the first electrode 105, the oxide semiconductor layer 107, and the second electrode 109 side. For example, silicon oxide (SiO _x (x> 0)) with a thickness of 5 nm to 300 nm is formed as the first gate insulating layer by a sputtering method, and a film as the second gate insulating layer is formed over the first gate insulating layer. A gate insulating layer is formed by stacking silicon nitride (SiN _y (y> 0)) with a thickness of 50 nm to 200 nm.

Next, heat treatment (preferably 200 ° C. to 400 ° C., for example, 250 ° C. to 350 ° C.) may be performed in an inert gas atmosphere or an oxygen gas atmosphere. Note that the second heat treatment may be performed after any of the third electrode 113 and the third electrode 115, the insulating layer 117, the wiring 125, and the wiring 131 that are formed later is formed. By the heat treatment, oxygen vacancies in the oxide semiconductor layer are supplemented with oxygen in the gate insulating layer or oxygen in the heat treatment atmosphere, so that an i-type oxide semiconductor layer can be obtained.

Next, as illustrated in FIG. 10C, as in Embodiment 5, a third electrode 113 and a third electrode 115 which function as gate electrodes are formed over the gate insulating layer 111.

Through the above steps, the transistor 133 including the oxide semiconductor layer 107 with reduced hydrogen concentration can be formed.

When the oxide semiconductor layer is formed as described above, hydrogen concentration in the oxide semiconductor layer can be reduced by removing hydrogen, water, a hydroxyl group, hydride, or the like remaining in the reaction atmosphere. . Accordingly, stabilization of the oxide semiconductor layer can be achieved.

Next, as illustrated in FIG. 10D, as in Embodiment 5, an insulating layer 117 is formed over the gate insulating layer 111, the third electrode 113, and the third electrode 115, and then the contact hole 119 is formed. The contact hole 121 and the contact hole 123 are formed.

Next, as illustrated in FIG. 10E, the wiring 125 and the wiring 131 are formed as in Embodiment 5.

Next, as in Embodiment 5, the insulating layer 117 is formed. Note that after the insulating layer 117 is formed, heat treatment may be performed in the air at 100 ° C. to 200 ° C. for 1 hour to 30 hours as in Embodiment Mode 5. Through this heat treatment, a normally-off transistor can be obtained. Therefore, the reliability of the semiconductor device can be improved.

Note that a planarization insulating layer for planarization may be provided between the third electrode 113 and the third electrode 115 and the wiring 125 and the wiring 131.

When the oxide semiconductor layer is formed as described above, the hydrogen concentration in the oxide semiconductor layer is reduced by removing hydrogen, water, hydroxyl group, hydride, or the like remaining in the reaction atmosphere, and high purity. Can be Accordingly, stabilization of the oxide semiconductor layer can be achieved. In addition, an oxide semiconductor layer with an extremely small number of minority carriers and a wide band gap can be formed by heat treatment at a glass transition temperature or lower. Thus, a transistor can be manufactured using a large-area substrate, so that mass productivity can be improved. In addition, by using a highly purified oxide semiconductor layer with reduced hydrogen concentration, it is suitable for high definition, has a high operation speed, can flow a large current when turned on, and hardly flows a current when turned off. A transistor can be manufactured.

In this way, by electrically connecting the source electrode or the drain electrode of the transistor to the gate electrode, a diode with extremely low reverse current can be obtained. Accordingly, it is possible to manufacture a diode in which a breakdown phenomenon hardly occurs (that is, a high breakdown voltage).

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 8)
The nonlinear element such as a diode described in the above embodiment can be applied to a semiconductor device. An example of the semiconductor device is a display device.

A structure of a display device which is one embodiment of the present invention is described with reference to FIGS. FIG. 12 is a top view of the substrate 200 on which the display device is formed. A pixel portion 201 is formed on the substrate 200. The input terminal 202 and the input terminal 203 supply a signal for displaying an image and power supply power to the pixel circuit formed on the substrate 200.

Note that the display device which is one embodiment of the present invention is not limited to the mode illustrated in FIG. That is, one or both of the scan line driver circuit and the signal line driver circuit may be formed over the substrate 200.

The scanning line side input terminal 202 and the signal line side input terminal 203 formed on the substrate 200 and the pixel portion 201 are connected to each other by wiring extending vertically and horizontally. The protection circuit 207 is connected.

The pixel portion 201 and the input terminal 202 are connected by a wiring 209. The protection circuit 204 is disposed between the pixel portion 201 and the input terminal 202 and is connected to the wiring 209. By providing the protection circuit 204, various semiconductor elements such as a transistor included in the pixel portion 201 can be protected and can be prevented from being deteriorated or destroyed. Note that the wiring 209 indicates one wiring in the drawing, but all of the plurality of wirings provided in parallel with the wiring 209 have the same connection relation as the wiring 209. Note that the wiring 209 functions as a scanning line.

Note that on the scanning line side, not only the protection circuit 204 provided between the input terminal 202 and the pixel portion 201 but also a protection circuit is provided on the opposite side of the input terminal 202 across the pixel portion 201. (Refer to the protection circuit 205 in FIG. 12).

On the other hand, the pixel portion 201 and the input terminal 203 are connected by a wiring 208. The protection circuit 206 is disposed between the pixel portion 201 and the input terminal 203 and is connected to the wiring 208. By providing the protection circuit 206, various semiconductor elements such as a transistor included in the pixel portion 201 can be protected and can be prevented from being deteriorated or destroyed. Note that although the wiring 208 indicates one wiring in the drawing, all of the plurality of wirings provided in parallel with the wiring 208 have the same connection relation as the wiring 208. Note that the wiring 208 functions as a signal line.

Note that the signal line side may be provided not only on the protective circuit 206 provided between the input terminal 203 and the pixel portion 201 but also on the opposite side of the input terminal 203 with the pixel portion 201 interposed therebetween. (See protection circuit 207 in FIG. 12).

Note that the protective circuits 204 to 207 are not necessarily provided. However, at least the protection circuit 204 needs to be provided. This is because an excessive current is generated in the scan line, so that the gate insulating layer of the transistor included in the pixel portion 201 is broken and a large number of point defects can be generated.

Further, by providing not only the protection circuit 204 but also the protection circuit 206, it is possible to prevent an excessive current from being generated in the signal line. Therefore, the reliability is improved and the yield is improved as compared with the case where only the protective circuit 204 is provided. By including the protective circuit 206, it is possible to prevent damage due to static electricity that may occur in a rubbing process after the formation of the transistor.

Furthermore, by including the protection circuit 205 and the protection circuit 207, reliability can be further improved. In addition, the yield can be increased. The protection circuit 205 and the protection circuit 207 are provided on the side opposite to the input terminal 202 and the input terminal 203. Therefore, these contribute to preventing deterioration and destruction of various semiconductor elements that occur during a manufacturing process of a display device (for example, a rubbing process in a manufacturing process of a liquid crystal display device).

In FIG. 12, a signal line driver circuit and a scan line driver circuit formed separately from the substrate 200 are mounted on the substrate 200 by a known method such as a COG method or a TAB method. However, the present invention is not limited to this, and a scanning line driver circuit and a pixel portion may be formed over the substrate 200, and a signal line driver circuit formed separately may be mounted. Alternatively, part of the scan line driver circuit or part of the signal line driver circuit is formed over the substrate 200 together with the pixel portion 201, and the other part of the scan line driver circuit or the other part of the signal line driver circuit is mounted. You may do it. In the case where a part of the scan line driver circuit is provided between the pixel portion 201 and the input terminal 202 on the scan line side, a part of the scan line driver circuit on the substrate 200 and the input terminal 202 on the scan line side. A protection circuit may be provided between the pixel line 201 and the pixel portion 201, or a protection circuit may be provided on both of them. In the case where a part of the signal line driver circuit is provided between the pixel portion 201 and the input terminal 203 on the signal line side, the input terminal 203 on the signal line side and the signal line driver circuit on the substrate 200 A protection circuit may be provided between a part thereof, a protection circuit may be provided between a part of the signal line driver circuit and the pixel portion 201, or a protection circuit may be provided on both of them. . That is, since there are various forms of the drive circuit, the number and place of the protection circuit are determined in accordance with the form.

Next, an example of a specific circuit configuration of the protection circuit used for the protection circuits 204 to 207 in FIG. 12 will be described with reference to FIG. In the following description, only the case where an n-type transistor is provided will be described.

The protection circuit illustrated in FIG. 13A includes a protection diode 211 to a protection diode 214 using a plurality of transistors. In the protection diode 211, an n-type transistor 211a and an n-type transistor 211b each including an oxide semiconductor (OS) are connected in series. One of the source electrode and the drain electrode of the n-type transistor 211a is connected to the gate electrodes of the n-type transistor 211a and the n-type transistor 211b, and is kept at the potential V _ss . The other of the source electrode and the drain electrode of the n-type transistor 211a is connected to one of the source electrode and the drain electrode of the n-type transistor 211b. The other of the source electrode and the drain electrode of the n-type transistor 211b is connected to the protection diode 212. Similarly to the protection diode 211, the other protection diodes 212 to 214 each have a plurality of transistors connected in series, and one ends of the plurality of transistors connected in series are gates of the plurality of transistors. It is connected to the electrode.

Note that the number and polarity of the transistors included in each of the protective diodes 211 to 214 are not limited to the structure illustrated in FIG. For example, the protection diode 211 may be configured by three transistors connected in series.

The protective diodes 211 to 214 are sequentially connected in series, and the protective diode 212 and the protective diode 213 are connected to the wiring 215. Note that the wiring 215 is electrically connected to a semiconductor element to be protected. Note that the wiring connected to the wiring 215 is not limited to the wiring between the protection diode 212 and the protection diode 213. That is, the wiring 215 may be connected between the protection diode 211 and the protection diode 212, or may be connected between the protection diode 213 and the protection diode 214.

One end of the protective diode 214 is kept at the power supply potential V _dd . In addition, each of the protection diodes 211 to 214 is connected so that a reverse bias voltage is applied.

A protection circuit illustrated in FIG. 13B includes a protection diode 220, a protection diode 221, a capacitor 222, a capacitor 223, and a resistor 224. Resistance element 224 is a two-terminal resistor, its one end is potential _{V in} is supplied from the wiring 225, the other end potential _{V ss} is supplied. Resistance element 224 is provided to the potential of the wiring 225 when the potential V _in is not supplied to the V _ss, the resistance value is set to be sufficiently larger than the wiring resistance of the wiring 225 . The protection diode 220 and the protection diode 221 are diode-connected n-type transistors.

Note that the protection diode shown in FIG. 13 may be a diode in which a plurality of transistors are further connected in series.

Here, consider the case where the protection circuit shown in FIG. 13 operates. At this time, in the source and drain electrodes of the protection diodes 211, 212, 221, 230, 231, 234, and 235, the side held at the potential V _ss is the drain electrode. The other is a source electrode. Of the source and drain electrodes of the protection diodes 213, 214, 220, 232, 233, 236, and 237, the side held at the potential V _dd is the source electrode, and the other is the drain electrode. Further, the threshold voltage of the transistor constituting the protection diode is denoted as _Vth .

The protective diode 211,212,221,230,231,234,235 takes a reverse bias voltage when the potential _{V in} is higher than the potential _{V ss,} hardly current flows. On the other hand, the protection diode 213,214,220,232,233,236,237, the potential _{V in} it takes a reverse bias voltage when lower than the potential _{V dd,} current does not easily flow.

Here, the operation of the protection circuit potential V _out is generally provided so as to be between the potential V _ss and the potential V _dd.

First, consider the case where the potential _{V in} is higher than the potential _{V dd.} If the potential _{V in} is higher than the potential _{V dd,} when the potential difference _{V gs = V in -V dd>} V th between the gate electrode and the source electrode of the protection diode 213,214,220,232,233,236,237 The n-type transistor is turned on. Here, it is assumed the case where V _in is abnormally high, the n-type transistor is turned on. At this time, the n-type transistors included in the protection diodes 211, 212, 221, 230, 231, 234, and 235 are turned off. Then, the potentials of the wirings 215, 225, 239A, and 239B become V _dd through the protective diodes 213, 214, 220, 232, 233, 236, and 237. Therefore, even when the potential _{V in} is unusually higher than the potential _{V dd} due to noise or the like, wiring 215,224,225,239A, the potential of 239B does not become higher than the potential _{V dd.}

On the other hand, the potential _{V in} is lower than the potential _{V ss} is the potential difference _V gs _{= V} ss _{-V in} between the gate electrode and the source electrode of the protection diode 211,212,221,230,231,234,235> When _Vth, the n-type transistor is turned on. Here, it is assumed the case where V _in is unusually low, n-type transistor is turned on. At this time, the n-type transistors included in the protection diodes 213, 214, 220, 232, 233, 236, and 237 are turned off. Then, the potentials of the wirings 215, 225, 239A, and 239B become V _ss through the protective diodes 211, 212, 221, 230, 231, 234, and 235. Therefore, due to noise or the like, even when the potential _{V in} is unusually lower than the potential _{V ss,} wiring 215,225,239A, the potential of 239B does not become lower than the potential _{V ss.} Further, a capacitor 222 and 223 reduce pulsed noise of the input potential V _in, to relieve a steep change in the potential due to noise.

The potential _{V in} is _the case between V ss _{-V th} of _V dd _{+ V th} is, n-type transistor that all of the protection diode has is turned off, the potential _{V in} is input to the potential _{V out.}

By disposing the protection circuit as described above, the potentials of the wirings 215, 225, 239A, and 239B are maintained between the potential V _ss and the potential V _dd . Accordingly, it is possible to prevent the wirings 215, 225, 239A, and 239B from having a potential greatly deviating from this range. That is, the wirings 215, 225, 239A, and 239B are prevented from becoming an abnormally high potential or an abnormally low potential, the subsequent circuit of the protection circuit is prevented from being destroyed or deteriorated, and the subsequent circuit is protected. can do.

Further, as shown in FIG. 13B, by providing a protective circuit having a resistance element 224 at the input terminal, the potentials of all wirings to which a signal is applied when the signal is not input are constant (here Then, the potential V _ss ). In other words, when a signal is not input, it also has a function as a short ring that can short-circuit the wires. Therefore, electrostatic breakdown due to a potential difference generated between the wirings can be prevented. In addition, since the resistance value of the resistance element 224 is sufficiently large with respect to the wiring resistance, it is possible to prevent a signal supplied to the wiring from dropping to the potential V _ss when a signal is input.

Here, as an example, a case where an n-type transistor having a threshold voltage V _th = 0 is used for the protection diode 220 and the protection diode 221 in FIG.

First, when V _in > V _dd , the protection diode 220 is turned on because V _gs = V _in −V _dd > 0. The n-type thin film transistor included in the protection diode 221 is turned off. Therefore, the potential of the wiring 225 is V _dd and V _out = V _dd .

On the other hand, when V _in <V _ss , the n-type thin film transistor included in the protection diode 220 is turned off. The n-type thin film transistor included in the protection diode 221 becomes V _gs = V _ss −V _in > 0 and is turned on. Therefore, the potential of the wiring 225 is V _ss and V _out = V _ss .

As described above, even when V _in <V _ss or V _dd <V _in , the operation can be performed in the range of V _ss <V _out <V _dd . Therefore, even if V _in is excessive or small, it is possible to prevent V _{out from} becoming excessive or excessive. Thus, for example, due to noise or the like, even when the potential V _in is lower than the potential V _ss, the potential of the wiring 225 does not become much lower than the potential V _ss. Further, a capacitor 222 and the capacitor 223 reduce pulsed noise of the input potential V _in, to relieve a steep change in potential.

By arranging the protection circuit as described above, the potential of the wiring 225 is generally kept between the potential V _ss and the potential V _dd . Therefore, the wiring 225 can be prevented from having a potential greatly deviating from this range, and a circuit subsequent to the protection circuit (a circuit in which the input portion is electrically connected to _Vout ) is protected from destruction or deterioration. can do. Further, by providing a protection circuit at the input terminal, the potentials of all wirings to which signals are _supplied can be kept constant (here, the potential V _ss ) when no signal is input. That is, when a signal is not input, it also has a function as a short ring that can short-circuit the wirings. Therefore, electrostatic breakdown due to a potential difference generated between the wirings can be prevented. In addition, since the resistance value of the resistance element 224 is sufficiently large, a decrease in the potential of the signal applied to the wiring 225 can be prevented when a signal is input.

In the protection circuit shown in FIG. 13C, the protection diode 220 and the protection diode 221 are each replaced with two n-type transistors.

Note that although the protection circuit illustrated in FIGS. 13B and 13C uses a diode-connected n-type transistor as the protection diode, the invention is not limited to this.

In addition, the protection circuit illustrated in FIG. 13D includes the protection diodes 230 to 237 and the resistance element 238. The resistance element 238 is connected in series between the wiring 239A and the wiring 239B. Each of the protection diode 230 to the protection diode 233 uses a diode-connected n-type transistor, and each of the protection diode 234 to the protection diode 237 uses a diode-connected n-type transistor.

Protection diode 230 and the protection diode 231 are connected in series, one end of which is kept at the potential _{V ss,} the other end is connected to the wiring 239A potential _{V in.} Protection diode 232 and the protection diode 233 are connected in series, one end of which is kept at the potential _{V dd,} and the other end thereof is connected to the wiring 239A potential _{V in.} The protective diode 234 and the protective diode 235 are connected in series, one end is held at the potential V _ss and the other end is connected to the wiring 239B having the potential V _out . The protective diode 236 and the protective diode 237 are connected in series, one end is held at the potential V _dd and the other end is connected to the wiring 239B having the potential V _out .

In addition, the protection circuit illustrated in FIG. 13E includes a resistance element 240, a resistance element 241, and a protection diode 242. In FIG. 13E, a diode-connected n-type transistor is used as the protective diode 242, but the invention is not limited to this. A plurality of diode-connected transistors may be used. The resistance element 240, the resistance element 241, and the protection diode 242 are connected in series to the wiring 243.

The resistance element 240 and the resistance element 241 can alleviate a rapid change in the potential of the wiring 243 and can prevent deterioration or destruction of the semiconductor element. In addition, the protective diode 242 can prevent a reverse bias current from flowing through the wiring 243 due to potential fluctuation.

Note that the protection circuit illustrated in FIG. 13A can be replaced with the structure illustrated in FIG. FIG. 15F illustrates a structure in which the protection diode 211 and the protection diode 212 illustrated in FIG. 15A are replaced with a protection diode 216, and the protection diode 213 and the protection diode 214 are replaced with a protection diode 217. In particular, since the diode described in the above embodiment has a high withstand voltage, a structure illustrated in FIG. 13F can be used.

Note that in the case where only the resistance element is connected in series to the wiring, rapid fluctuations in the potential of the wiring can be alleviated and deterioration or destruction of the semiconductor element can be prevented. Further, when only the protective diode is connected in series to the wiring, it is possible to prevent a reverse current from flowing through the wiring due to potential fluctuation.

Note that the protective circuit provided in the display device which is one embodiment of the present invention is not limited to the structure illustrated in FIG. 13, and the design can be changed as appropriate as long as the circuit structure functions similarly.

(Embodiment 9)
In this embodiment, an example of a structure of a semiconductor device that enables stable power supply using the diode described in the above embodiment will be described with reference to FIGS. If a voltage higher than expected is applied to the power line, the circuit connected to the power line may be damaged. In the eighth embodiment, a configuration example for protecting a signal line mainly from an excessive voltage that is higher than expected has been described. However, in FIG. 14, in order to prevent a voltage higher than expected from being applied to a power supply line. The example of a structure is shown.

14 (A) is a power supply line 270 for supplying a potential _{V ss,} between the power supply line 271 for supplying a potential _{V dd,} the protection diode 251 to protection with n-type transistor having an oxide semiconductor (OS) It is a circuit diagram which shows the state in which the diode 255 and the protection diode 261 are connected. FIG. 14B is a diagram in which the configuration of the protection diode using the transistor in FIG. 14A is replaced with a circuit symbol of the diode.

As an example, a case will be described in which the potential V _ss is 0 V, the potential V _dd is 10 V, and the potential difference between the power supply line 270 and the power supply line 271 does not exceed 10 V. Here, an n-type transistor having a threshold voltage (V _th ) of 2 V is used as the protective diode.

14A and 14B, the anode side of the protection diode 251 is connected to the power supply line 271 that supplies the potential V _dd . The protective diode 251 includes an n-type transistor including an oxide semiconductor (OS), and one of a source electrode and a drain electrode of the n-type transistor is connected to the power supply line 271 and the gate electrode of the n-type transistor, Functions as an anode. The other of the source electrode and the drain electrode functions as a cathode and is connected to the anode of the protection diode 252.

The protection diode 252 includes an n-type transistor including an oxide semiconductor (OS), and one of the source electrode and the drain electrode of the n-type transistor is connected to the cathode of the protection diode 251 and the gate electrode of the n-type transistor. And function as an anode. The other of the source electrode and the drain electrode functions as a cathode and is connected to the anode of the protection diode 253.

In this manner, the protective diodes 251 to 255 are connected in series, and the cathode of the protective diode 255 is connected to the power supply line 270 that supplies the potential V _ss . That is, five protective diodes are connected in series between the power supply line 270 and the power supply line 271 in the forward bias direction.

Normally, when a voltage is applied in the forward bias direction, a forward current flows through the diode, and the anode and the cathode become conductive. In this embodiment, since five diodes composed of n-type transistors having a threshold voltage (V _th ) of 2V are connected in series, the forward bias does not exceed 10V, which is five times 2V. The power supply line 270 and the power supply line 271 are not electrically connected. However, when the potential difference between the power supply line 270 and the power supply line 271 exceeds 10 V due to noise or the like, the protection diodes 251 to 255 are turned on, and the power supply line 270 and the power supply line 271 are turned on until the potential difference becomes 10 V or less. Becomes a short circuit state. In this way, it is possible to prevent the circuit from being damaged by applying a voltage higher than expected to the circuit through the power supply line.

Further, when the protective diode 261 is connected between the power supply line 270 and the power supply line 271 so as to have a reverse bias, the potential of the power supply line 270 becomes higher than the power supply line 271 due to noise or the like. The power supply line 270 and the power supply line 271 can be short-circuited to release electric charges, thereby preventing damage to a circuit connected to the power supply line.

The protection diode 261 is a transistor including an oxide semiconductor (OS), and is a high-breakdown-voltage diode that hardly causes a breakdown phenomenon even when a large reverse bias is applied. In this embodiment, an example is shown in which one protective diode 261 is arranged between the power supply line 270 and the power supply line 271, but a plurality of protective diodes 261 may be arranged in series. By arranging n protection diodes 261 in series, the voltage applied to each protection diode can be reduced to 1 / n. Therefore, a plurality of diodes arranged in series are more excellent in breakdown voltage characteristics. It can function as a single diode.

A plurality of the protective diodes 251 to 255 and the protective diodes 261 connected in series may be provided in parallel between the power supply line 270 and the power supply line 271. By providing a plurality in parallel, more current can flow, so that the potential between the power supply line 270 and the power supply line 271 can be stabilized more quickly.

Note that by providing the terminal 281 between the protection diode 254 and the protection diode 255, the threshold voltage (V _th ) of the protection diode 255 can be extracted. In this embodiment mode, since the threshold voltage (V _th ) of the protective diode 255 is 2V, the terminal 281 can be used as a 2V power supply line. Further, by providing the terminal 281 between the protective diode 253 and the protective diode 252, the terminal 281 can be used as a 6V power supply line. An arbitrary potential can be taken out by adjusting the threshold voltage (V _th ) of the protective diode 255 and the number of series connections.

(Embodiment 10)
The display device including the protection circuit described in Embodiment 8 can be applied to electronic devices.

As an electronic device using the display device of Embodiment 8 as a display unit, for example, a camera such as a video camera or a digital camera, a goggle type display, a navigation system, a sound reproduction device (car audio, audio component, etc.), a computer, a game A device, a portable information terminal (such as a mobile computer, a cellular phone, a portable game machine, or an electronic book), and an image reproducing device (specifically, a digital versatile disc (DVD)) equipped with a recording medium are reproduced. And a device provided with a display capable of displaying an image).

A display illustrated in FIG. 15A includes a housing 300, a support base 301, and a display portion 302, and has a function of displaying various input information (still images, moving images, text images, and the like) on the display portion 302. . Note that the function of the display illustrated in FIG. 15A is not limited thereto, and for example, a speaker may be included, or a touch panel capable of inputting information as well as displaying information may be used.

In the television device illustrated in FIG. 15B, a display portion 312 is incorporated in a housing 311. The display unit 312 can display an image. Here, a configuration is shown in which the rear side of the housing is supported by being fixed to the wall 310.

The television device illustrated in FIG. 15B can be operated with an operation switch included in the housing 311 or the remote controller 315. The operation keys 314 provided on the remote controller 315 can be used to operate the channel and volume, and the video displayed on the display unit 312 can be operated. Further, the remote controller 315 may be provided with a display unit 313 for displaying information output from the remote controller 315.

Note that the television set illustrated in FIG. 15B is preferably provided with a receiver, a modem, and the like. General TV broadcasts can be received by a receiver, and connected to a wired or wireless communication network via a modem, so that it can be unidirectional (sender to receiver) or bidirectional (sender and receiver). It is also possible to perform information communication between each other or between recipients).

A computer illustrated in FIG. 15C includes a main body 320, a housing 321, a display portion 322, a keyboard 323, an external connection port 324, and a pointing device 325, and displays a variety of information (still images, moving images, text images, and the like). A function of displaying in the portion 322; Note that the functions of the computer illustrated in FIG. 15C are not limited thereto, and for example, a touch panel that can input information as well as display information may be used.

As described in this embodiment, a nonlinear element such as a diode which is one embodiment of the present invention can be used for an electronic device.

101 substrate 103 insulating layer 105 electrode 106 electrode 107 oxide semiconductor layer 109 electrode 111 gate insulating layer 113 electrode 115 electrode 117 insulating layer 119 contact hole 121 contact hole 123 contact hole 125 wiring 129 wiring 131 wiring 132 wiring 133 transistor 141 transistor 143 transistor 145 Transistor 151 Oxide semiconductor layer 153 Chain line portion 155 Amorphous region 157 Crystal grain

Claims (18)

A first electrode formed on a substrate;
An oxide semiconductor layer having a hydrogen concentration detected by secondary ion mass spectrometry formed on and in contact with the first electrode of 5 × 10 ¹⁹ / cm ³ or less;
A second electrode formed on and in contact with the oxide semiconductor layer;
A gate insulating layer covering the first electrode, the oxide semiconductor layer, and the second electrode;
A plurality of third electrodes formed in contact with the gate insulating layer and facing each other through the first electrode, the oxide semiconductor layer, and the second electrode;
The plurality of third electrodes are connected to the second electrode,
A nonlinear element characterized in that a work function φmd of the first electrode, an electron affinity χ of the oxide semiconductor layer, and a work function φms of the second electrode satisfy φms ≦ χ ≧ φmd. In claim 1,
The non-linear element, wherein the oxide semiconductor layer has a carrier concentration of less than 1 × 10 ¹² / cm ³ . In any one of Claim 1 or Claim 2,
The first electrode material is aluminum (Al), chromium (Cr), iron (Fe), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W) or yttrium ( A non-linear element comprising an element selected from Y). In any one of Claims 1 to 3,
The second electrode material is aluminum (Al), chromium (Cr), iron (Fe), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W) or yttrium ( A non-linear element comprising an element selected from Y). In any one of Claims 1 thru | or 4,
The nonlinear element, wherein the first electrode material in contact with the oxide semiconductor layer and the second electrode material in contact with the oxide semiconductor layer are the same. In any one of Claims 1 thru | or 5,
The non-linear element, wherein at least a portion of the gate insulating layer in contact with the oxide semiconductor layer is an oxide insulating layer. In any one of Claims 1 thru | or 6,
The oxide insulating layer is silicon oxide;
The non-linear element, wherein the silicon oxide is covered with silicon nitride. A display device provided with a protection circuit having the nonlinear element according to claim 1. An electronic device using the display device according to claim 8. A first electrode formed on a substrate;
An oxide semiconductor layer having a hydrogen concentration detected by secondary ion mass spectrometry formed on and in contact with the first electrode of 5 × 10 ¹⁹ / cm ³ or less;
A second electrode formed on and in contact with the oxide semiconductor layer;
A gate insulating layer covering the first electrode, the oxide semiconductor layer, and the second electrode;
A plurality of third electrodes formed in contact with the gate insulating layer and facing each other through the first electrode, the oxide semiconductor layer, and the second electrode;
The plurality of third electrodes are connected to the second electrode,
A nonlinear element characterized in that a work function φmd of the first electrode, an electron affinity χ of the oxide semiconductor layer, and a work function φms of the second electrode satisfy φms> χ ≧ φmd. In claim 10,
The non-linear element, wherein the oxide semiconductor layer has a carrier concentration of less than 1 × 10 ¹² / cm ³ . In any one of Claim 10 or Claim 11,
The first electrode material is tungsten (W), molybdenum (Mo), chromium (Cr), iron (Fe), gold (Au), platinum (Pt), copper (Cu), cobalt (Co), nickel ( A nonlinear element comprising an element selected from Ni), beryllium (Be), or indium tin oxide (ITO). In any one of Claim 10 or Claim 12,
The second electrode material is selected from titanium (Ti), yttrium (Y), aluminum (Al), zirconium (Zr), magnesium (Mg), silver (Ag), manganese (Mn), or tantalum (Ta). A non-linear element characterized by containing a selected element. In any one of Claims 10 thru | or 13,
The nonlinear element, wherein the first electrode material in contact with the oxide semiconductor layer is different from the second electrode material in contact with the oxide semiconductor layer. In any one of Claims 10-14,
The non-linear element, wherein at least a portion of the gate insulating layer in contact with the oxide semiconductor layer is an oxide insulating layer. In any one of Claims 10 to 15,
The oxide insulating layer is silicon oxide;
The non-linear element, wherein the silicon oxide is covered with silicon nitride. A display device provided with a protection circuit having the nonlinear element according to claim 10. An electronic device using the display device according to claim 17.

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