CN103021944A - TFT (thin-film transistor) array substrate, manufacturing method of TFT array substrate, and display device with TFT array substrate - Google Patents
TFT (thin-film transistor) array substrate, manufacturing method of TFT array substrate, and display device with TFT array substrate Download PDFInfo
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- CN103021944A CN103021944A CN2012105646228A CN201210564622A CN103021944A CN 103021944 A CN103021944 A CN 103021944A CN 2012105646228 A CN2012105646228 A CN 2012105646228A CN 201210564622 A CN201210564622 A CN 201210564622A CN 103021944 A CN103021944 A CN 103021944A
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Abstract
An embodiment of the invention discloses a TFT (thin-film transistor) array substrate, a manufacturing method of the TFT array substrate, and a display device with the TFT array substrate, relates to the display field and aims to reduce composition process times and lower array substrate manufacture cost. The manufacturing method of the TFT array substrate includes: making a gate-including pattern, at least including a gate and a gate wire, on a substrate; sequentially forming a gate insulated layer and a semiconductor film, making first via holes on the gate insulated layer and second via holes on the semiconductor film by single one-step composition process; forming a source and drain metal layer and making a source layer pattern and a drain-source electrode pattern by one-step composition process. The first via holes and the second via holes superpose correspondingly and are both located above the gate wire.
Description
Technical field
The present invention relates to the demonstration field, relate in particular to a kind of TFT (Thin Film Transistor, Thin Film Transistor (TFT)) array base palte and manufacture method, display unit.
Background technology
Along with the development of electronic technology, liquid crystal display has been widely used in each demonstration field.In order to realize the high-resolution of liquid crystal display, high aperture and GOA (GateDriver on Array, the capable driving of array base palte) application of technology, AD-SDS (Advanced-Super Dimensional Switching, referred to as ADS, senior super dimension field switch) production technology of type array base palte is converted into masking process 7 times, that is: grid metal mask layer, the active layer mask, the gate insulation layer mask, the first electrode layer mask, source leak metal mask layer, passivation layer mask and the second metal mask layer array base palte that completes.
The inventor finds that in research process there is following problem at least in prior art: because masking process has been used in the making of array base palte 7 times, using mask technique number of times is more, cause the production capacity of product to descend, and cost of manufacture is higher.
Summary of the invention
Embodiments of the invention technical problem to be solved is to provide a kind of tft array substrate and manufacture method, display unit, can reduce composition technique number of times, reduces the cost of manufacture of array base palte.
The application's one side provides a kind of manufacture method of tft array substrate, comprising:
Make the pattern that comprises grid at substrate, the described pattern of grid that comprises comprises grid and grid cabling at least;
Form successively gate insulation layer and semiconductive thin film, by a composition technique, make to form and to be positioned at the first via hole on the described gate insulation layer and to be positioned at the second via hole on the described semiconductive thin film, described the first via hole and described the second via hole correspondence position coincide, and all are positioned at the top of described grid cabling;
Metal level is leaked in the formation source, by a composition technique, makes forming the pattern that comprises active layer and the pattern that comprises source-drain electrode.
Further, the described composition technique of passing through one time make to form and to be positioned at the first via hole on the described gate insulation layer and to be positioned at the second via hole on the described semiconductive thin film, comprising:
At described semiconductive thin film coating the first photoresist layer;
To described the first photoresist layer expose, development treatment, form and to be positioned at the first photoresist reserve part that the first photoresist that pre-sets via area is removed part, is positioned at other zones;
Adopt etching technics, remove successively described semiconductive thin film and described gate insulation layer that described the first photoresist is removed the part below, form described the first via hole and described the second via hole;
Adopt stripping technology, remove the photoresist of described the first photoresist reserve part.
Further, the described composition technique of passing through one time makes forming the pattern that comprises active layer and the pattern that comprises source-drain electrode, comprising:
Leak metal level coating the second photoresist layer in described source;
To described the second photoresist layer expose, development treatment, form and to be positioned at the second photoresist that pre-sets the second photoresist reserve part of comprising the source-drain electrode area of the pattern, is positioned at the second photoresist half reserve part in thin-film transistor channel region territory and is positioned at other zones and to remove part;
Adopt etching technics, remove successively described source leakage metal level and described semiconductive thin film that described the second photoresist is removed the part below;
Adopt cineration technics, remove the photoresist of described the second photoresist half reserve part;
Adopt etching technics, metal level and the described semiconductive thin film of part are leaked in the described source of removing described the second photoresist half reserve part below, form described pattern and the described pattern that comprises active layer that comprises source-drain electrode;
Adopt stripping technology, remove the photoresist of described the second photoresist reserve part.
Further, after making forms the pattern that comprises active layer and comprises the pattern of source-drain electrode, also comprise:
Making comprises the pattern of the first electrode.
Further, after described making comprises the pattern of the first electrode, also comprise:
Make the pattern of passivation layer and the pattern that comprises the second electrode.
The application also provides a kind of tft array substrate on the other hand, comprises the pattern that comprises grid that is arranged on the substrate, and the gate insulation layer pattern comprises the pattern of active layer, comprises the pattern of source-drain electrode, comprises the pattern of the first electrode, also comprises:
Be positioned at the first via hole on the described gate insulation layer pattern and be positioned at the second via hole on the described pattern that comprises active layer by what composition technique formed; The described pattern of grid that comprises comprises grid and grid cabling at least, and described the first via hole and described the second via hole correspondence position coincide, and all are positioned at the top of described grid cabling.
Further, the described pattern that comprises active layer is positioned at the top of the first via hole neighboring area of described grid, described gate insulation layer and the below of described source-drain electrode.
Further, described tft array substrate also comprises: passivation layer pattern and the pattern that comprises the second electrode.
Further, the described pattern that the comprises source-drain electrode connection metal layer that comprises at least source-drain electrode and cover described the first via hole and described the second via hole.
Further, described passivation layer pattern comprises passivation layer via hole.
Further, the described pattern of the second electrode that comprises comprises the second electrode and the connecting electrode that covers described passivation layer via hole at least.
Further, the described pattern of the first electrode and the described pattern of the second electrode that comprises of comprising arranges with layer, the described pattern of the first electrode that comprises comprises a plurality of the first strip electrodes, the described pattern of the second electrode that comprises comprises a plurality of the second strip electrodes, and described the first strip electrode and described the second bar shaped electrode gap arrange.
Further, the described pattern that comprises the first electrode and the described different layer of pattern of the second electrode that comprises arrange, and the electrode pattern that wherein is positioned at the upper strata comprises a plurality of strip electrodes, and the electrode pattern that is positioned at lower floor comprises a plurality of strip electrodes or for plate shaped.
The application's again one side provides a kind of display unit, comprises above-mentioned array base palte.
The tft array substrate of the embodiment of the invention and manufacture method, display unit, by a composition technique, formation is positioned at the first via hole on the gate insulation layer of grid cabling top and the second via hole on the semiconductive thin film, and after metal level is leaked in the formation source, comprise the pattern of active layer, the pattern of source-drain electrode by a composition technique making, the structure that three composition technique in the prior art just can be finished, twice composition technique just can be finished, effectively reduce the cost of manufacture of array base palte, improved the production capacity of display unit.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the accompanying drawing of required use was done to introduce simply during the below will describe embodiment, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the schematic flow sheet of the manufacture method of tft array substrate in one embodiment of the invention;
Fig. 2-Figure 14 is the structural representation of tft array substrate in manufacturing process in another embodiment of the present invention;
Figure 15-Figure 17 is the schematic flow sheet of the manufacture method of tft array substrate in another embodiment of the present invention.
Embodiment
The embodiment of the invention provides a kind of tft array substrate and manufacture method, display unit, can reduce masking process (composition technique) number of times, reduces the cost of manufacture of array base palte.
In below describing, in order to illustrate rather than in order limiting, to have proposed the detail such as particular system structure, interface, technology, understand the present invention in order to thoroughly cut.Yet, not it will be clear to one skilled in the art that in having other embodiment of these details and can realize the present invention yet.In other situation, omit the detailed description to well-known device, circuit and method, in order to avoid unnecessary details hinders description of the invention.
The present embodiment provides a kind of manufacture method of tft array substrate, and such as Fig. 1-shown in Figure 14, the method comprises:
As shown in Figure 2, the substrate 1 of the present embodiment can be glass substrate, also can select as required the substrate of other materials, is not construed as limiting at this.Concrete, this step is made at substrate 1 and is comprised that the pattern of grid comprises: at first form the grid metal level at substrate 1; Apply one deck photoresist at the grid metal level again, such as positive photoresist, and to this photoresist layer expose, development treatment, form and to be positioned at the photoresist reserve part that pre-sets grid 21 zones and grid cabling 22 zones, to be positioned at other regional photoresists removal parts; Then adopt etching technics, preferred wet-etching technique is removed the grid metal level that photoresist is removed the part below; Adopt at last stripping technology, remove the photoresist of photoresist reserve part, the final pattern that comprises grid that forms.Concrete, the above-mentioned pattern of grid that comprises further comprises grid 21 and grid cabling 22.
As shown in Figure 3, comprise the pattern of grid 21 in formation after, on substrate 1, form successively gate insulation layer 3 and semiconductive thin film 4, and by a composition technique, shown in Fig. 5 b, make to form and to be positioned at the first via hole 30 on the gate insulation layer 3 and to be positioned at the second via hole 40 on the semiconductive thin film 4, and the first via hole 30 and the second via hole 40 correspondence positions coincide, all be positioned at the top of described grid cabling 22.That is to say, the method for the present embodiment two layer structures of etching simultaneously in composition technique, and formed the via hole of two stacks.
Need to prove the abbreviation of the series of process process in the composition technique here refers to comprise exposure, develop and be etched in.A composition technique is corresponding to a masking process, uses a mask plate some pattern that completes and is called and carried out composition technique one time.Concrete, as shown in figure 16, by a composition technique, make and be positioned at the first via hole 30 on the gate insulation layer 3 and be positioned at the second via hole 40 on the semiconductive thin film 4 in this step, comprising:
Step 1021, at described semiconductive thin film 4 coatings the first photoresist layer;
Optionally, this semiconductive thin film 4 comprises semiconductor layer and doping semiconductor layer.The first photoresist layer in the present embodiment can be selected negative photoresist or positive photoresist, can be dissolved in some solvent, and what form insoluble material after the illumination is negative photoresist; Otherwise, be insoluble to some solvent, after illumination, become the positive photoresist that is of soluble substance.
Different types of photoresist is to there being different mask plates, and for example, when photoresist was positive photoresist, in the mask plate that adopts, it was the exposure area that photoresist is removed zone corresponding to part, and material therefor is light transmissive material; Zone corresponding to photoresist reserve part is exposure area not, and material therefor is light-proof material; The zone that photoresist half reserve part is corresponding is half exposure area, and material therefor is semi transparent material.When photoresist was negative photoresist, in the mask plate that then adopts, photoresist was removed zone corresponding to part and is exposure area not, and material therefor is light-proof material; The zone that the photoresist reserve part is corresponding is the exposure area, and material therefor is light transmissive material; The zone that photoresist half reserve part is corresponding is half exposure area, and material therefor is semi transparent material.
Step 1022, to described the first photoresist layer expose, development treatment, form and to be positioned at the first photoresist reserve part that the first photoresist that pre-sets via area is removed part, is positioned at other zones;
As shown in Figure 4,6 pairs of described the first photoresist layers 5 of employing mask plate expose, development treatment, wherein, and when the first photoresist layer 5 is positive photoresist, exposure area B is the zone that the first photoresist is removed part 52 correspondences, and exposure area A is not the zone of the first photoresist reserve part 51 correspondences; When the first photoresist layer 5 was negative photoresist, exposure area A was the zone of the first photoresist reserve part 51 correspondences, and exposure area B is not the zone that the first photoresist is removed part 52 correspondences.The first photoresist is removed the zone of part 52 correspondences for pre-seting via area.
Step 1023, employing etching technics are removed described semiconductive thin film 4 and described gate insulation layer 3 that described the first photoresist is removed the part below successively, form described the first via hole 30 and described the second via hole 40;
Concrete, shown in Fig. 5 a, because the first photoresist is removed the part correspondence and is pre-seted via area, therefore, after etching technics is finished, the semiconductive thin film 4 and the gate insulation layer 3 that pre-set via area are etched away, and form the second via hole 40 and gate insulation layer 3 formation the first via hole 30 at semiconductive thin film 4.
Step 1024, adopt stripping technology, remove the photoresist of described the first photoresist reserve part.
Concrete, shown in Fig. 5 b, remove the photoresist of described the first photoresist reserve part 51.
Metal level is leaked in step 103, formation source, by a composition technique, makes forming the pattern that comprises active layer and the pattern that comprises source-drain electrode.
As shown in Figure 6, form respectively on gate insulation layer 3 and semiconductive thin film 4 after the first via hole 30 and the second via hole 40, metal level 7 is leaked in the formation source again.Afterwards, shown in Fig. 7-11, make the pattern that comprises active layer and the pattern that comprises source-drain electrode.Concrete, as shown in figure 17, this step comprises:
As shown in Figure 7, at first leak metal level 7 in the source and apply one deck the second photoresist layer 8.
Concrete, as shown in Figure 8, described the second photoresist layer 8 is exposed, after the development treatment, forms Three regions: the second photoresist is removed zone 82 corresponding to part corresponding zone 81, the second photoresist reserve part and the zone of the second photoresist half reserve part 83 correspondences.The second photoresist reserve part 82 is positioned at the first via hole and corresponding zone and the corresponding zone of source-drain electrode of the second via hole of grid cabling top, the second photoresist half reserve part 83 is positioned at the corresponding zone of thin film transistor channel, and the second photoresist is removed part 81 and is positioned at the zone of removing above two kinds of situations.
When the second photoresist layer 8 is positive photoresist, exposure area B ' is the zone that the second photoresist is removed part 81 correspondences, exposure area A ' is not the zone of the second photoresist reserve part 82 correspondences, and partial exposure area C ' is the zone of the second photoresist half reserve part 83 correspondences; When the second photoresist layer 8 is negative photoresist, exposure area A ' is the zone of the second photoresist reserve part 82 correspondences, exposure area B ' is not the zone that the second photoresist is removed part 81 correspondences, and partial exposure area C ' is similarly the zone of the second photoresist half reserve part 83 correspondences.
As shown in Figure 9, metal level is leaked in the described source below the second photoresist is removed partly and described semiconductive thin film is removed.As seen in the present embodiment, the pattern that comprises active layer is positioned at the top of the first via hole neighboring area of grid 21, described gate insulation layer and the below of source-drain electrode.Wherein, it is because the connection metal layer 73 that its top keeps blocks causes that the semiconductive thin film of the top of the first via hole neighboring area of described gate insulation layer 4 keeps, and semiconductive thin film 4 reservations of source-drain electrode below are that the source-drain electrode owing to the top blocks and causes.
Concrete, such as Fig. 9, the photoresist of the second photoresist half reserve part 83 and the photoresist of the second photoresist reserve part 82 are carried out the ashing operation, the photoresist of the second photoresist half reserve part 83 is removed, a part of photoresist of the second photoresist reserve part 82 also can be removed simultaneously, but because thickness is thicker, still some retains photoresist, so can not have influence on the layer structure below 82 corresponding regions of the second photoresist reserve part in follow-up etching process.
Concrete, as shown in figure 10, adopt etching technics, preferably adopt wet-etching technique, etch away the second photoresist half reserve part, namely metal level is leaked in the source in thin-film transistor channel region territory, forms the described pattern that comprises source-drain electrode (source electrode 71 and drain electrode 72).The described pattern of source-drain electrode that comprises comprises that source-drain electrode (source electrode 71 and drain electrode 72) and covering are positioned at the first via hole 30 of grid cabling 22 tops and the connection metal layer 73 of the second via hole 40, and described connection metal layer 73 is used for connecting the grid cabling 22 of outside input drive signal and below.
Need to prove, generally speaking, semiconductive thin film comprises semiconductor layer and doping semiconductor layer, after metal level 7 is leaked in the source of the complete channel region of etching, need the doping semiconductor layer in the continuation etching semiconductor film, to finish the described pattern 41 that comprises active layer.But in some cases, semiconductive thin film does not comprise doping semiconductor layer, and the source leakage metal level that then only need to etch away channel region gets final product, and needn't continue the etching semiconductor film.For above-mentioned two situations, select according to actual needs, the present invention does not limit.
Concrete, as shown in figure 11, behind the photoresist layer of peeling off the second photoresist reserve part, finally obtain the pattern that comprises the pattern 41 of active layer and comprise source-drain electrode (source electrode 71 and drain electrode 72).Further, as shown in figure 15, the method for the present embodiment also comprises after making comprises the pattern 41 of active layer and comprises the pattern of source-drain electrode (source electrode 71 and drain electrode 72):
As shown in figure 12, form the pattern that comprises the first electrode 9 by a composition technique, wherein, the first electrode 9 is arranged on the top of gate insulation layer 3, and is connected with source electrode 71.
Further, after described making comprises the pattern of the first electrode, also comprise:
Shown in Figure 13～14, at first form passivation layer 10, and pass through the pattern of a composition technique formation passivation layer; And then form the pattern that comprises the second electrode 11 by composition technique.
Concrete, shown in Figure 13 a, be formed with the substrate formation passivation layer 10 that comprises the first electrode pattern.Afterwards, shown in Figure 13 b, form passivation layer pattern by a composition technique, described passivation layer pattern comprises passivation layer via hole 100, and described passivation layer via hole 100 is positioned at the top of described connection metal layer 73.Afterwards, as shown in figure 14, by a composition technique, form the described pattern that comprises the second electrode 11, the described pattern of the second electrode that comprises comprises the second electrode 11 and the connecting electrode 110 that covers described passivation layer via hole 100, is used for connecting the grid cabling 22 of outside input drive signal and below.Certainly, in the GOA circuit structure, be integrated on the substrate because grid drives, also described passivation layer via hole 100 and connecting electrode 110 can be set, design according to actual needs, do not do restriction herein.
The manufacture method of the tft array substrate of the embodiment of the invention, by a composition technique, making is positioned at the first via hole of the gate insulation layer above the grid cabling and the second via hole on the semiconductive thin film, and after metal level is leaked in the formation source, by a composition technique, make and form the pattern that comprises active layer and the pattern that comprises source-drain electrode, the structure that three composition technique in the prior art just can be finished, twice composition technique just can be finished, effectively reduce the cost of manufacture of array base palte, improved production capacity.
Embodiment is corresponding with said method, the embodiment of the invention also provides a kind of tft array substrate that adopts said method to make, comprise the pattern that comprises grid that is arranged on the substrate, the gate insulation layer pattern, the pattern that comprises active layer, the pattern that comprises source-drain electrode comprises also comprising the pattern of the first electrode: be positioned at the first via hole on the described gate insulation layer pattern and be positioned at the second via hole on the described pattern that comprises active layer by what composition technique formed; Wherein, the described pattern of grid that comprises comprises grid and grid cabling at least, and described the first via hole and described the second via hole correspondence position coincide, and all are positioned at the top of described grid cabling.
Concrete, as shown in figure 14, comprise the pattern that comprises grid 21 that is arranged on the substrate 1, the pattern of gate insulation layer, the pattern 41 that comprises active layer, the pattern (source electrode 71 and drain electrode 72) that comprises source-drain electrode comprises also comprising the pattern of the first electrode 9: be positioned at the first via hole 30 on the gate insulation layer 3 and be positioned at the second via hole 40 on the described pattern 41 that comprises active layer by what composition technique formed; The described pattern of grid that comprises comprises grid 21 and grid cabling 22 at least, and described the first via hole 30 coincides with described the second via hole 40 correspondence positions, all is positioned at the top of described grid cabling 22.
Further, the described pattern that comprises active layer is positioned at the top of the first via hole 30 neighboring areas of described grid 21, described gate insulation layer and the below of described source-drain electrode (source electrode 71 and drain electrode 72).
Optionally, described tft array substrate also comprises passivation layer pattern and comprises the pattern of the second electrode 11.
Optionally, the described pattern that comprises source-drain electrode comprises source-drain electrode (source electrode 71 and drain electrode 72) and the connection metal layer 73 that covers described the first via hole 30 and described the second via hole 40 at least.
Optionally, described passivation layer pattern comprises passivation layer via hole 100.
Optionally, the described pattern of the second electrode that comprises comprises the second electrode 11 and the connecting electrode 110 that covers described passivation layer via hole 100 at least.
Need to prove, described passivation layer via hole 100 is positioned at the top of described connection metal layer 73.The described pattern of the second electrode that comprises comprises the second electrode 11 and the connecting electrode 110 that covers described passivation layer via hole 100, is used for connecting the grid cabling 22 of outside input drive signal and below.Certainly, in the GOA circuit structure, be integrated on the substrate because grid drives, also described passivation layer via hole 100 and connecting electrode 110 can be set, design according to actual needs, do not do restriction herein.
The tft array substrate that the embodiment of the invention provides goes for AD-SDS (Advanced-Super Dimensional Switching, referred to as ADS, senior super dimension field switch) type, IPS (In Plane Switch, the transverse electric field effect) production of the liquid crystal indicator of the type such as type, TN (Twist Nematic, twisted-nematic) type.The longitudinal electric field that the parallel electric field that the AD-SDS technology produces by pixel electrode edge in the same plane and pixel electrode layer and public electrode interlayer produce forms multi-dimensional electric field, make in the liquid crystal cell between pixel electrode, all aligned liquid-crystal molecules can both produce the rotation conversion directly over the electrode, thereby to have improved planar orientation be the liquid crystal operating efficiency and increased light transmission efficiency.
Above-mentioned which kind of liquid crystal indicator all comprises color membrane substrates and the array base palte that box is shaped.Different is, the public electrode of TN type display unit is arranged on the color membrane substrates, and pixel electrode is arranged on the array base palte, includes only the first electrode on the described array base palte; The public electrode of ADS type display unit and IPS type display unit and pixel electrode all are arranged on the array base palte, also comprise the second electrode on the described array base palte.
In the array base palte of the ADS of the present embodiment type display unit, described the first electrode 9 and described the second electrode 11 can be different layer arrange, the electrode that wherein is positioned at the upper strata comprises a plurality of strip electrodes, the electrode that is positioned at lower floor comprises a plurality of strip electrodes or for plate shaped.Optionally, the second electrode 11 that comprises a plurality of strip electrodes that is positioned at the upper strata is public electrode, and plate shaped the first electrode 9 that is positioned at lower floor is pixel electrode.
Different layer arranges at least two kinds of patterns, and at least two kinds of different layer settings of pattern refer to, double-layer films forms at least two kinds of patterns by composition technique at least respectively.Refer to for two kinds of different layer settings of pattern, by composition technique, respectively form a kind of pattern by double-layer films.For example, the first electrode 9 and the second electrode 11 different layer settings refer to: form the first electrode 9 by the ground floor transparent conductive film by composition technique, form the second electrode 11 by second layer transparent conductive film by composition technique, wherein, the first electrode 9 is pixel electrode (or public electrode), and the second electrode 11 is public electrode (or pixel electrode).
In the array base palte of described IPS type display unit, described the first electrode 9 and described the second electrode 11 arrange with layer, described the first electrode 9 comprises a plurality of the first strip electrodes, described the second electrode 11 comprises a plurality of the second strip electrodes, and described the first strip electrode and described the second bar shaped electrode gap arrange.
Arrange at least two kinds of patterns with layer; At least two kinds of patterns refer to layer setting: same film is formed at least two kinds of patterns by composition technique.For example, the first electrode 9 and the second electrode 11 refer to layer setting: form the first electrode 9 and the second electrode 11 by same transparent conductive film by composition technique.Wherein, the electrode that is electrically connected with data wire by switch element (for example, can be thin-film transistor) is pixel electrode, and the electrode that public electrode wire is electrically connected is public electrode.
The embodiment of the invention also provides a kind of display unit, comprises any above-mentioned tft array substrate.Described display unit can have for liquid crystal display, LCD TV, digital camera, mobile phone, panel computer etc. product or the parts of any Presentation Function.
The above; be the specific embodiment of the present invention only, but protection scope of the present invention is not limited to this, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (14)
1. the manufacture method of a tft array substrate is characterized in that, comprising:
Make the pattern that comprises grid at substrate, the described pattern of grid that comprises comprises grid and grid cabling at least;
Form successively gate insulation layer and semiconductive thin film, by a composition technique, make to form and to be positioned at the first via hole on the described gate insulation layer and to be positioned at the second via hole on the described semiconductive thin film, described the first via hole and described the second via hole correspondence position coincide, and all are positioned at the top of described grid cabling;
Metal level is leaked in the formation source, by a composition technique, makes forming the pattern that comprises active layer and the pattern that comprises source-drain electrode.
2. the manufacture method of tft array substrate according to claim 1 is characterized in that, the described composition technique of passing through one time make to form and to be positioned at the first via hole on the described gate insulation layer and to be positioned at the second via hole on the described semiconductive thin film, comprising:
At described semiconductive thin film coating the first photoresist layer;
To described the first photoresist layer expose, development treatment, form and to be positioned at the first photoresist reserve part that the first photoresist that pre-sets via area is removed part, is positioned at other zones;
Adopt etching technics, remove successively described semiconductive thin film and described gate insulation layer that described the first photoresist is removed the part below, form described the first via hole and described the second via hole;
Adopt stripping technology, remove the photoresist of described the first photoresist reserve part.
3. the manufacture method of tft array substrate according to claim 1 is characterized in that, the described composition technique of passing through one time makes forming the pattern that comprises active layer and the pattern that comprises source-drain electrode, comprising:
Leak metal level coating the second photoresist layer in described source;
To described the second photoresist layer expose, development treatment, form and to be positioned at the second photoresist that pre-sets the second photoresist reserve part of comprising the source-drain electrode area of the pattern, is positioned at the second photoresist half reserve part in thin-film transistor channel region territory and is positioned at other zones and to remove part;
Adopt etching technics, remove successively described source leakage metal level and described semiconductive thin film that described the second photoresist is removed the part below;
Adopt cineration technics, remove the photoresist of described the second photoresist half reserve part;
Adopt etching technics, metal level and the described semiconductive thin film of part are leaked in the described source of removing described the second photoresist half reserve part below, form described pattern and the described pattern that comprises active layer that comprises source-drain electrode;
Adopt stripping technology, remove the photoresist of described the second photoresist reserve part.
4. the manufacture method of tft array substrate according to claim 1 is characterized in that, after making forms the pattern that comprises active layer and comprises the pattern of source-drain electrode, also comprises:
Making comprises the pattern of the first electrode.
5. the manufacture method of tft array substrate according to claim 4 is characterized in that, after described making comprises the pattern of the first electrode, also comprises:
Make the pattern of passivation layer and the pattern that comprises the second electrode.
6. a tft array substrate comprises the pattern that comprises grid that is arranged on the substrate, and the gate insulation layer pattern comprises the pattern of active layer, comprises the pattern of source-drain electrode, comprises the pattern of the first electrode, it is characterized in that, also comprises:
Be positioned at the first via hole on the described gate insulation layer pattern and be positioned at the second via hole on the described pattern that comprises active layer by what composition technique formed; The described pattern of grid that comprises comprises grid and grid cabling at least, and described the first via hole and described the second via hole correspondence position coincide, and all are positioned at the top of described grid cabling.
7. tft array substrate according to claim 6 is characterized in that, the described pattern that comprises active layer is positioned at the top of the first via hole neighboring area of described grid, described gate insulation layer and the below of described source-drain electrode.
8. tft array substrate according to claim 6 is characterized in that, also comprises: passivation layer pattern and the pattern that comprises the second electrode.
9. tft array substrate according to claim 8 is characterized in that, the connection metal layer that the described pattern that comprises source-drain electrode comprises at least source-drain electrode and covers described the first via hole and described the second via hole.
10. tft array substrate according to claim 9 is characterized in that, described passivation layer pattern comprises passivation layer via hole.
11. tft array substrate according to claim 10 is characterized in that, the described pattern of the second electrode that comprises comprises the second electrode and the connecting electrode that covers described passivation layer via hole at least.
12. tft array substrate according to claim 8, it is characterized in that, the described pattern of the first electrode and the described pattern of the second electrode that comprises of comprising arranges with layer, the described pattern of the first electrode that comprises comprises a plurality of the first strip electrodes, the described pattern of the second electrode that comprises comprises a plurality of the second strip electrodes, and described the first strip electrode and described the second bar shaped electrode gap arrange.
13. tft array substrate according to claim 8, it is characterized in that, the described pattern of the first electrode and the described different layer of pattern of the second electrode that comprises of comprising arranges, the electrode pattern that wherein is positioned at the upper strata comprises a plurality of strip electrodes, and the electrode pattern that is positioned at lower floor comprises a plurality of strip electrodes or for plate shaped.
14. a display unit is characterized in that, comprises each described array base palte of claim 6～13.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103456746A (en) * | 2013-09-10 | 2013-12-18 | 北京京东方光电科技有限公司 | Array substrate, manufacturing method thereof and display device |
| CN103730473A (en) * | 2013-12-25 | 2014-04-16 | 北京京东方光电科技有限公司 | Array substrate, method for manufacturing array substrate and display device |
| CN105206567A (en) * | 2015-10-10 | 2015-12-30 | 深圳市华星光电技术有限公司 | Array substrate and manufacturing method thereof |
| CN105374881A (en) * | 2014-08-29 | 2016-03-02 | 中华映管股份有限公司 | Oxide semiconductor thin film transistor and method of manufacturing the same |
| CN104037089B (en) * | 2014-06-26 | 2017-01-11 | 华映视讯（吴江）有限公司 | Manufacturing method for thin film transistor |
| CN108364960A (en) * | 2018-02-22 | 2018-08-03 | 京东方科技集团股份有限公司 | A kind of array substrate, display panel, display device and preparation method |
| CN108511394A (en) * | 2018-03-27 | 2018-09-07 | 京东方科技集团股份有限公司 | Array substrate and its manufacturing method, display device |
| CN109659312A (en) * | 2018-10-15 | 2019-04-19 | 深圳市华星光电半导体显示技术有限公司 | A kind of array substrate and preparation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1512829A (en) * | 2002-12-26 | 2004-07-14 | Lg.������Lcd��ʽ���� | Organic electroluminescent devcie and its producing method |
| CN101150091A (en) * | 2007-11-08 | 2008-03-26 | 友达光电股份有限公司 | Pixel structure and its making method |
| US20110086474A1 (en) * | 2009-10-12 | 2011-04-14 | Hong-Kee Chin | Method of manufacturing thin film transistor substrate |
| CN102096089A (en) * | 2009-12-10 | 2011-06-15 | 乐金显示有限公司 | Photo diode for detecting X-ray and manufacturing method thereof |
| CN202948925U (en) * | 2012-12-21 | 2013-05-22 | 北京京东方光电科技有限公司 | TFT array substrate and display device |
-
2012
- 2012-12-21 CN CN2012105646228A patent/CN103021944A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1512829A (en) * | 2002-12-26 | 2004-07-14 | Lg.������Lcd��ʽ���� | Organic electroluminescent devcie and its producing method |
| CN101150091A (en) * | 2007-11-08 | 2008-03-26 | 友达光电股份有限公司 | Pixel structure and its making method |
| US20110086474A1 (en) * | 2009-10-12 | 2011-04-14 | Hong-Kee Chin | Method of manufacturing thin film transistor substrate |
| CN102096089A (en) * | 2009-12-10 | 2011-06-15 | 乐金显示有限公司 | Photo diode for detecting X-ray and manufacturing method thereof |
| CN202948925U (en) * | 2012-12-21 | 2013-05-22 | 北京京东方光电科技有限公司 | TFT array substrate and display device |
Cited By (25)
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