CN103456746B - A kind of array base palte and preparation method thereof, display unit - Google Patents
A kind of array base palte and preparation method thereof, display unit Download PDFInfo
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- CN103456746B CN103456746B CN201310409592.8A CN201310409592A CN103456746B CN 103456746 B CN103456746 B CN 103456746B CN 201310409592 A CN201310409592 A CN 201310409592A CN 103456746 B CN103456746 B CN 103456746B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 60
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- 238000000059 patterning Methods 0.000 claims abstract description 34
- 238000009413 insulation Methods 0.000 claims abstract description 33
- 229920002120 photoresistant polymer Polymers 0.000 claims description 126
- 239000000758 substrate Substances 0.000 claims description 82
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 49
- 239000012528 membrane Substances 0.000 claims description 33
- 238000005530 etching Methods 0.000 claims description 30
- 238000005516 engineering process Methods 0.000 claims description 16
- 229910044991 metal oxide Inorganic materials 0.000 claims description 15
- 150000004706 metal oxides Chemical class 0.000 claims description 15
- 238000002161 passivation Methods 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 11
- 238000005520 cutting process Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 116
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- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 16
- 229910052750 molybdenum Inorganic materials 0.000 description 16
- 239000011733 molybdenum Substances 0.000 description 16
- 239000010409 thin film Substances 0.000 description 9
- 239000007769 metal material Substances 0.000 description 8
- 239000004973 liquid crystal related substance Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
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- 238000005229 chemical vapour deposition Methods 0.000 description 3
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- 230000004075 alteration Effects 0.000 description 2
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- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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- 230000008021 deposition Effects 0.000 description 1
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- 239000011521 glass Substances 0.000 description 1
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- 239000010703 silicon Substances 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
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Abstract
Embodiments provide a kind of array base palte and preparation method thereof, display unit, relate to Display Technique field, patterning processes number of times can be reduced, reduce costs.This array base palte comprises pixel region and array base palte row cutting GOA district; Pixel region comprise grid, the pattern of active layer, source electrode and drain electrode, with drain be electrically connected pixel electrode, be positioned to be electrically connected with source electrode above source electrode and with second transparency electrode of pixel electrode with layer; The pattern setting of gate insulation layer is in described pixel region and described GOA district; GOA district comprise with grid with floor the first electrode, retains pattern, and source electrode and drain with the second electrode of floor, with first transparency electrode of pixel electrode with layer with the pattern of active layer with the active layer of floor; Wherein, active layer reservation pattern and the second electrode include the via hole exposing the first electrode; First transparency electrode to be arranged on above the second electrode and to be all electrically connected with the second electrode and the first electrode.For the manufacture of display unit.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of array base palte and preparation method thereof, display unit.
Background technology
Along with thin-film transistor (ThinFilmTransistor, be called for short TFT) development of lcd technology, increasing new technology is constantly suggested and applies, such as high-resolution, high aperture, array base palte row cutting (GateonArray is called for short GOA) technology etc.Wherein, in order to reduce costs the TFT display floater obtaining narrow frame, GOA structure becomes particularly important.But the introducing of GOA structure also brings the complexity of array base-plate structure design, adds the patterning processes quantity and difficulty that make array base palte simultaneously.
At present, form the tft array substrate with GOA structure and need the repeatedly patterning processes such as grid metal mask layer, gate insulation layer mask, active layer mask, source and drain metal mask layer, the first electrode layer mask, passivation layer mask and the second electrode lay mask, and comprise the techniques such as film forming, exposure, development, etching, stripping respectively again in patterning processes each time.The number of times of patterning processes too much will directly cause the reduction of the increase of technological difficulty, the rising of product cost and product production capacity.
Therefore, when formation has the tft array substrate of GOA structure, how to reduce the number of times of patterning processes, become the problem of people's growing interest.
Summary of the invention
Embodiments of the invention provide a kind of array base palte and preparation method thereof, display unit, can reduce the number of times of patterning processes, thus promote the production capacity of volume production product, reduce costs.
For achieving the above object, embodiments of the invention adopt following technical scheme:
On the one hand, provide a kind of array base palte, this array base palte comprises pixel region and GOA district; Described pixel region comprise the grid be arranged on substrate, the pattern of active layer, source electrode and drain electrode, with the described pixel electrode be electrically connected that drains, the pattern setting of gate insulation layer is in described pixel region and described GOA district; Also comprise be arranged on described GOA district and described grid with floor the first electrode, retains pattern, and described source electrode and drain with the second electrode of floor, with first transparency electrode of described pixel electrode with layer with the pattern of described active layer with the active layer of floor; Wherein, described active layer reservation pattern and described second electrode include the via hole exposing described first electrode; Described first transparency electrode to be arranged on above described second electrode and to be all electrically connected with described second electrode and described first electrode; Described pixel region also comprise to be arranged on above described source electrode and with second transparency electrode of described pixel electrode with layer, described second transparency electrode is electrically connected with described source electrode.
On the other hand, provide a kind of display unit, comprise above-mentioned array base palte.
Again on the one hand, provide a kind of preparation method of above-mentioned array base palte, described array base palte comprises pixel region and GOA district; This preparation method comprises: by a patterning processes, the underlay substrate of described pixel region forms grid, and the underlay substrate in described GOA district forms the first electrode; By a patterning processes, the substrate in described pixel region and described GOA district is formed the pattern of gate insulation layer, the substrate of described pixel region is formed the first pattern and is positioned at the second pattern above described first pattern, the substrate in described GOA district is formed with described first pattern with the active layer of floor retains pattern, with second electrode of described second pattern with floor, and described active layer reservation pattern and described second electrode include the via hole exposing described first electrode divides; Wherein, the pattern of the corresponding active layer of described first pattern, the corresponding source electrode of described second pattern and drain electrode; By a patterning processes, the substrate of described pixel region is at least formed described source electrode and drain electrode, with described drain be electrically connected pixel electrode, be positioned at the second transparency electrode be electrically connected above described source electrode and with described source electrode, the substrate in described GOA district is formed and to be positioned at above described second electrode and the first transparency electrode be all electrically connected with described second electrode and described first electrode.
Embodiments provide a kind of array base palte and preparation method thereof, display unit, this array base palte comprises pixel region and GOA district; Described pixel region comprise the grid be arranged on substrate, the pattern of active layer, source electrode and drain electrode, with the described pixel electrode be electrically connected that drains; The pattern setting of gate insulation layer is in described pixel region and described GOA district; Also comprise be arranged on described GOA district and described grid with floor the first electrode, retains pattern, and described source electrode and drain with the second electrode of floor, with first transparency electrode of described pixel electrode with layer with the pattern of described active layer with the active layer of floor; Wherein, described active layer reservation pattern and described second electrode include the via hole exposing described first electrode; Described first transparency electrode to be arranged on above described second electrode and to be all electrically connected with described second electrode and described first electrode; Described pixel region also comprise to be arranged on above described source electrode and with second transparency electrode of described pixel electrode with layer, described second transparency electrode is electrically connected with described source electrode.Like this, can just form TFT structure on array base palte and GOA structure by means of only 3 patterning processes, and pixel electrode, effectively reduce the number of times of patterning processes, thus the production capacity of volume production product can be promoted, reduce costs.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
A kind of preparation method's flow chart comprising the tft array substrate of GOA structure that Fig. 1 provides for the embodiment of the present invention;
A kind of structural representation forming grid and the first electrode that Fig. 2 provides for the embodiment of the present invention;
Fig. 3 retains the structural representation of pattern, the second electrode and GOA district via hole for a kind of pattern, the first pattern, the second pattern, active layer forming gate insulation layer that the embodiment of the present invention provides;
A kind of array base-plate structure schematic diagram one that Fig. 4 (a) provides for the embodiment of the present invention;
A kind of array base-plate structure schematic diagram two that Fig. 4 (b) provides for the embodiment of the present invention;
Fig. 5 (a) ~ Fig. 5 (e) retains the process schematic of pattern, the second electrode and GOA district via hole for a kind of pattern, the first pattern, the second pattern, active layer forming gate insulation layer that the embodiment of the present invention provides;
Fig. 6 (a) ~ Fig. 6 (d) for the embodiment of the present invention provide a kind of be formed with active layer pattern, source electrode and drain electrode, pixel electrode, the second transparency electrode and the first transparency electrode process schematic;
Fig. 7 comprises the structural representation of the pattern of passivation layer for a kind of formation that the embodiment of the present invention provides;
A kind of array base-plate structure schematic diagram three that Fig. 8 provides for the embodiment of the present invention.
Reference numeral:
Pixel region-10a; GOA district-10b; Underlay substrate-100; Gate insulation layer film-11; Amorphous silicon membrane-12a; N+ amorphous silicon membrane-12b; Metallic film-13; Grid-101a; First electrode-101b; The pattern-102 of gate insulation layer; The pattern-103 of active layer; First pattern-103a; Active layer retains pattern-103b; Source electrode-1041; Drain electrode-1042; Second pattern-104a; Second electrode-104b; Via hole-105b; Pixel electrode-106; Second transparency electrode-106a; First transparency electrode-106b; The pattern-107 of passivation layer; Public electrode-108; Intermediate tone mask plate-20; The opaque section-201 of intermediate tone mask plate; The translucent portion-202 of intermediate tone mask plate; The transparent part-203 of intermediate tone mask plate; Photoresist-30; The complete reserve part-301 of photoresist; Photoresist half reserve part-302; Part-303 removed completely by photoresist.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Embodiments provide a kind of preparation method of array base palte, described array base palte comprises pixel region 10a and GOA district 10b; As shown in Figure 1, the method comprises the steps:
S101, as shown in Figure 2, by a patterning processes, the underlay substrate 100 of described pixel region 10a forms grid 101a, the underlay substrate 100 of described GOA district 10b forms the first electrode 101b.
S102, as shown in Figure 3, by a patterning processes, the substrate of described pixel region 10a and described GOA district 10b forms the pattern 102 of gate insulation layer; The substrate of described pixel region 10a is formed the first pattern 103a and is positioned at the second pattern 104a above described first pattern, the substrate of described GOA district 10b is formed with described first pattern 103a with the active layer of floor retains pattern 103b, with the second electrode 104b of described second pattern 104a with floor, and described active layer reservation pattern 103b and described second electrode 104b includes the via hole 105b exposing described first electrode 101b.
Wherein, the pattern 103 of the corresponding active layer of described first pattern 103a, the corresponding source electrode 1041 of described second pattern 104a and drain electrode 1042.
S103, as Fig. 4 (a) and 4(b) shown in, by a patterning processes, the substrate of described pixel region 10a is at least formed source electrode 1041 and drain electrode 1042, the pixel electrode 106 be electrically connected with described drain electrode 1042, is positioned at the second transparency electrode 106a be electrically connected above described source electrode 1041 and with described source electrode 1041, on the substrate of described GOA district 10b, formation to be positioned at above described second electrode 104b and the first transparency electrode 106b be all electrically connected with described second electrode 104b and described first electrode 101b.
Here, when described first pattern 103a comprises metal-oxide film, in step s 102, described first pattern 103a is the pattern 103 of described active layer; When described first pattern 103a comprises amorphous silicon membrane and n+ amorphous silicon membrane, in step s 103, after the n+ amorphous silicon membrane of described first pattern 103a corresponding to gap between described source electrode 1041 and drain electrode 1042 is etched, just can form the pattern 103 of described active layer; Now, the pattern 103 of described active layer comprises amorphous silicon pattern and n+ amorphous silicon pattern.
In the embodiment of the present invention, be positioned at the grid 101a of described pixel region 10a by a patterning processes formation, be positioned at first electrode of described GOA district 10b, the pattern 102 being positioned at the gate insulation layer of described pixel region 10a and described GOA district 10b is formed by other twice patterning processes, be positioned at the pattern 103 of the active layer of described pixel region 10a, source electrode 1041 and drain electrode 1042, be positioned at the second transparency electrode 106a be electrically connected above described source electrode and with described source electrode 1041, the pixel electrode 106 be electrically connected with described drain electrode 1042, and described in be positioned at GOA district 10b and described active layer pattern 103 retain pattern 103b with the active layer of floor, with described source electrode 1041 with drain 1042 with the second electrode 104b of layer, to be positioned at above described second electrode 104b and the first transparency electrode 106b be all electrically connected with described second electrode 104b and described first electrode 101b, wherein, described first transparency electrode 106b is electrically connected with described first electrode 101b by via hole 105b, described active layer retains pattern 103b and described second electrode 104b and includes the described via hole 105b exposing described first electrode 101b.The embodiment of the present invention just can form TFT structure on array base palte and GOA structure by means of only 3 patterning processes, and pixel electrode, effectively reduces the number of times of patterning processes, thus can promote the production capacity of volume production product, reduce costs.
Optionally, if in above-mentioned S102, described first pattern 103a comprises amorphous silicon membrane 12a and n+ amorphous silicon membrane 12b, and on this basis, described S102 specifically comprises:
Form gate insulation layer film 11, amorphous silicon membrane 12a and n+ amorphous silicon membrane 12b and metallic film 13 successively on the substrate, and form photoresist 30 on described metallic film 13.
Adopt intermediate tone mask plate 20 or gray tone mask plate to after being formed with the base board to explosure of described photoresist 30, development, form the complete reserve part 301 of photoresist, photoresist half reserve part 302 and photoresist and remove part 303 completely; Wherein, the to be formed via hole 105b exposing described first electrode 101b that part 303 correspondence is positioned at described GOA district 10b removed completely by described photoresist; Described photoresist complete reserve part 301 correspondence be positioned at described pixel region 10a described first pattern 103a to be formed and be positioned at the described second pattern 104a above described first pattern 103a and be positioned at the to be formed of described GOA district 10b and described first pattern 103a with the described active layer of floor retain pattern 103b and with the described second electrode 104b of described second pattern 104a with floor; Described photoresist half reserve part 302 other regions corresponding.
Adopt etching technics to remove described photoresist and remove the described metallic film 13 of part 303, described n+ amorphous silicon membrane 12b, described amorphous silicon membrane 12a and described gate insulation layer film 11 completely, form the via hole 105b exposing described first electrode 101b.
Cineration technics is adopted to remove the photoresist 30 of described photoresist half reserve part 302.
Etching technics is adopted to remove the described metallic film 13 exposed, described n+ amorphous silicon membrane 12b and described amorphous silicon membrane 12a, form described first pattern 103a and described second pattern 104a, and with described first pattern 103a with the described active layer of layer retain pattern 103b and with the described second electrode 104b of described second pattern 104a with layer, and described active layer retains pattern 103b and described second electrode 104b includes the via hole 105b exposing described first electrode 101b; Wherein, the pattern 103 of the corresponding described active layer of described first pattern 103a, the corresponding described source electrode 1041 of described second pattern 104a and drain electrode 1042.
Stripping technology is adopted to remove the photoresist 30 of the complete reserve part 301 of described photoresist.
It should be noted that, above-mentioned film forming method can be the methods such as deposition, coating, sputtering.
In addition, because described first electrode 101b and described grid 101a is formed by a patterning processes, generally can select identical metal material, and the above-mentioned metallic film 13 be positioned at below described photoresist 30 is also metal material; In process prepared by reality, these two kinds of metal materials can be identical, also can not be identical.Like this, because first described first electrode 101b is formed by etching, and before the metallic film 13 of described photoresist half reserve part 302 correspondence is carried out etching to form described second pattern 104a, outside described first electrode 101b has been exposed to by described via hole 105b, therefore, just need when etching and forming described second pattern 104a to consider the following two kinds situation:
First, when described first electrode 101b is not identical with the metal material of above-mentioned metallic film 13, removed the photoresist 30 of described photoresist half reserve part 302 by cineration technics after, selectivity should be had for the etching liquid etching the metallic film 13 exposed corresponding with described photoresist half reserve part 302 to metal material; That is, only to the metal material at described metallic film 13 place of exposing, there is corrasion, corrasion do not had to the metal material of described first electrode 101b.
Second, when described first electrode 101b is identical with the metal material of above-mentioned metallic film 13, one deck such as ITO transparent conductive film can be set above described first electrode 101b, with prevent etch described in expose metallic film 13 time, the described first electrode 101b of same material is also etched away.
On this basis, further alternative, described S103 specifically comprises:
Substrate forms transparent conductive film, and form photoresist 30 on described transparent conductive film.
By mask plate to after being formed with the base board to explosure of described photoresist 30, development, etching, stripping, the substrate of described pixel region 10a is formed the pattern 103 of described active layer, described source electrode 1041 and drain electrode 1042, the pixel electrode 106 be electrically connected with described drain electrode 1042, is positioned at the second transparency electrode 106a be electrically connected above described source electrode 1041 and with described source electrode 1041; The substrate of described GOA district 101b is formed and to be positioned at above described second electrode 104b and the first transparency electrode 106b be all electrically connected with described second electrode 104b and described first electrode 101b; Wherein, the pattern 103 of described active layer comprises amorphous silicon pattern and n+ amorphous silicon pattern.
Here, after forming described source electrode 1041 and drain electrode 1042 by etching, also need to etch the n+ amorphous silicon membrane 12b of the described first pattern 103a corresponding with the gap between described source electrode 1041 and described drain electrode 1042, thus form the pattern 103 of described active layer.
The preparation method comprising the array base palte of GOA structure described in a specific embodiment a pair is provided to be described below:
S201, with reference to shown in figure 2, described underlay substrate 100 forms layer of metal film, by a patterning processes process, the underlay substrate 100 of described pixel region 10a forms grid 101a, the underlay substrate 100 of described GOA district 10b forms the first electrode 101b.
Concrete, can magnetically controlled sputter method be used, prepare a layer thickness on the glass substrate and exist
extremely
copper metal film.Then undertaken by patterning processes process such as exposure, development, etching, strippings by mask plate, the underlay substrate 100 of described pixel region 10a is formed described grid 101a, the underlay substrate 100 of described GOA district 10b is formed described first electrode 101b, certainly, also form grid line, grid line lead-in wire etc. simultaneously.
S202, as shown in Fig. 5 (a), the substrate of completing steps S201 forms gate insulation layer film 11, amorphous silicon membrane 12a and n+ amorphous silicon membrane 12b and molybdenum film 13 successively, and form photoresist 30 on described molybdenum film 13.
Concrete, chemical vapour deposition technique can be utilized first on the substrate being formed with grid 101a and the first electrode 101b patterned layer, to deposit a layer thickness and to be about
extremely
gate insulation layer film 11, the material normally silicon nitride of described gate insulation layer film 11, also can use silica and silicon oxynitride etc.; Be about by chemical vapour deposition technique deposit thickness on aforesaid substrate again
extremely
amorphous silicon membrane 12a and n+ amorphous silicon membrane 12b; And then on aforesaid substrate, deposit a layer thickness be about
arrive
molybdenum film 13, and apply one deck photoresist 30 on described molybdenum film 13.
S203, as shown in Fig. 5 (b), adopt intermediate tone mask plate 20 to after being formed with the base board to explosure of described photoresist 30, development, form the complete reserve part 301 of photoresist, photoresist half reserve part 302 and photoresist and remove part 303 completely.
Wherein, described photoresist complete reserve part 301 correspondence be positioned at described pixel region 10a described first pattern 103a to be formed and be positioned at the described second pattern 104a above described first pattern 103a and be positioned at the to be formed of described GOA district 10b and described first pattern 103a with the described active layer of floor retain pattern 103b and with the described second electrode 104b of described second pattern 104a with floor; The to be formed via hole 105b exposing described first electrode 101b that part 303 correspondence is positioned at described GOA district 10b removed completely by described photoresist; Described photoresist half reserve part 302 other regions corresponding.
Herein, with reference to figure 5(b) cardinal principle of described intermediate tone mask plate 20 is described as follows:
Described intermediate tone mask plate 20 is by grating effect, makes the intensity through light being exposed on zones of different different, thus makes described photoresist 30 carry out selectivity exposure, development.Described intermediate tone mask plate 20 comprises opaque section 201, translucent portion 202 and transparent part 203.Described photoresist 30 is after overexposure, the opaque section 201 of the corresponding described intermediate tone mask plate of the complete reserve part of described photoresist 301, the translucent portion 202 of the corresponding described intermediate tone mask plate of described photoresist half reserve part 302, the transparent part 203 of the corresponding described intermediate tone mask plate of part 303 removed completely by described photoresist.
Principle and the described intermediate tone mask plate 20 of described gray tone mask plate 20 are similar, do not repeat them here.
Wherein, in all embodiments of the present invention, the described photoresist 30 of indication is positive photoresist, namely in described intermediate tone mask plate 20, the region that part 303 correspondence removed completely by described photoresist is complete exposure area, and the material of corresponding described intermediate tone mask plate 20 is light transmissive material; The region of described photoresist half reserve part 302 correspondence is half exposure area, the material of corresponding described intermediate tone mask plate 20 is semi transparent material, the region of described photoresist complete reserve part 301 correspondence is not exposure area, and the material of corresponding described intermediate tone mask plate 20 is light-proof material.
S204, as shown in Fig. 5 (c), adopt etching technics to remove described photoresist and remove the described molybdenum film 13 of part 303, described n+ amorphous silicon membrane 12b and described amorphous silicon membrane 12a and described gate insulation layer film 11 completely, form the pattern 102 of gate insulation layer and expose the via hole 105b of described first electrode 101b.
Here, the etching technics adopted can comprise dry quarter and wet etching.Wherein, dry quarter or wet etching is adopted when etching described molybdenum film 13; Adopt dry quarter when etching described n+ amorphous silicon membrane 12b and described amorphous silicon membrane 12a and described gate insulation layer film 11, and this dry carving technology can be realized by same gas.
S205, as shown in Fig. 5 (d), cineration technics is adopted to remove the photoresist 30 of described photoresist half reserve part 302.
Because the photoresist 30 of the complete reserve part of described photoresist 301 is thicker than the thickness of the photoresist 30 of described photoresist half reserve part 302, therefore after being removed by the photoresist of described photoresist half reserve part 302, the complete reserve part 301 of described photoresist also has part photoresist to stay on the substrate.Now, outside the molybdenum film 13 of described photoresist half reserve part 302 correspondence is exposed to.
S206, as shown in Figure 5 (e) shows, etching technics is adopted to remove the described molybdenum film 13 exposed, and described n+ amorphous silicon membrane 12b below described molybdenum film 13 and described amorphous silicon membrane 12a, form described first pattern 103a at described pixel region 10a and be positioned at the described second pattern 104a above described first pattern 103a, described GOA district 10b formed with described first pattern 103a with the active layer of floor retain pattern 103b and with the described second electrode 104b of described second pattern 104a with floor, described active layer retains pattern 103b and described second electrode 104b and includes the described via hole 105b exposing described first electrode 101b.
Wherein, the pattern 103 of the corresponding described active layer of described first pattern 103a, comprises amorphous silicon membrane 12a and n+ amorphous silicon membrane 12b is two-layer; The corresponding described source electrode 1041 of described second pattern 104a and drain electrode 1042.
Here, wet-etching technique can be adopted to etch described molybdenum film 13, adopt dry quarter to etch described n+ amorphous silicon membrane 12b and described amorphous silicon membrane 12a.
S207, employing stripping technology remove the photoresist 30 of the complete reserve part 301 of described photoresist, obtain with reference to the structure shown in figure 3.
Above step S202 ~ S207 is by a patterning processes process, the substrate of described pixel region 10a and described GOA district 10b is formed the pattern 102 of gate insulation layer, the substrate of described pixel region 10a is formed described first pattern 103a and is positioned at the described second pattern 104a above described first pattern 103a, the substrate of described GOA district 10b is formed and retains pattern 103b with described first pattern 103a with the described active layer of floor, with the described second electrode 104b of described second pattern 104a with layer, and described active layer reservation pattern 103b and the second electrode 104b includes the described via hole 105b exposing described first electrode 101b.
S208, as shown in Figure 6 (a), the substrate of completing steps S207 forms ito thin film, and form photoresist 30 on described ito thin film.
Concrete, chemical vapour deposition technique first can be utilized on whole substrate to deposit a layer thickness and to be about
extremely
ito thin film, then on described ito thin film, apply one deck photoresist 30.
Here, other transparent conductive films can also be used to carry out alternative described ito thin film; Wherein conventional transparent conductive film also comprises indium zinc oxide (IndiumZincOxide is called for short IZO) conductive film.
S209, as shown in Figure 6 (b), adopts mask plate to the base board to explosure, the development that are formed with described photoresist 30, forms the complete reserve part 301 of photoresist and part 303 removed completely by photoresist.
Wherein, the corresponding pixel electrode 106 to be formed of described photoresist complete reserve part 301, be positioned at the second transparency electrode 106a above source electrode 1041 to be formed and be positioned at the first transparency electrode 106b be electrically connected with described first electrode 101b above described second electrode 104b and by the via hole 105b exposing described first electrode 101b; Part 303 other regions corresponding removed completely by described photoresist.
S210, as shown in Figure 6 (c), adopt etching technics to remove described photoresist and remove the described ito thin film of part 303 and the molybdenum film 13 of described second pattern 104a completely, form described source electrode 1041 and drain electrode 1042, the pixel electrode 106 be electrically connected with described drain electrode 1042, be positioned at the second transparency electrode 106a of being electrically connected above described source electrode 1041 and with described source electrode 1041 and be positioned at above described second electrode 104b and the first transparency electrode 106b be all electrically connected with described second electrode 104b and described first electrode 101b.
S211, as shown in Fig. 6 (d), adopt etching technics to remove the n+ amorphous silicon membrane 12b of described first pattern 103a corresponding to gap between described source electrode 1041 and described drain electrode 1042, thus be formed with the pattern 103 of active layer.Wherein, the pattern 103 of described active layer comprises amorphous silicon pattern and n+ amorphous silicon pattern.
S212, adopt stripping technology to remove the photoresist 30 of the complete reserve part 301 of described photoresist, obtain with reference to figure 4(a) shown in structure.
Above step S208 ~ S212 is by a patterning processes process, the substrate of described pixel region 10a is formed described source electrode 1041 and drain electrode 1042, be positioned at the pattern 103 of the active layer below described source electrode 1041 and drain electrode 1042, the pixel electrode 106 be electrically connected with described drain electrode 1042, be positioned at the second transparency electrode 106a be electrically connected above described source electrode 1041 and with described source electrode 1041, the substrate of described GOA district 10b is formed and to be positioned at above described second electrode 104b and the first transparency electrode 106b be all electrically connected with described second electrode 104b and described first electrode 101b.
In embodiments of the present invention, just form TFT structure on array base palte and GOA structure by 3 patterning processes, and pixel electrode, effectively reduce the number of times of patterning processes, thus the production capacity of volume production product can be promoted, reduce costs.
The array base palte that the embodiment of the present invention provides goes for the production of the liquid crystal indicator of the type such as senior super dimension field conversion hysteria, twisted-nematic (TwistNematic is called for short TN) type.Wherein, senior super dimension field switch technology, the electric field that its core technology characteristic description is produced for: the electric field produced by gap electrode edge in same plane and gap electrode layer and plate electrode interlayer forms multi-dimensional electric field, make in liquid crystal cell that between gap electrode, directly over electrode, all aligned liquid-crystal molecules can both produce rotation, thus improve liquid crystal operating efficiency and increase light transmission efficiency.Senior super dimension field switch technology can improve the picture quality of TFT LCD panel, have high-resolution, high permeability, low-power consumption, wide viewing angle, high aperture, low aberration, without advantages such as water of compaction ripples.
Therefore, on the basis of step S212, described preparation method also comprises:
S213, as shown in Figure 7, the substrate of described pixel region 10a and described GOA district 10b forms the pattern 107 of passivation layer.
S214, as shown in Figure 8, the substrate of described pixel region 10a forms public electrode 108.
It should be noted that, described public electrode 108 and the described pixel electrode 106 of described senior super dimension field conversion hysteria array base palte are all arranged on described array base palte.In the case, the described pixel electrode 106 being positioned at below can be tabular, and the described public electrode 108 being positioned at top can be strip; Also can be positioned at below pixel electrode 106 also in strip.
Optionally, if in above-mentioned S102, described first pattern 103a is metal-oxide film, and on this basis, described S102 specifically comprises:
Form gate insulation layer film 11, metal-oxide film and metallic film 13 successively on the substrate, and form photoresist 30 on described metallic film 13.
Adopt intermediate tone mask plate 20 or gray tone mask plate to after being formed with the base board to explosure of described photoresist 30, development, form the complete reserve part 301 of photoresist, photoresist half reserve part 302 and photoresist and remove part 303 completely; Wherein, the to be formed via hole 105b exposing described first electrode 101b that part 303 correspondence is positioned at described GOA district 10b removed completely by described photoresist; Described photoresist complete reserve part 301 correspondence be positioned at described pixel region 10a described first pattern 103a to be formed and be positioned at the described second pattern 104a above described first pattern 103a and be positioned at the to be formed of described GOA district 10b and described first pattern 103a with the described active layer of floor retain pattern 103b and with the described second electrode 104b of described second pattern 104a with floor; Described photoresist half reserve part 302 other regions corresponding.
Adopt etching technics to remove described photoresist and remove the described metallic film 13 of part 303, described metal-oxide film and described gate insulation layer film 11 completely, form the via hole 105b exposing described first electrode 101b.
Cineration technics is adopted to remove the photoresist 30 of described photoresist half reserve part 302.
Etching technics is adopted to remove the described metallic film 13, the described metal-oxide film that expose, form described first pattern 103a and described second pattern 104a, and with described first pattern 103a with the described active layer of layer retain pattern 103b and with the described second electrode 104b of described second pattern 104a with layer; Wherein, described active layer reservation pattern 103b and described second electrode 104b includes the via hole 105b exposing described first electrode 101b; Wherein, described first pattern 103a is the pattern 103 of described active layer, the corresponding described source electrode 1041 of described second pattern 103b and drain electrode 1042.
Stripping technology is adopted to remove the photoresist 30 of the complete reserve part 301 of described photoresist.
On this basis, further alternative, described S103 specifically comprises:
Substrate forms transparent conductive film, and form photoresist 30 on described transparent conductive film.
By mask plate to after being formed with the base board to explosure of described photoresist 30, development, etching, stripping, the substrate of described pixel region 10a is formed described source electrode 1041 and drain electrode 1042, the pixel electrode 106 be electrically connected with described drain electrode 1042, is positioned at the second transparency electrode 106a be electrically connected above described source electrode 1041 and with described source electrode 1041; The substrate of described GOA district 101b is formed and to be positioned at above described second electrode 104b and the first transparency electrode 106b be all electrically connected with described second electrode 104b and described first electrode 101b.
The preparation method of a specific embodiment two to the array base palte of the described GOA of comprising structure is provided to be described below:
S301, on described underlay substrate 100, form copper metal film, by a patterning processes process, the underlay substrate 100 of described pixel region 10a forms grid 101a, the underlay substrate 100 of described GOA district 10b forms the first electrode 101b.
S302, on the substrate of completing steps S201, form gate insulation layer film 11, metal-oxide film and molybdenum film 13 successively, and form photoresist 30 on described molybdenum film 13.
S303, adopt intermediate tone mask plate 20 to after being formed with the base board to explosure of described photoresist 30, development, form the complete reserve part 301 of photoresist, photoresist half reserve part 302 and photoresist and remove part 303 completely.
Wherein, the to be formed via hole 105b exposing described first electrode 101b that part 303 correspondence is positioned at described GOA district 10b removed completely by described photoresist; Described photoresist complete reserve part 301 correspondence be positioned at described pixel region 10a described first pattern 103a to be formed and be positioned at the described second pattern 104a above described first pattern 103a and be positioned at the to be formed of described GOA district 10b and described first pattern 103a with the described active layer of floor retain pattern 103b and with the described second electrode 104b of described second pattern with floor 104a; Described photoresist half reserve part 302 other regions corresponding.
S304, employing etching technics are removed described photoresist and are removed the described molybdenum film 13 of part 303, described metal-oxide film and described gate insulation layer film 11 completely, form the pattern 102 of gate insulation layer and expose the via hole 105b of described first electrode 101b.
S305, employing cineration technics remove the photoresist 30 of described photoresist half reserve part 302.
S306, etching technics is adopted to remove described metal-oxide film below the described molybdenum film 13 and described molybdenum film 13 that expose, form described first pattern 103a at described pixel region 10a and be positioned at the described second pattern 104a above described first pattern 103a, described GOA district 10b formed with described first pattern 103a with the active layer of floor retain pattern 103b and with the described second electrode 104b of described second pattern 104a with floor, described active layer retains pattern 103b and described second electrode 104b and includes the via hole 105b exposing described first electrode 101b.
Wherein, described first pattern 103a is the pattern 103 of described active layer, and the pattern 103 of active layer described in it comprises metal oxide pattern; The corresponding described source electrode 1041 of described second pattern 104a and drain electrode 1042.
S307, employing stripping technology remove the photoresist 30 of the complete reserve part 301 of described photoresist, obtain with reference to the structure shown in figure 3.
S308, on the substrate of completing steps S307, form ito thin film, and form photoresist 30 on described ito thin film.
S309, adopt mask plate to after being formed with the base board to explosure of described photoresist 30, development, etching, formed be positioned at described active layer pattern 103 above source electrode 1041 and drain electrode 1042, the pixel electrode 106 be electrically connected with described drain electrode 1042, be positioned at the second transparency electrode 106a of being electrically connected above described source electrode 1041 and with described source electrode 1041 and to be positioned at above described second electrode 104b and with the first transparency electrode 106b that described second electrode 104b and described first electrode 101b are all electrically connected, obtain the structure as shown in figure Fig. 4 (b).
Further, on the basis of step S309, described preparation method also comprises:
S310, on the substrate of described pixel region 10a and described GOA district 10b, form the pattern 107 of passivation layer.
S311, on the substrate of described pixel region 10a, form public electrode 108.
The embodiment of the present invention additionally provides a kind of array base palte utilizing said method to prepare, with reference to figure 4(a) and Fig. 4 (b) shown in, this array base palte comprises pixel region 10a and GOA district 10b; Described pixel region 10a comprises the grid 101a be arranged on substrate, the pattern 103 of active layer, source electrode 1041 and drain electrode 1042, the pixel electrode 106 that is electrically connected with described drain electrode 1042, and the pattern 102 of gate insulation layer is arranged on described pixel region 10a and described GOA district 10b; Described array base palte further comprises: be arranged on described GOA district 10b and described grid 101a with floor the first electrode 101b, with the pattern 103 of described active layer with the active layer of floor retains pattern 103b, with described source electrode 1041 and drain 1042 with floor the second electrode 104b, and described pixel electrode 106 with the first transparency electrode 106b of floor.
Wherein, described active layer reservation pattern 103b and described second electrode 104b includes the via hole 105b exposing described first electrode 101b; Described first transparency electrode 106b to be arranged on above described second electrode 104b and to be all electrically connected with described second electrode 104b and described first electrode 101b; Described pixel region 10a also comprise to be arranged on above described source electrode 1041 and with the second transparency electrode 106a of described pixel electrode 106 with layer, described second transparency electrode 106a is electrically connected with described source electrode 1041.
Optionally, with reference to figure 4(a), the pattern 103 of described active layer comprises amorphous silicon pattern and n+ amorphous silicon pattern; Or with reference to figure 4(b) shown in, the pattern 103 of described active layer comprises metal oxide pattern.
When the pattern 103 of described active layer comprises amorphous silicon pattern and n+ amorphous silicon pattern, described active layer retains pattern 103b and comprises amorphous silicon reservation pattern and n+ amorphous silicon reservation pattern; When the pattern 103 of described active layer comprises metal oxide pattern, described active layer retains pattern 103b and comprises metal oxide reservation pattern.
Further, shown in figure 8, described array base palte also comprises the pattern 107 of the passivation layer being arranged on described pixel region 10a and described GOA district 10b and is arranged on the public electrode 108 of described pixel region 10a.
For senior super dimension field conversion hysteria array base palte, described public electrode 108 is all arranged on described array base palte with described pixel electrode 106, and the multi-dimensional electric field by being formed in same plane, the liquid crystal molecule of all orientations in liquid crystal cell can be made all to produce rotation, thus improve the operating efficiency of liquid crystal and increase light transmittance.Senior super dimension field switch technology can improve the picture quality of display floater, have high-resolution, high permeability, low-power consumption, wide viewing angle, high aperture, low aberration, without advantages such as water of compaction ripples.
The embodiment of the present invention additionally provides a kind of display unit, comprises above-mentioned array base palte.
Although in above-described embodiment, 1042 be connected to example and be illustrated with pixel electrode 106 to drain, but those skilled in the art is understood that, due to source electrode 1041 and the interchangeability of drain electrode 1042 in structure and composition of transistor, also source electrode 1041 can be connected with pixel electrode 106, this belongs to the equivalents of the above embodiment of the present invention.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (6)
1. a preparation method for array base palte, described array base palte comprises pixel region and GOA district; It is characterized in that, comprising:
By a patterning processes, the underlay substrate of described pixel region forms grid, the underlay substrate in described GOA district forms the first electrode;
By a patterning processes, the substrate in described pixel region and described GOA district is formed the pattern of gate insulation layer, the substrate of described pixel region is formed the first pattern and is positioned at the second pattern above described first pattern, the substrate in described GOA district is formed with described first pattern with the active layer of floor retains pattern, with second electrode of described second pattern with floor, and described active layer reservation pattern and described second electrode include the via hole exposing described first electrode; Wherein, the pattern of the corresponding active layer of described first pattern, the corresponding source electrode of described second pattern and drain electrode;
By a patterning processes, the substrate of described pixel region is at least formed described source electrode and drain electrode, with described drain be electrically connected pixel electrode, be positioned at the second transparency electrode be electrically connected above described source electrode and with described source electrode, the substrate in described GOA district is formed and to be positioned at above described second electrode and the first transparency electrode be all electrically connected with described second electrode and described first electrode.
2. method according to claim 1, it is characterized in that, describedly pass through a patterning processes, the substrate in described pixel region and described GOA district is formed the pattern of gate insulation layer, the substrate of described pixel region is formed the first pattern and is positioned at the second pattern above described first pattern, the substrate in described GOA district is formed with described first pattern with the active layer of floor retains pattern, with second electrode of described second pattern with floor, and described active layer reservation pattern and described second electrode include the via hole exposing described first electrode; Wherein, the pattern of the corresponding active layer of described first pattern, the corresponding source electrode of described second pattern and drain electrode comprise:
Form gate insulation layer film, amorphous silicon membrane and n+ amorphous silicon membrane and metallic film successively on the substrate, and form photoresist on described metallic film;
Adopt intermediate tone mask plate or gray tone mask plate to after being formed with the base board to explosure of described photoresist, development, form the complete reserve part of photoresist, photoresist half reserve part and photoresist and remove part completely; Wherein, the to be formed via hole exposing described first electrode that part correspondence is positioned at described GOA district removed completely by described photoresist; Described photoresist complete reserve part correspondence be positioned at described pixel region described first pattern to be formed and be positioned at described second pattern above described first pattern and be positioned at the to be formed of described GOA district and described first pattern with the described active layer of floor retain pattern and with described second electrode of described second pattern with floor; Described photoresist half reserve part other regions corresponding;
Adopt etching technics to remove the described metallic film of described photoresist removal part completely, described n+ amorphous silicon membrane, described amorphous silicon membrane and described gate insulation layer film, form the via hole exposing described first electrode;
Cineration technics is adopted to remove the photoresist of described photoresist half reserve part;
Etching technics is adopted to remove the described metallic film exposed, described n+ amorphous silicon membrane and described amorphous silicon membrane, form described first pattern and described second pattern, and with described first pattern with the described active layer of layer retain pattern and with described second electrode of described second pattern with layer; Wherein, described active layer reservation pattern and described second electrode include the described via hole exposing described first electrode; The pattern of the corresponding described active layer of described first pattern, the corresponding described source electrode of described second pattern and drain electrode;
Stripping technology is adopted to remove the photoresist of the complete reserve part of described photoresist.
3. method according to claim 2, it is characterized in that, describedly pass through a patterning processes, the substrate of described pixel region is at least formed described source electrode and drain electrode, with described drain be electrically connected pixel electrode, be positioned at the second transparency electrode be electrically connected above described source electrode and with described source electrode, the substrate in described GOA district is formed and to be positioned at above described second electrode and to comprise with the first transparency electrode that described second electrode and described first electrode are all electrically connected:
Substrate forms transparent conductive film, and form photoresist on described transparent conductive film;
By mask plate to after being formed with the base board to explosure of described photoresist, development, etching, stripping, the substrate of described pixel region is formed the pattern of described active layer, described source electrode and drain electrode, with described drain be electrically connected pixel electrode, be positioned at the second transparency electrode be electrically connected above described source electrode and with described source electrode, the substrate in described GOA district is formed and to be positioned at above described second electrode and the first transparency electrode be all electrically connected with described second electrode and described first electrode; Wherein, the pattern of described active layer comprises amorphous silicon pattern and n+ amorphous silicon pattern.
4. method according to claim 1, it is characterized in that, describedly pass through a patterning processes, the substrate in described pixel region and described GOA district is formed the pattern of gate insulation layer, the substrate of described pixel region is formed the first pattern and is positioned at the second pattern above described first pattern, the substrate in described GOA district is formed with described first pattern with the active layer of floor retains pattern, with second electrode of described second pattern with floor, and described active layer reservation pattern and described second electrode include the via hole exposing described first electrode; Wherein, the pattern of the corresponding active layer of described first pattern, the corresponding source electrode of described second pattern and drain electrode comprise:
Form gate insulation layer film, metal-oxide film and metallic film successively on the substrate, and form photoresist on described metallic film;
Adopt intermediate tone mask plate or gray tone mask plate to after being formed with the base board to explosure of described photoresist, development, form the complete reserve part of photoresist, photoresist half reserve part and photoresist and remove part completely; Wherein, the to be formed via hole exposing described first electrode that part correspondence is positioned at described GOA district removed completely by described photoresist; Described photoresist complete reserve part correspondence be positioned at described pixel region described first pattern to be formed and be positioned at described second pattern above described first pattern and be positioned at the to be formed of described GOA district and described first pattern with the described active layer of floor retain pattern and with described second electrode of described second pattern with floor; Described photoresist half reserve part other regions corresponding;
Adopt etching technics to remove the described metallic film of described photoresist removal part completely, described metal-oxide film and described gate insulation layer film, form the via hole exposing described first electrode;
Cineration technics is adopted to remove the photoresist of described photoresist half reserve part;
Etching technics is adopted to remove the described metallic film, the described metal-oxide film that expose, form described first pattern and described second pattern, and with described first pattern with the described active layer of layer retain pattern and with described second electrode of described second pattern with layer; Wherein, described active layer reservation pattern and described second electrode include the described via hole exposing described first electrode; Described first pattern is the pattern of described active layer, the corresponding described source electrode of described second pattern and drain electrode;
Stripping technology is adopted to remove the photoresist of the complete reserve part of described photoresist.
5. method according to claim 4, it is characterized in that, describedly pass through a patterning processes, the substrate of described pixel region is at least formed described source electrode and drain electrode, with described drain be electrically connected pixel electrode, be positioned at the second transparency electrode be electrically connected above described source electrode and with described source electrode, the substrate in described GOA district is formed and to be positioned at above described second electrode and to comprise with the first transparency electrode that described second electrode and described first electrode are all electrically connected:
Substrate forms transparent conductive film, and form photoresist on described transparent conductive film;
By mask plate to after being formed with the base board to explosure of described photoresist, development, etching, stripping, the substrate of described pixel region is formed described source electrode and drain electrode, with described drain be electrically connected pixel electrode, be positioned at the second transparency electrode be electrically connected above described source electrode and with described source electrode, the substrate in described GOA district is formed and to be positioned at above described second electrode and the first transparency electrode be all electrically connected with described second electrode and described first electrode.
6. the method according to any one of claim 1 to 5, is characterized in that, described method also comprises: the pattern forming passivation layer on the substrate in described pixel region and described GOA district; The substrate of described pixel region also forms public electrode.
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| CN104538411A (en) * | 2015-01-22 | 2015-04-22 | 京东方科技集团股份有限公司 | Array substrate, manufacture method of array substrate, and display device |
| CN106206603A (en) * | 2016-07-19 | 2016-12-07 | 京东方科技集团股份有限公司 | A kind of array base palte, its manufacture method, display floater and display device |
| CN106019672A (en) * | 2016-07-26 | 2016-10-12 | 武汉华星光电技术有限公司 | Making method for thin film transistor array substrate |
| CN107170753B (en) * | 2017-05-10 | 2020-04-07 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display device |
| CN109659312B (en) * | 2018-10-15 | 2021-02-26 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and preparation method thereof |
| CN109976049A (en) * | 2019-04-08 | 2019-07-05 | 深圳市华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
| CN110120367B (en) * | 2019-04-09 | 2022-03-01 | 昆山龙腾光电股份有限公司 | Manufacturing method of thin film transistor and thin film transistor |
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| CN103021944A (en) * | 2012-12-21 | 2013-04-03 | 北京京东方光电科技有限公司 | TFT (thin-film transistor) array substrate, manufacturing method of TFT array substrate, and display device with TFT array substrate |
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| CN103021944A (en) * | 2012-12-21 | 2013-04-03 | 北京京东方光电科技有限公司 | TFT (thin-film transistor) array substrate, manufacturing method of TFT array substrate, and display device with TFT array substrate |
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