CN104538411A - Array substrate, manufacture method of array substrate, and display device - Google Patents
Array substrate, manufacture method of array substrate, and display device Download PDFInfo
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- CN104538411A CN104538411A CN201510032699.4A CN201510032699A CN104538411A CN 104538411 A CN104538411 A CN 104538411A CN 201510032699 A CN201510032699 A CN 201510032699A CN 104538411 A CN104538411 A CN 104538411A
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Abstract
The embodiment of the invention discloses an array substrate, a manufacture method of the array substrate, and a display device, and relates to the technical field of display; the invalidation of a pixel electrode can be prevented; the array substrate comprises a substrate, a thin-film transistor and the pixel electrode, wherein the thin-film transistor and the pixel electrode are arranged on the substrate; the drain electrode of the thin-film transistor comprises at least two conductive layers overlapped with each other, wherein except one conductive layer farthest from the substrate, at least one conductive layer is made of aluminium; the pixel electrode is made of indium tin oxide; the pixel electrode is electrically connected with one conductive layer, farthest from the substrate, in the drain electrode; and an isolation layer is arranged between the side wall, near the pixel electrode, of the drain electrode and the pixel electrode.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of array base palte and preparation method thereof, display unit.
Background technology
High permeability senior super dimension field switch technology type (being called for short HADS) display unit, HADS display unit comprises array base palte, color membrane substrates and therebetween layer of liquid crystal molecule.
Particularly, as shown in Figure 1, the array base palte of HADS display unit comprises thin-film transistor, the pixel electrode 1 ' of tabular and the public electrode 2 ' of slit-shaped, wherein, thin-film transistor comprises grid 3 ', gate insulator 4 ', active layer 5 ', source electrode 6 ' and drain electrode 7 ', pixel electrode 1 ' is electrically connected with the drain electrode 7 ' of thin-film transistor, usually, the source electrode 6 ' of thin-film transistor and the material of drain electrode 7 ' are Mo/Al/Mo three-decker, and the material of pixel electrode 1 ' is tin indium oxide (ITO).
Inventor finds, in the manufacturing process of array base palte, pixel electrode 1 ' inevitably with the sidewall contact of the drain electrode 1 ' of thin-film transistor, and then contact with the Al layer in drain electrode 7 ', in the use procedure of array base palte, to displacement reaction be there is in Al and pixel electrode 1 ', be specially, In and Sn in pixel electrode 1 ' displaces by Al, thus affect the conductivity of pixel electrode 1 ', cause pixel electrode 1 ' to lose efficacy, and can not charge normal, and then it is bad to cause HADS display unit to occur.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of array base palte and preparation method thereof, display unit, and pixel electrode can be prevented to lose efficacy.
For solving the problems of the technologies described above, embodiments providing a kind of array base palte, adopting following technical scheme:
A kind of array base palte, the thin-film transistor comprising underlay substrate and be positioned on described underlay substrate and pixel electrode, the drain electrode of described thin-film transistor comprises at least two conductive layers of superposition mutually, wherein, except apart from except a described underlay substrate conductive layer farthest, the material of at least one conductive layer is aluminium, the material of described pixel electrode is tin indium oxide, described pixel electrode is electrically connected with the conductive layer farthest of underlay substrate described in described drain electrode middle distance, and described drain electrode is provided with separator near between the sidewall and described pixel electrode of described pixel electrode.
Described separator is insulating barrier, described separator covers whole described array base palte, described array base palte also comprises the via hole running through described separator, and described pixel electrode is electrically connected with the conductive layer farthest of underlay substrate described in described drain electrode middle distance by described via hole.
Described array base palte also comprises the passivation layer be positioned on described thin-film transistor and described pixel electrode, and is positioned at the public electrode on described passivation layer, and described public electrode is slit-shaped electrode or strip shaped electric poles.
Embodiments provide a kind of array base palte, this array base palte comprises thin-film transistor and pixel electrode, the drain electrode of thin-film transistor is provided with separator near between the sidewall and pixel electrode of pixel electrode, thus the pixel electrode that can to prevent material in the drain electrode of thin-film transistor from being conductive layer and the material of aluminium be tin indium oxide contacts, thus can prevent aluminium from the indium in pixel electrode and tin being displaced, thus the conductivity of pixel electrode can not be affected, prevent pixel electrode to lose efficacy, and then it is bad to avoid display unit to occur.
In addition, the embodiment of the present invention additionally provides a kind of display unit, and this display unit comprises the array base palte described in above any one.
In order to solve the problems of the technologies described above further, the embodiment of the present invention additionally provides the following technical scheme of a kind of employing:
A manufacture method for array base palte, comprising:
Underlay substrate forms thin-film transistor, and the drain electrode of described thin-film transistor comprises at least two conductive layers of superposition mutually, and wherein, except apart from except a described underlay substrate conductive layer farthest, the material of at least one conductive layer is aluminium;
Formed and comprise the figure of separator, described separator in described drain electrode near between the sidewall and pixel electrode of pixel electrode;
Form the figure comprising described pixel electrode, the material of described pixel electrode is tin indium oxide, and described pixel electrode is electrically connected with the conductive layer farthest of underlay substrate described in described drain electrode middle distance.
Described separator is insulating barrier, and described separator covers whole described array base palte.
Comprise the figure of separator in described formation, afterwards, comprising:
Through patterning processes, form the via hole running through described separator, described via hole is for being electrically connected a underlay substrate conductive layer farthest described in described pixel electrode and described drain electrode middle distance.
Described through patterning processes, form the via hole running through described separator, comprising:
Described separator is coated with one deck photoresist;
Half gray level mask plate is used to hide described photoresist, expose described photoresist, wherein, the described photoresist of described via hole corresponding position exposes entirely, described photoresist half exposure of described pixel electrode corresponding position, the described photoresist of other positions does not expose completely;
Develop to described photoresist, wherein, described via hole corresponding position forms photoresist and removes district completely, and described pixel electrode corresponding position forms photoresist part reserved area, and other positions described form the complete reserved area of photoresist;
Etch described separator, wherein, the described separator that place of district removed completely by described photoresist is etched away, and forms described via hole.
Described, described separator is etched, afterwards, also comprises:
Through cineration technics, remove the described photoresist at described photoresist part reserved area place, the described photoresist at described photoresist complete reserved area place still has residual;
Described formation comprises the figure of described pixel electrode, comprising:
Whole described array base palte forms indium oxide layer tin;
Peel off the described photoresist that described photoresist complete reserved area place is residual, the tin indium oxide that described photoresist covers is removed simultaneously, form the figure comprising described pixel electrode, described pixel electrode is electrically connected with the conductive layer farthest of underlay substrate described in described drain electrode middle distance by described via hole.
The manufacture method of described array base palte also comprises:
Described thin-film transistor and described pixel electrode form passivation layer;
Described passivation layer is formed the figure comprising public electrode, and described public electrode is slit-shaped electrode or strip shaped electric poles.
Embodiments provide a kind of manufacture method of array base palte, this manufacture method comprises the figure being formed and comprise separator, separator in described drain electrode near between the sidewall and pixel electrode of pixel electrode, thus the pixel electrode that can to prevent material in the drain electrode of thin-film transistor from being conductive layer and the material of aluminium be tin indium oxide contacts, thus can prevent aluminium from the indium in pixel electrode and tin being displaced, thus the conductivity of pixel electrode can not be affected, prevent pixel electrode to lose efficacy, and then it is bad to avoid display unit to occur.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of array base palte of the prior art;
Fig. 2 is the structural representation of the array base palte in the embodiment of the present invention;
Fig. 3 is the manufacture method flow chart of the array base palte in the embodiment of the present invention;
Fig. 4 is the structural representation of the array base palte after forming thin-film transistor in the embodiment of the present invention;
Fig. 5 is the structural representation of the array base palte after forming separator in the embodiment of the present invention;
Fig. 6 is the flow chart forming via hole in the embodiment of the present invention;
Fig. 7 is the structural representation of the array base palte after developing to photoresist in the embodiment of the present invention;
Fig. 8 is the structural representation of the array base palte after etching separator in the embodiment of the present invention;
Fig. 9 is the structural representation of the array base palte in the embodiment of the present invention after cineration technics;
Figure 10 is the flow chart forming pixel electrode in the embodiment of the present invention;
Figure 11 is the structural representation of the array base palte after forming tin indium oxide in the embodiment of the present invention;
Figure 12 is the structural representation of the array base palte after forming pixel electrode in the embodiment of the present invention.
Description of reference numerals:
1-underlay substrate; 2-grid; 3-gate insulator;
4-active layer; 5-source electrode; 6-drain electrode;
7-separator; 71-via hole; 8-pixel electrode;
9-passivation layer; 10-public electrode; 11-photoresist.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Embodiment one
Embodiments provide a kind of array base palte, pixel electrode can be prevented to lose efficacy.
Particularly, as shown in Figure 2, this array base palte comprises underlay substrate 1 and the thin-film transistor be positioned on underlay substrate 1 and pixel electrode 8, the drain electrode 6 of thin-film transistor comprises at least two conductive layers of superposition mutually, wherein, except distance underlay substrate 1 conductive layer farthest, the material of at least one conductive layer is aluminium, the material of pixel electrode 8 is tin indium oxide, pixel electrode 8 is electrically connected with drain electrode 6 middle distance underlay substrates 1 conductive layer farthest, drain electrode 6 is provided with separator 7 near between the sidewall and pixel electrode 8 of pixel electrode 8, thus can prevent material in drain electrode 6 from being that the conductive layer of aluminium contacts with pixel electrode 8, thus can prevent aluminium from the indium in pixel electrode 8 and tin being displaced, thus the conductivity of pixel electrode 8 can not be affected, pixel electrode 8 is prevented to lose efficacy, and then it is bad to avoid display unit to occur.
It should be noted that, as shown in Figure 2, above-described thin-film transistor comprises drain electrode 6, also comprises grid 2, gate insulator 3, active layer 4 and source electrode 5, and wherein, source electrode 5 and drain electrode 6 arrange with layer and formed simultaneously.Alternatively, source electrode 5 and drain electrode 6 are Mo/Al/Mo three-decker, and wherein, the thickness of one deck Mo layer that distance underlay substrate 1 is nearest is
the thickness of Al layer is
the thickness of distance underlay substrate 1 one deck Mo layer is farthest
in addition, alternatively, pixel electrode 8 thickness be
Further, separator 7 can be conductive layer or insulating barrier.When separator 7 is conductive layer, due to array base palte being also provided with other conductive structures, the normal function affecting other conductive structures is set in order to avoid separator 7, needs to carry out composition separately to separator 7, thus make the manufacturing process more complicated of array base palte; When separator 7 is insulating barrier, then can avoid the appearance of above-mentioned situation.Therefore, as shown in Figure 2, in the embodiment of the present invention, preferred separator 7 is insulating barrier, separator 7 covers whole array base palte, now, array base palte also comprises the via hole 71 running through separator 7, and pixel electrode 8 is electrically connected with drain electrode 6 middle distance underlay substrates 1 conductive layer farthest by via hole 71.Exemplarily, the material of separator 7 is silicon nitride or silica.
Further, in order to improve the transmitance of the display unit comprising this array base palte, the display unit preferably including this array base palte in the embodiment of the present invention is HADS display unit, now, as shown in Figure 2, array base palte also comprises the passivation layer 9 be positioned on thin-film transistor and pixel electrode 8, and is positioned at the public electrode 10 on passivation layer 9, and public electrode 10 is slit-shaped electrode or strip shaped electric poles.Exemplarily, the material of passivation layer 9 is identical with the material of separator 7, is silicon nitride or silica, and the material of public electrode 10 is identical with the material of pixel electrode 8, is tin indium oxide, to simplify the manufacturing process of array base palte.
Embodiments provide a kind of array base palte, this array base palte comprises thin-film transistor and pixel electrode, the drain electrode of thin-film transistor is provided with separator near between the sidewall and pixel electrode of pixel electrode, thus the pixel electrode that can to prevent material in the drain electrode of thin-film transistor from being conductive layer and the material of aluminium be tin indium oxide contacts, thus can prevent aluminium from the indium in pixel electrode and tin being displaced, thus the conductivity of pixel electrode can not be affected, prevent pixel electrode to lose efficacy, and then it is bad to avoid display unit to occur.
In addition, the embodiment of the present invention additionally provides a kind of display unit, and this display unit comprises the array base palte described in above any one.This display unit can be: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, organic electroluminescence display panel, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.Exemplarily, the display unit in the embodiment of the present invention is HADS display unit.
Embodiment two
Embodiments provide the manufacture method making the array base palte described in embodiment one, particularly, as shown in Figure 3, the manufacture method of this array base palte comprises:
Step S301, on underlay substrate 1, form thin-film transistor.
Wherein, the drain electrode 6 of thin-film transistor comprises at least two conductive layers of superposition mutually, and wherein, except apart from except underlay substrate 1 conductive layer farthest, the material of at least one conductive layer is aluminium.After step S301, the structure of array base palte as shown in Figure 4.
Particularly, underlay substrate 1 forms thin-film transistor to comprise:
First, underlay substrate 1 forms gate metal layer, through patterning processes, form the figure comprising grid 2; Secondly, on the underlay substrate 1 defining the figure comprising grid 2, form gate insulator 3; Then, on the underlay substrate 1 defining gate insulator 3, form semiconductor layer, through patterning processes, form the figure including active layer 4; Finally, on the underlay substrate 1 defining the figure including active layer 4, form source-drain electrode metal level, through patterning processes, form the figure comprising source electrode 5 and drain electrode 6, to form thin-film transistor on underlay substrate 1.
It should be noted that, above-mentioned source-drain electrode metal level comprises at least two conductive film layers of mutually superposition, and wherein, except apart from except underlay substrate 1 conductive film layer farthest, the material of at least one conductive film layer is aluminium.
Step S302, formed and comprise the figure of separator 7.
Wherein, separator 7 in drain electrode 6 near between the sidewall and pixel electrode 8 of pixel electrode 8.
Step S303, formed and comprise the figure of pixel electrode 8.
Wherein, the material of pixel electrode 8 is tin indium oxide, and pixel electrode 8 is electrically connected with drain electrode 6 middle distance underlay substrates 1 conductive layer farthest.
Preferably, separator 7 is insulating barrier, and as shown in Figure 5, separator 7 covers whole array base palte.
Further, after step S302, namely after formation comprises the figure of separator 7, comprise through patterning processes, form the step running through the via hole 71 of separator 7.Wherein, via hole 71 is for being electrically connected pixel electrode 8 and drain electrode 6 middle distance underlay substrates 1 conductive layer farthest.
Particularly, through patterning processes, form the via hole 71 running through separator 7, comprise following steps as shown in Figure 6:
Step S601, on separator 7, be coated with one deck photoresist 11.
Step S602, use half gray level mask plate hide photoresist 11, photoresist 11 is exposed.
Wherein, the photoresist 11 of via hole 71 corresponding position exposes entirely, and the photoresist 11 half of pixel electrode 8 corresponding position exposes, and the photoresist 11 of other positions does not expose completely.
Step S603, photoresist 11 to be developed.
As shown in Figure 7, via hole 71 corresponding position forms photoresist and removes district completely, and pixel electrode 8 corresponding position forms photoresist part reserved area, and other positions form the complete reserved area of photoresist.
Step S604, separator 7 to be etched.
As shown in Figure 8, the separator 7 that place of district removed completely by photoresist is etched away, and forms via hole 71.
Further, the manufacture method of the array base palte in the embodiment of the present invention, after step S604, after namely etching separator 7, also comprises:
Through cineration technics, remove the photoresist 11 at photoresist part reserved area place, the photoresist at photoresist complete reserved area place still has residual.Now, the structure of array base palte as shown in Figure 9.
Now, step S303, forms the figure comprising pixel electrode 8, comprises following steps as described in Figure 10:
Step S1001, on whole array base palte, form indium oxide layer tin.Now, the structure of array base palte as shown in figure 11.
The photoresist 11 that step S1002, stripping photoresist complete reserved area place is residual, removes the tin indium oxide that photoresist 11 covers simultaneously, forms the figure comprising pixel electrode 8.
As shown in figure 12, pixel electrode 8 is electrically connected with drain electrode 6 middle distance underlay substrates 1 conductive layer farthest by via hole 71.
In addition, when the array base palte made is used in HADS display unit, the manufacture method of the array base palte in the embodiment of the present invention also comprises: on thin-film transistor and pixel electrode 8, form passivation layer 9, and on passivation layer 9, forming the figure comprising public electrode 10, public electrode 10 is the step of slit-shaped electrode or strip shaped electric poles.Now, the structure of the array base palte formed after above-mentioned steps as shown in Figure 2.
Embodiments provide a kind of manufacture method of array base palte, this manufacture method comprises the figure being formed and comprise separator, separator in described drain electrode near between the sidewall and pixel electrode of pixel electrode, thus the pixel electrode that can to prevent material in the drain electrode of thin-film transistor from being conductive layer and the material of aluminium be tin indium oxide contacts, thus can prevent aluminium from the indium in pixel electrode and tin being displaced, thus the conductivity of pixel electrode can not be affected, prevent pixel electrode to lose efficacy, and then it is bad to avoid display unit to occur.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (10)
1. an array base palte, it is characterized in that, the thin-film transistor comprising underlay substrate and be positioned on described underlay substrate and pixel electrode, the drain electrode of described thin-film transistor comprises at least two conductive layers of superposition mutually, wherein, except apart from except a described underlay substrate conductive layer farthest, the material of at least one conductive layer is aluminium, the material of described pixel electrode is tin indium oxide, described pixel electrode is electrically connected with the conductive layer farthest of underlay substrate described in described drain electrode middle distance, described drain electrode is provided with separator near between the sidewall and described pixel electrode of described pixel electrode.
2. array base palte according to claim 1, it is characterized in that, described separator is insulating barrier, described separator covers whole described array base palte, described array base palte also comprises the via hole running through described separator, and described pixel electrode is electrically connected with the conductive layer farthest of underlay substrate described in described drain electrode middle distance by described via hole.
3. array base palte according to claim 1 and 2, it is characterized in that, also comprise the passivation layer be positioned on described thin-film transistor and described pixel electrode, and be positioned at the public electrode on described passivation layer, described public electrode is slit-shaped electrode or strip shaped electric poles.
4. a display unit, is characterized in that, comprises the array base palte as described in any one of claim 1-3.
5. a manufacture method for array base palte, is characterized in that, comprising:
Underlay substrate forms thin-film transistor, and the drain electrode of described thin-film transistor comprises at least two conductive layers of superposition mutually, and wherein, except apart from except a described underlay substrate conductive layer farthest, the material of at least one conductive layer is aluminium;
Formed and comprise the figure of separator, described separator in described drain electrode near between the sidewall and pixel electrode of pixel electrode;
Form the figure comprising described pixel electrode, the material of described pixel electrode is tin indium oxide, and described pixel electrode is electrically connected with the conductive layer farthest of underlay substrate described in described drain electrode middle distance.
6. the manufacture method of array base palte according to claim 5, is characterized in that,
Described separator is insulating barrier, and described separator covers whole described array base palte.
7. the manufacture method of array base palte according to claim 6, is characterized in that, comprises the figure of separator in described formation, afterwards, comprising:
Through patterning processes, form the via hole running through described separator, described via hole is for being electrically connected a underlay substrate conductive layer farthest described in described pixel electrode and described drain electrode middle distance.
8. the manufacture method of array base palte according to claim 7, is characterized in that, described through patterning processes, forms the via hole running through described separator, comprising:
Described separator is coated with one deck photoresist;
Half gray level mask plate is used to hide described photoresist, expose described photoresist, wherein, the described photoresist of described via hole corresponding position exposes entirely, described photoresist half exposure of described pixel electrode corresponding position, the described photoresist of other positions does not expose completely;
Develop to described photoresist, wherein, described via hole corresponding position forms photoresist and removes district completely, and described pixel electrode corresponding position forms photoresist part reserved area, and other positions described form the complete reserved area of photoresist;
Etch described separator, wherein, the described separator that place of district removed completely by described photoresist is etched away, and forms described via hole.
9. the manufacture method of array base palte according to claim 8, is characterized in that, etches, afterwards, also comprise described to described separator:
Through cineration technics, remove the described photoresist at described photoresist part reserved area place, the described photoresist at described photoresist complete reserved area place still has residual;
Described formation comprises the figure of described pixel electrode, comprising:
Whole described array base palte forms indium oxide layer tin;
Peel off the described photoresist that described photoresist complete reserved area place is residual, the tin indium oxide that described photoresist covers is removed simultaneously, form the figure comprising described pixel electrode, described pixel electrode is electrically connected with the conductive layer farthest of underlay substrate described in described drain electrode middle distance by described via hole.
10. the manufacture method of the array base palte according to any one of claim 5-9, is characterized in that, also comprises:
Described thin-film transistor and described pixel electrode form passivation layer;
Described passivation layer is formed the figure comprising public electrode, and described public electrode is slit-shaped electrode or strip shaped electric poles.
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| CN201510032699.4A CN104538411A (en) | 2015-01-22 | 2015-01-22 | Array substrate, manufacture method of array substrate, and display device |
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| CN201510032699.4A CN104538411A (en) | 2015-01-22 | 2015-01-22 | Array substrate, manufacture method of array substrate, and display device |
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