CN102723309A - Array substrate and manufacturing method thereof as well as display device - Google Patents
Array substrate and manufacturing method thereof as well as display device Download PDFInfo
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- CN102723309A CN102723309A CN2012101956278A CN201210195627A CN102723309A CN 102723309 A CN102723309 A CN 102723309A CN 2012101956278 A CN2012101956278 A CN 2012101956278A CN 201210195627 A CN201210195627 A CN 201210195627A CN 102723309 A CN102723309 A CN 102723309A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
Abstract
The embodiment of the invention provides an array substrate and a manufacturing method thereof as well as a display device, and relates to the technical field of display. Mask process times are reduced, so that the manufacturing cost is reduced, the process flow is simplified, and the production efficiency is improved. The method for manufacturing the array substrate comprises the following steps of: sequentially depositing a first transparent conductive film and an insulating film on a grid insulating layer, a semiconductor active layer, a data line, a source electrode and a drain electrode; and forming a pixel electrode which is positioned in the area of a pixel electrode, is formed by the first transparent conductive film and is connected with the drain electrode, a data line additional layer which is positioned in the area of the data line and is formed by the first transparent conductive film, and passivation layers which are positioned in the area of the pixel electrode, the area of the data line and the area of the source electrode, cover the pixel electrode, the data line additional layer, the source electrode and the drain electrode and are formed by the insulating film through the one-step pattern composition process. The edge of the pixel electrode is positioned within the coverage range of the passivation layers.
Description
Technical field
The present invention relates to the Display Technique field, relate in particular to a kind of array base palte and manufacturing approach thereof and display unit.
Background technology
A senior ultra dimension switch technology (ADvanced Super Dimension Switch; Be called for short ADS); The electric field that electric field that is produced through gap electrode edge in the same plane and gap electrode layer and plate electrode interlayer produce forms multi-dimensional electric field; Make in the liquid crystal cell between gap electrode, all aligned liquid-crystal molecules can both produce rotation directly over the electrode, thereby improved the liquid crystal operating efficiency and increased light transmission efficiency.Senior ultra dimension field switch technology can improve TFT-LCD (Thin Film Transistor-Liquid Crystal Display; The TFT LCD) picture quality of product has high-resolution, high permeability, low-power consumption, wide visual angle, high aperture, low aberration, no water of compaction ripple advantages such as (push Mura).
The ADS LCD is compared with other LCDs has the advantage that enlarges the visual angle, has occupied consequence in current flat panel display market.Yet for the ADS LCD; Array base palte and manufacturing process thereof have determined its performance of products and price; This array base palte is in traditional manufacturing process; Normally adopt 6 mask manufacturing process (mask manufacturing process), this technological process generally is grid mask → semiconductor active layer mask → source-drain electrode mask → first tin indium oxide (1st ITO) mask → passivation layer mask → second tin indium oxide (2nd ITO) mask.
But the cost of mask technology and complexity are all very high, and more its manufacturing costs of number of applications will be high more, and production efficiency is low more.
Summary of the invention
Embodiments of the invention provide a kind of array base palte and manufacturing approach and display unit, through minimizing mask technology number of times, thereby reduce manufacturing cost, simplify technological process, enhance productivity.
For achieving the above object, embodiments of the invention adopt following technical scheme:
On the one hand, a kind of manufacturing approach of array base palte is provided, comprises,
On substrate, form the figure that comprises grid line, grid, gate insulation layer, semiconductor active layer, data wire, source electrode and drain electrode;
In said gate insulation layer, said semiconductor active layer, said data wire, said source electrode and said drain electrode, deposit first transparent conductive film and insulation film successively;
Comprise the pixel electrode that is connected with said drain electrode that forms by said first transparent conductive film that is positioned at pixel electrode area through a composition PROCESS FOR TREATMENT formation; Be positioned at the data wire extra play that forms by said first transparent conductive film in data wire zone, be positioned at the passivation layer that forms by said insulation film of the said pixel electrode of covering of pixel electrode area, data wire zone, source region, drain region, said data wire extra play, said source electrode, said drain electrode; Wherein, the edge of said pixel electrode is positioned within the coverage of said passivation layer;
Deposition second transparent conductive film on said passivation layer forms the public electrode with slit through the composition PROCESS FOR TREATMENT.
On the one hand, a kind of array base palte is provided, comprises:
Substrate;
Be formed on grid line, grid, gate insulation layer, semiconductor active layer, data wire, source electrode and drain electrode on the said substrate;
Be formed on the conduction that comprises said data wire top the data wire extra play, be formed on the pixel electrode of pixel electrode area; Wherein, said data wire extra play is identical with layer and material with said pixel electrode;
Be formed on the passivation layer that comprises on said data wire extra play and the said pixel electrode; Wherein, the edge of said pixel electrode is positioned within the coverage of said passivation layer;
Be formed on the public electrode on the said passivation layer.
Wherein, said data wire extra play, said pixel electrode, said passivation layer can utilize common mask plate to obtain through a composition PROCESS FOR TREATMENT.
On the one hand, a kind of display unit is provided, comprises above-mentioned array base palte.
In array base palte that the embodiment of the invention provides and manufacturing approach thereof and the display unit; The manufacturing approach of this array base palte after having deposited first transparent conductive film and insulation film successively on the substrate, forms pixel electrode and patterned passivation layer through a composition PROCESS FOR TREATMENT; And the edge of the pixel electrode after the etching processing is positioned within the scope of this passivation layer; Compare in the prior art and make pixel electrode and passivation layer, can in the manufacturing process of array base palte, reduce mask technology number of times, thereby reduce manufacturing cost through twice mask technology; Simplify technological process, enhance productivity.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
The schematic flow sheet of the manufacturing approach of the array base palte that Fig. 1 provides for the embodiment of the invention;
The sketch map of the part-structure of a kind of array base palte that Fig. 2 provides for the embodiment of the invention;
The sketch map of a kind of array base palte that Fig. 9 provides for the embodiment of the invention;
The sketch map of the part-structure of the another kind of array base palte that Fig. 3 provides for the embodiment of the invention;
The sketch map of the another kind of array base palte that Fig. 9 ' provides for the embodiment of the invention;
The structural representation of array base palte in the manufacturing approach process of a kind of array base palte that Fig. 4～Fig. 9 provides for the embodiment of the invention;
The structural representation of array base palte in the manufacturing approach process of the another kind of array base palte that Figure 10～Figure 16 provides for the embodiment of the invention.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
The manufacturing approach of the array base palte that the embodiment of the invention provides, as shown in Figure 1, comprising:
S11, on substrate, form the figure comprise grid line, grid, gate insulation layer, semiconductor active layer, data wire, source electrode and drain electrode.
Wherein, the following two kinds of methods of passing through that this step S11 is concrete realize:
One of which can comprise the steps, the structure of the array base palte of formation (part-structure of array base palte) is as shown in Figure 2:
S11a1, on substrate 20 deposition first metallic film, form the figure comprise grid line (not shown), grid 201 through the composition PROCESS FOR TREATMENT.
S11a2, on said grid line, grid 201 and said substrate 20, form gate insulation layer 24.
S11a3, on said gate insulation layer 24, form the figure comprise semiconductor active layer 34, data wire 21, source electrode 22, drain electrode 23.Like this, grid 201, semiconductor active layer 34, source electrode 22 and the 23 formation TFT that drain.
Its two, can comprise the steps that the structure of the array base palte of formation (part-structure of array base palte) is as shown in Figure 3:
S11b1, on substrate 20 the deposited semiconductor film, and form the figure that comprises semiconductor active layer 34 through composition PROCESS FOR TREATMENT.
S11b2, on said semiconductor active layer 34, form first grid insulating barrier 38; And on said first grid insulating barrier 38, form first via hole 351 and second via hole 352 through a composition PROCESS FOR TREATMENT; Wherein, Said first via hole 351, second via hole 352 lay respectively at the two ends of said semiconductor active layer 34, and expose said semiconductor active layer 34.
S11b3, on said first grid insulating barrier 38 deposition first metallic film, and form the figure that comprises grid line (not shown), grid 201 through composition PROCESS FOR TREATMENT.
S11b4, be mask through ion implantation technology, make the said semiconductor active layer 34 outside said grid 201 coverages be converted into doped semiconductor active layer 36 with said grid 201.
S11b5, on said grid line, grid 201, form second gate insulation layer 37, and on said second gate insulation layer 37, form the 3rd via hole 353 and the 4th via hole 354 through a composition PROCESS FOR TREATMENT; Wherein, said the 3rd via hole 353 corresponding said first via holes 351, and expose said first via hole 351; Said the 4th via hole 354 corresponding said second via holes 352, and expose said second via hole 352.
Need to prove that above-mentioned via hole is that etching forms respectively at twice on two-layer gate insulation layer, also can be after second gate insulation layer 37 forms, and forms through an etching.
S11b6, on said second gate insulation layer 37, form and comprise data wire 21, source electrode 22 and 23 the figure of draining.
Like this, just formed the tft array substrate of semiconductor active layer below grid.And grid 201, source electrode 22, drain electrode 23, semiconductor active layer 34, and doped semiconductor active layer 36 etc. constitutes TFT.
S12, in said gate insulation layer, said semiconductor active layer, said data wire, said source electrode, said drain electrode, deposit first transparent conductive film and insulation film successively.
Exemplary, be that example describes with the structure of semiconductor active layer on grid, as shown in Figure 4, at gate insulation layer 24, semiconductor active layer 34, data wire 21, source electrode 22 with drain and deposit first transparent conductive film 25 and insulation film 26 successively on 23.The material of this insulation film 26 can be a silicon nitride, and this first transparent conductive film can be
indium tin oxide films for thickness.
S13, form through composition PROCESS FOR TREATMENT and to comprise the pixel electrode that is connected with said drain electrode that forms by said first transparent conductive film that is positioned at pixel electrode area; Be positioned at the data wire extra play that forms by said first transparent conductive film in data wire zone, be positioned at the passivation layer that forms by said insulation film of the said pixel electrode of covering of pixel electrode area, data wire zone, source region, drain region, said data wire extra play, said source electrode, said drain electrode; Wherein, the edge of said pixel electrode is positioned within the coverage of said passivation layer.
Need to prove that the edge of said pixel electrode is positioned within the coverage of said passivation layer, be meant that pixel electrode is passivated layer and covers fully, and its edge has been fully retracted in the edge of passivation layer.This structure can be through realizing carving excessively of first transparent conductive film (forming the rete of pixel electrode).Public electrode and pixel electrode short circuit that this can effectively be avoided follow-up formation cause bad.
And preferably, the edge of the said data wire extra play after the etching processing also is positioned within the coverage of said passivation layer.This public electrode that can effectively avoid follow-up formation causes bad through data wire extra play and data wire short circuit.
S14, on said passivation layer deposition second transparent conductive film, form public electrode with slit through the composition PROCESS FOR TREATMENT.
Wherein, preferably, the thickness of second transparent conductive film is greater than the thickness of first transparent conductive film, and promptly the thickness of pixel electrode is less than the thickness of public electrode.
Need to prove, in the present embodiment,, can effectively reduce the resistance on the data wire, improve the quality of products because the data wire top is provided with the data wire extra play; And in the data pads zone (Pad zone), the data wire extra play can play the effect of protected data line (the concrete actual data cable lead wire that is).And; In the present embodiment; The thickness of pixel electrode is less than the thickness of public electrode; The intersection that has guaranteed public electrode and passivation layer so can not plan a successor bad; Further guaranteed product quality; Exemplary, the thickness of this first transparent conductive film be
this second transparent conductive film thickness is
Wherein, step S13 can be made by following method, like Fig. 5～shown in Figure 9.
S131, as shown in Figure 5; Coating photoresist 27 on this insulation film 26; Through overexposure; The back of developing forms on this insulation film and comprises the photoresist reserve area 271 of respective data lines zone, pixel electrode area, source region, drain region, and the photoresist that exposes said insulation film is removed the zone fully.That is, what used this moment is common mask plate (monotone mask plate), but not duotone mask plates such as halftoning mask, gray scale mask plate.
S132, as shown in Figure 6; Etch away the insulation film 26 that said photoresist is removed zone 271 fully through first etching processing, form the passivation layer 261 that is positioned at said first transparent conductive film 25 of covering that comprises said pixel electrode area, said data wire 21 zones, said source electrode 22 zones, said drain electrode 23 zones.
S133, as shown in Figure 7 etches away said first transparent conductive film 251 that exposes through second etching processing, forms to comprise data wire extra play 252 that is positioned at the data wire zone and the pixel electrode 253 that is positioned at pixel electrode area; Wherein, the edge of said pixel electrode 253 is positioned within the coverage of said passivation layer 261.
Concrete, cross and carve that to handle be through the control etch period, the edge of pixel electrode 253 is positioned within the coverage of passivation layer 261, thus guaranteed pixel electrode 253 and the public electrode that forms afterwards can short circuit together, guaranteed product quality.
S134, as shown in Figure 8 peels off remaining photoresist.
Above-mentioned is a kind of implementation of present embodiment S13, has used common mask plate to realize the composition PROCESS FOR TREATMENT; Certainly, this step can also realize through other modes, such as using double-colored mask plate, does not give unnecessary details here.Afterwards, identical with prior art, as shown in Figure 9, on this passivation layer 261, form public electrode 28 through composition technology with slit.
Above-mentioned steps S12 and S13 are that example is illustrated with the structure of semiconductor active layer on grid, and the array base palte that finally makes is as shown in Figure 9.For the structure of semiconductor active layer below grid, also can adopt manufacture method same as described above to realize, the structure of the final array base palte that forms is shown in Fig. 9 '.
Need to prove; The order of S133 and S134 can be changed in the method step that the embodiment of the invention provides; Because when first transparent conductive film 25 is carried out etching; Passivation layer 261 has served as the protective effect of photoresist, like this, conspicuously can reach identical purpose with above-mentioned implementation method.And; This method step S12～S14 can also be used for the manufacturing process of the array base palte of grid above semiconductor active layer; Concrete is behind above-mentioned steps S11b6; On said data wire, said source electrode, said drain electrode and said second gate insulation layer, carry out above-mentioned steps S12～S14, repeat no more at this.
The manufacturing approach of the array base palte that the embodiment of the invention provides; After having deposited first transparent conductive film and insulation film successively, form pixel electrode and patterned passivation layer through a composition PROCESS FOR TREATMENT, and the edge of the pixel electrode after the etching processing is positioned within the scope of this passivation layer; Compare prior art and can in the manufacturing process of array base palte, reduce mask technology number of times; Thereby the reduction manufacturing cost is simplified technological process, enhances productivity.
Need to prove, in above-mentioned steps S11a3, can adopt existing manufacturing process, elder generation's deposited semiconductor film on gate insulation layer 24, and through a composition technology formation semiconductor active layer 34; Depositing metal films again, and form the figure that comprises data wire 21, source electrode 22, drain electrode 23 through a composition technology.Step S11a3 adopts twice composition technology to accomplish like this.In order further to reduce the number of times of mask technology, optional, the semiconductor active layer of step S11a3, data wire, source electrode, drain electrode can also form through a composition PROCESS FOR TREATMENT, specifically can make by following method, like Figure 10～shown in Figure 16,
S11a31, on gate insulation layer 24 deposited semiconductor film 31, shown in figure 10;
S11a32, on this semiconductive thin film 31 deposition second metallic film 32, shown in figure 11;
S11a33, on this second metallic film 32 coating photoresist 33; Photoresist half reserve area 332 of the complete reserve area of the photoresist that utilize gray scale mask plate or pellicle mask board to explosure, the back of developing forms respective data lines zone, source region, drain region on this second metallic film 331, corresponding channel region; And the photoresist that exposes said second metallic film removes the zone fully, and is shown in figure 12.
S11a34, through etching processing etch away photoresist remove fully the zone second metallic film 32 and semiconductive thin film 31, shown in figure 13.
S11a35, get rid of the photoresist 332 of photoresist half reserve area 332 through ashing treatment, exposed portions serve second metallic film 321, shown in figure 14.
S11a36, said second metallic film 321 that exposes is carried out etching, to form raceway groove 34, shown in figure 15.
S11a37, peel off the photoresist of the complete reserve area 331 of photoresist, obtaining comprising semiconductor active layer 31, the figure of data wire 21, source electrode 22, drain electrode 23, shown in figure 16.
So; Because active layer, data wire and source electrode, drain electrode make through a composition technology; From and reduced mask 1 time, make and in making the process of this array base palte, only used mask technology 4 times, thereby further reduce manufacturing cost; Simplify technological process, enhance productivity.
The array base palte that the embodiment of the invention provides comprising with reference to figure 9 or Fig. 9 ':
Wherein, said data wire extra play 252, said pixel electrode 253, said passivation layer 261 can utilize common mask plate to obtain through a composition PROCESS FOR TREATMENT.
Wherein, Be formed on grid line, grid 201, gate insulation layer, semiconductor active layer, data wire 21, source electrode 22, drain electrode 23 on this substrate 20; Its concrete structure can be as shown in Figure 9, is formed on grid line (not shown), grid 201 on the said substrate; Be formed on the gate insulation layer 24 on said substrate 20, said grid line, the said grid 201; Be formed on the semiconductor active layer 31 on the said gate insulation layer 24; Be formed on source electrode 22, the drain electrode 23 on the said semiconductor active layer 31 and be formed on the data wire 21 on the said gate insulation layer 24; In addition, shown in Fig. 9 ', its structure can also be formed in semiconductor active layer 34 and the doped semiconductor active layer 36 on the said substrate 20; Wherein, said doped semiconductor active layer 36 is positioned at the both sides of said semiconductor active layer 34; Be formed on the first grid insulating barrier 38 on said substrate 20, said semiconductor active layer 34 and the said doped semiconductor active layer 36; Be formed on grid line (not shown), grid 201 on the said first grid insulating barrier 38; Be formed on second insulating barrier 37 on said grid line (not shown), the grid 201; Be formed on data wire 21, source electrode 22, drain electrode 23 on said second gate insulation layer 37; Wherein, Said source electrode 22 is connected with the said doped semiconductor active layer 36 of said semiconductor active layer 34 1 sides through the 5th via hole 35, and said drain electrode 23 is connected with the said doped semiconductor active layer 36 of said semiconductor active layer opposite side through the 6th via hole 35.
Need to prove,, can effectively reduce the resistance on the data wire like this, improve the quality of products because data wire 21 tops are formed with data wire extra play 252.
The array base palte that the embodiment of the invention provides after having deposited first transparent conductive film and insulation film successively, forms pixel electrode and patterned passivation layer through a composition PROCESS FOR TREATMENT; And the edge of the pixel electrode after the etching processing is positioned within the scope of this passivation layer, and, above data wire, be formed with the data wire extra play; Compare prior art, in the manufacturing process of array base palte, reduce mask technology number of times (being the masking process number of times), thereby reduce manufacturing cost; Simplify technological process; Enhance productivity, and can effectively reduce the resistance on the data wire, thereby further improve the quality of products.
Preferably, the thickness of pixel electrode is less than the thickness of public electrode, and like this, the intersection that has guaranteed public electrode and passivation layer can not plan a successor bad, has further guaranteed product quality.Concrete; This pixel electrode can be that thickness is the indium tin oxide films of
, and this public electrode can be that thickness is the indium tin oxide films of
.
The embodiment of the invention also provides a kind of display unit, and it comprises above-mentioned any one array base palte.Said display unit can be any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.
The above; Be merely embodiment of the present invention, but protection scope of the present invention is not limited thereto, any technical staff who is familiar with the present technique field is in the technical scope that the present invention discloses; Can expect easily changing or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of said claim.
Claims (14)
1. the manufacturing approach of an array base palte is characterized in that, comprising:
On substrate, form the figure that comprises grid line, grid, gate insulation layer, semiconductor active layer, data wire, source electrode and drain electrode;
In said gate insulation layer, said semiconductor active layer, said data wire, said source electrode and said drain electrode, deposit first transparent conductive film and insulation film successively;
Comprise the pixel electrode that is connected with said drain electrode that forms by said first transparent conductive film that is positioned at pixel electrode area through a composition PROCESS FOR TREATMENT formation; Be positioned at the data wire extra play that forms by said first transparent conductive film in data wire zone, be positioned at the passivation layer that forms by said insulation film of the said pixel electrode of covering of pixel electrode area, data wire zone, source region, drain region, said data wire extra play, said source electrode, said drain electrode; Wherein, the edge of said pixel electrode is positioned within the coverage of said passivation layer;
Deposition second transparent conductive film on said passivation layer forms the public electrode with slit through the composition PROCESS FOR TREATMENT.
2. the manufacturing approach of array base palte according to claim 1 is characterized in that, said on substrate, formation comprises that the figure of grid line, grid, gate insulation layer, semiconductor active layer, data wire, source electrode and drain electrode comprises:
Deposition first metallic film on substrate forms the figure that comprises grid line, grid through the composition PROCESS FOR TREATMENT;
On said grid line, grid and said substrate, form gate insulation layer;
On said gate insulation layer, form the figure that comprises semiconductor active layer, data wire, source electrode, drain electrode.
3. the manufacturing approach of array base palte according to claim 1 is characterized in that, said on substrate, formation comprises that the figure of grid line, grid, gate insulation layer, semiconductor active layer, data wire, source electrode and drain electrode comprises:
Deposited semiconductor film on substrate, and form the figure that comprises semiconductor active layer through composition PROCESS FOR TREATMENT;
On said semiconductor active layer, form first grid insulating barrier; And on said first grid insulating barrier, form first via hole and second via hole through a composition PROCESS FOR TREATMENT; Wherein, Said first via hole, second via hole lay respectively at the two ends of said semiconductor active layer, and expose said semiconductor active layer;
On said first grid insulating barrier, deposit first metallic film, and form the figure that comprises grid line, grid through a composition PROCESS FOR TREATMENT;
With said grid is that mask passes through ion implantation technology, makes the said semiconductor active layer outside the said grid coverage be converted into the doped semiconductor active layer;
On said grid line, grid, form second gate insulation layer, and on said second gate insulation layer, form the 3rd via hole and the 4th via hole through a composition PROCESS FOR TREATMENT; Wherein, corresponding said first via hole of said the 3rd via hole, and expose said first via hole; Corresponding said second via hole of said the 4th via hole, and expose said second via hole;
On said second gate insulation layer, form the figure that comprises data wire, source electrode and drain electrode.
4. according to the manufacturing approach of the arbitrary described array base palte of claim 1～3; It is characterized in that; Comprise the pixel electrode that is connected with said drain electrode that forms by said first transparent conductive film that is positioned at pixel electrode area through a composition PROCESS FOR TREATMENT formation; Be positioned at the data wire extra play that forms by said first transparent conductive film in data wire zone, be positioned at the passivation layer that forms by said insulation film of the said pixel electrode of covering of pixel electrode area, data wire zone, source region, drain region, said data wire extra play, said source electrode, said drain electrode; Wherein, the edge of said pixel electrode is positioned within the coverage of said passivation layer and comprises:
On said insulation film, be coated with photoresist; Comprise the photoresist reserve area of respective data lines zone, pixel electrode area, source region, drain region through overexposure, the back formation on said insulation film of developing, and the photoresist that exposes said insulation film is removed the zone fully;
Etch away the insulation film that said photoresist is removed the zone fully through first etching processing, form the passivation layer that is positioned at said first transparent conductive film of covering that comprises said pixel electrode area, said data wire zone, said source region, said drain region;
Etch away said first transparent conductive film that exposes through second etching processing, formation comprises data wire extra play that is positioned at the data wire zone and the pixel electrode that is positioned at pixel electrode area; Wherein, the edge of said pixel electrode is positioned within the coverage of said passivation layer;
Peel off remaining photoresist.
5. according to the manufacturing approach of the arbitrary described array base palte of claim 1～3; It is characterized in that; Comprise the pixel electrode that is connected with said drain electrode that forms by said first transparent conductive film that is positioned at pixel electrode area through a composition PROCESS FOR TREATMENT formation; Be positioned at the data wire extra play that forms by said first transparent conductive film in data wire zone, be positioned at the passivation layer that forms by said insulation film of the said pixel electrode of covering of pixel electrode area, data wire zone, source region, drain region, said data wire extra play, said source electrode, said drain electrode; Wherein, the edge of said pixel electrode is positioned within the coverage of said passivation layer and comprises:
On said insulation film, be coated with photoresist; Comprise the photoresist reserve area of respective data lines zone, pixel electrode area, source region, drain region through overexposure, the back formation on said insulation film of developing, and the photoresist that exposes said insulation film is removed the zone fully;
Etch away the insulation film that said photoresist is removed the zone fully through first etching processing, form the patterned passivation layer that is positioned at said first transparent conductive film of covering that comprises said pixel electrode area, said data wire zone, said source region, said drain region;
Peel off the residue photoresist;
Etch away said first transparent conductive film that exposes through second etching processing, formation comprises data wire extra play that is positioned at the data wire zone and the pixel electrode that is positioned at pixel electrode area; Wherein, the edge of said pixel electrode is positioned within the coverage of said passivation layer.
6. the manufacturing approach of array base palte according to claim 2 is characterized in that, on said gate insulation layer, forms to comprise that the figure of semiconductor active layer, data wire, source electrode, drain electrode comprises:
Deposited semiconductor film on said gate insulation layer;
Deposition second metallic film on said semiconductive thin film;
On said second metallic film, be coated with photoresist; The complete reserve area of photoresist that utilize gray scale mask plate or pellicle mask board to explosure, the back of developing forms respective data lines zone, source region, drain region on said second metallic film; Photoresist half reserve area of corresponding channel region, and the photoresist that exposes said second metallic film is removed the zone fully;
Etch away said second metallic film and the semiconductive thin film that photoresist is removed the zone fully through etching processing;
Get rid of the photoresist of said photoresist half reserve area, exposed portions serve second metallic film through ashing treatment;
Said second metallic film to exposing carries out etching, to form raceway groove;
Peel off the photoresist of the complete reserve area of photoresist, to obtain comprising semiconductor active layer, the figure of data wire, source electrode, drain electrode.
7. the manufacturing approach of array base palte according to claim 1 is characterized in that, the thickness of said pixel electrode is less than the thickness of said public electrode.
8. the manufacturing approach of array base palte according to claim 7; It is characterized in that, the thickness of said pixel electrode be
said public electrode thickness is
9. an array base palte is characterized in that, comprising:
Substrate;
Be formed on grid line, grid, gate insulation layer, semiconductor active layer, data wire, source electrode and drain electrode on the said substrate;
Be formed on the conduction that comprises said data wire top the data wire extra play, be formed on the pixel electrode of pixel electrode area; Wherein, said data wire extra play is identical with layer and material with said pixel electrode;
Be formed on the passivation layer that comprises on said data wire extra play and the said pixel electrode; Wherein, the edge of said pixel electrode is positioned within the coverage of said passivation layer;
Be formed on the public electrode on the said passivation layer.
10. array base palte according to claim 9 is characterized in that, the grid line, grid, gate insulation layer, semiconductor active layer, data wire, source electrode and the drain electrode that are formed on the said substrate comprise:
Be formed on grid line, grid on the said substrate;
Be formed on the gate insulation layer on said substrate, said grid line, the grid;
Be formed on the semiconductor active layer on the said gate insulation layer;
Be formed on source electrode on the said semiconductor active layer, drain and be formed on the data wire on the said gate insulation layer.
11. array base palte according to claim 9 is characterized in that, the grid line, grid, gate insulation layer, semiconductor active layer, data wire, source electrode and the drain electrode that are formed on the said substrate comprise:
Be formed on semiconductor active layer and doped semiconductor active layer on the said substrate; Wherein, said doped semiconductor active layer is positioned at the both sides of said semiconductor active layer;
Be formed on the first grid insulating barrier on said substrate, said semiconductor active layer and the said doped semiconductor active layer;
Be formed on grid line, grid on the said first grid insulating barrier;
Be formed on second gate insulation layer on said grid line, the grid;
Be formed on data wire, source electrode, drain electrode on said second gate insulation layer; Wherein, said source electrode is connected with the said doped semiconductor active layer of said semiconductor active layer one side through the 5th via hole, and said drain electrode is connected with the said doped semiconductor active layer of said semiconductor active layer opposite side through the 6th via hole.
12., it is characterized in that the thickness of said pixel electrode is less than the thickness of said public electrode according to the arbitrary described array base palte of claim 9～11.
13. array base palte according to claim 12; It is characterized in that, the thickness of said pixel electrode be
said public electrode thickness is
14. a display unit is characterized in that, comprises each described array base palte of claim 9-13.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210195627.8A CN102723309B (en) | 2012-06-13 | 2012-06-13 | Array substrate and manufacturing method thereof as well as display device |
| PCT/CN2012/086309 WO2013185454A1 (en) | 2012-06-13 | 2012-12-10 | Array substrate, fabrication method thereof, and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210195627.8A CN102723309B (en) | 2012-06-13 | 2012-06-13 | Array substrate and manufacturing method thereof as well as display device |
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| Publication Number | Publication Date |
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| CN102723309A true CN102723309A (en) | 2012-10-10 |
| CN102723309B CN102723309B (en) | 2014-07-02 |
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| CN201210195627.8A Active CN102723309B (en) | 2012-06-13 | 2012-06-13 | Array substrate and manufacturing method thereof as well as display device |
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| CN (1) | CN102723309B (en) |
| WO (1) | WO2013185454A1 (en) |
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Also Published As
| Publication number | Publication date |
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| WO2013185454A1 (en) | 2013-12-19 |
| CN102723309B (en) | 2014-07-02 |
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