CN102723309B - Array substrate and manufacturing method thereof as well as display device - Google Patents
Array substrate and manufacturing method thereof as well as display device Download PDFInfo
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- CN102723309B CN102723309B CN201210195627.8A CN201210195627A CN102723309B CN 102723309 B CN102723309 B CN 102723309B CN 201210195627 A CN201210195627 A CN 201210195627A CN 102723309 B CN102723309 B CN 102723309B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 42
- 239000000758 substrate Substances 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 75
- 239000004065 semiconductor Substances 0.000 claims abstract description 73
- 238000002161 passivation Methods 0.000 claims abstract description 49
- 230000008569 process Effects 0.000 claims abstract description 34
- 239000000203 mixture Substances 0.000 claims abstract description 31
- 239000010408 film Substances 0.000 claims description 85
- 238000009413 insulation Methods 0.000 claims description 55
- 229920002120 photoresistant polymer Polymers 0.000 claims description 34
- 230000004888 barrier function Effects 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 17
- 239000010409 thin film Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 4
- 238000004380 ashing Methods 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 93
- 239000004973 liquid crystal related substance Substances 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 2
- 238000003325 tomography Methods 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 101100269850 Caenorhabditis elegans mask-1 gene Proteins 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005056 compaction Methods 0.000 description 1
- 210000002858 crystal cell Anatomy 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The embodiment of the invention provides an array substrate and a manufacturing method thereof as well as a display device, and relates to the technical field of display. Mask process times are reduced, so that the manufacturing cost is reduced, the process flow is simplified, and the production efficiency is improved. The method for manufacturing the array substrate comprises the following steps of: sequentially depositing a first transparent conductive film and an insulating film on a grid insulating layer, a semiconductor active layer, a data line, a source electrode and a drain electrode; and forming a pixel electrode which is positioned in the area of a pixel electrode, is formed by the first transparent conductive film and is connected with the drain electrode, a data line additional layer which is positioned in the area of the data line and is formed by the first transparent conductive film, and passivation layers which are positioned in the area of the pixel electrode, the area of the data line and the area of the source electrode, cover the pixel electrode, the data line additional layer, the source electrode and the drain electrode and are formed by the insulating film through the one-step pattern composition process. The edge of the pixel electrode is positioned within the coverage range of the passivation layers.
Description
Technical field
The present invention relates to Display Technique field, relate in particular to a kind of array base palte and manufacture method thereof and display unit.
Background technology
A senior super dimension switch technology (ADvanced Super Dimension Switch, be called for short ADS), the electric field producing by electric field that in same plane, gap electrode edge produces and gap electrode layer and plate electrode interlayer forms multi-dimensional electric field, make in liquid crystal cell between gap electrode, directly over electrode, all aligned liquid-crystal molecules can both produce rotation, thereby improved liquid crystal operating efficiency and increased light transmission efficiency.Senior super dimension field switch technology can improve TFT-LCD (Thin Film Transistor-Liquid Crystal Display, Thin Film Transistor (TFT) liquid crystal display) picture quality of product, there is high-resolution, high permeability, low-power consumption, wide visual angle, high aperture, low aberration, without advantages such as water of compaction ripples (push Mura).
ADS liquid crystal display has advantages of the visual angle of expansion compared with other liquid crystal display, has occupied consequence in current flat panel display market.But for ADS liquid crystal display, array base palte and manufacturing process thereof have determined performance and the price of its product, this array base palte is in traditional manufacturing process, normally adopt 6 mask manufacturing process (mask manufacturing process), this technological process generally, grid mask → semiconductor active layer mask → source-drain electrode mask → the first tin indium oxide (1st ITO) mask → passivation layer mask → the second tin indium oxide (2nd ITO) mask.
But the cost of mask technique and complexity are all very high, more its manufacturing costs of number of applications will be higher, and production efficiency is lower.
Summary of the invention
Embodiments of the invention provide a kind of array base palte and manufacture method and display unit, by reducing mask technique number of times, thereby reduce manufacturing cost, and simplification of flowsheet, enhances productivity.
For achieving the above object, embodiments of the invention adopt following technical scheme:
On the one hand, provide a kind of manufacture method of array base palte, comprise,
On substrate, form the figure that comprises grid line, grid, gate insulation layer, semiconductor active layer, data wire, source electrode and drain electrode;
In described gate insulation layer, described semiconductor active layer, described data wire, described source electrode and described drain electrode, deposit successively the first transparent conductive film and insulation film;
Form and comprise the pixel electrode being connected with described drain electrode being formed by described the first transparent conductive film that is positioned at pixel electrode area by a composition PROCESS FOR TREATMENT, be positioned at the data wire extra play being formed by described the first transparent conductive film in data wire region, be positioned at the passivation layer being formed by described insulation film of the described pixel electrode of covering of pixel electrode area, data wire region, source region, drain region, described data wire extra play, described source electrode, described drain electrode; Wherein, within the edge of described pixel electrode is positioned at the coverage of described passivation layer;
On described passivation layer, deposit the second transparent conductive film, form the public electrode with slit by composition PROCESS FOR TREATMENT.
On the one hand, provide a kind of array base palte, comprising:
Substrate;
Be formed on grid line, grid, gate insulation layer, semiconductor active layer, data wire, source electrode and drain electrode on described substrate;
Be formed on the conduction that comprises described data wire top data wire extra play, be formed on the pixel electrode of pixel electrode area; Wherein, described data wire extra play is identical with layer and material with described pixel electrode;
Be formed on the passivation layer comprising on described data wire extra play and described pixel electrode; Wherein, within the edge of described pixel electrode is positioned at the coverage of described passivation layer;
Be formed on the public electrode on described passivation layer.
Wherein, described data wire extra play, described pixel electrode, described passivation layer can utilize common mask plate to obtain by a composition PROCESS FOR TREATMENT.
On the one hand, provide a kind of display unit, comprise above-mentioned array base palte.
In the array base palte that the embodiment of the present invention provides and manufacture method thereof and display unit, the manufacture method of this array base palte, on substrate, deposit successively after the first transparent conductive film and insulation film, form pixel electrode and patterned passivation layer by a composition PROCESS FOR TREATMENT, and within the edge of the pixel electrode after etching processing is positioned at the scope of this passivation layer, compare in prior art and make pixel electrode and passivation layer by twice mask technique, can in the manufacturing process of array base palte, reduce mask technique number of times, thereby reduction manufacturing cost, simplification of flowsheet, enhance productivity.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The schematic flow sheet of the manufacture method of the array base palte that Fig. 1 provides for the embodiment of the present invention;
The schematic diagram of the part-structure of a kind of array base palte that Fig. 2 provides for the embodiment of the present invention;
The schematic diagram of a kind of array base palte that Fig. 9 provides for the embodiment of the present invention;
The schematic diagram of the part-structure of the another kind of array base palte that Fig. 3 provides for the embodiment of the present invention;
The schematic diagram of the another kind of array base palte that Fig. 9 ' provides for the embodiment of the present invention;
The structural representation of array base palte in the manufacture method process of a kind of array base palte that Fig. 4～Fig. 9 provides for the embodiment of the present invention;
The structural representation of array base palte in the manufacture method process of the another kind of array base palte that Figure 10～Figure 16 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
The manufacture method of the array base palte that the embodiment of the present invention provides, as shown in Figure 1, comprising:
S11, on substrate, form and comprise the figure of grid line, grid, gate insulation layer, semiconductor active layer, data wire, source electrode and drain electrode.
What wherein, this step S11 was concrete passes through following two kinds of methods realization:
One, can comprise the steps, the structure (part-structure of array base palte) of the array base palte of formation as shown in Figure 2:
S11a1, on substrate 20, deposit the first metallic film, form the figure that comprises grid line (not shown), grid 201 by composition PROCESS FOR TREATMENT.
S11a2, on described grid line, grid 201 and described substrate 20, form gate insulation layer 24.
S11a3, on described gate insulation layer 24, form the figure that comprises semiconductor active layer 34, data wire 21, source electrode 22, drain electrode 23.Like this, grid 201, semiconductor active layer 34, source electrode 22 and drain electrode 23 form TFT.
Its two, can comprise the steps, the structure (part-structure of array base palte) of the array base palte of formation as shown in Figure 3:
S11b1, on substrate 20 deposited semiconductor film, and form the figure that comprises semiconductor active layer 34 by composition PROCESS FOR TREATMENT.
S11b2, on described semiconductor active layer 34, form first grid insulating barrier 38, and on described first grid insulating barrier 38, form the first via hole 351 and the second via hole 352 by a composition PROCESS FOR TREATMENT, wherein, described the first via hole 351, the second via hole 352 lay respectively at the two ends of described semiconductor active layer 34, and expose described semiconductor active layer 34.
S11b3, on described first grid insulating barrier 38, deposit the first metallic film, and form by a composition PROCESS FOR TREATMENT figure that comprises grid line (not shown), grid 201.
S11b4, take described grid 201 as mask by ion implantation technology, make the described semiconductor active layer 34 outside described grid 201 coverages be converted into doped semiconductor active layer 36.
S11b5, on described grid line, grid 201, form second gate insulating barrier 37, and on described second gate insulating barrier 37, form the 3rd via hole 353 and the 4th via hole 354 by a composition PROCESS FOR TREATMENT; Wherein, corresponding described the first via hole 351 of described the 3rd via hole 353, and expose described the first via hole 351; Corresponding described the second via hole 352 of described the 4th via hole 354, and expose described the second via hole 352.
It should be noted that, above-mentioned via hole is that etching forms respectively at twice on two-layer gate insulation layer, can be also after second gate insulating barrier 37 forms, and forms by an etching.
S11b6, on described second gate insulating barrier 37, form the figure that comprises data wire 21, source electrode 22 and drain electrode 23.
Like this, just form the tft array substrate of semiconductor active layer below grid.And grid 201, source electrode 22, drain electrode 23, semiconductor active layer 34, and doped semiconductor active layer 36 etc. forms TFT.
S12, in described gate insulation layer, described semiconductor active layer, described data wire, described source electrode, described drain electrode, deposit successively the first transparent conductive film and insulation film.
Exemplary, the structure take semiconductor active layer on grid, as example describes, as shown in Figure 4, deposits successively the first transparent conductive film 25 and insulation film 26 in gate insulation layer 24, semiconductor active layer 34, data wire 21, source electrode 22 and drain electrode 23.The material of this insulation film 26 can be silicon nitride, and this first transparent conductive film can be for thickness
indium tin oxide films.
S13, form and comprise the pixel electrode being connected with described drain electrode being formed by described the first transparent conductive film that is positioned at pixel electrode area by composition PROCESS FOR TREATMENT, be positioned at the data wire extra play being formed by described the first transparent conductive film in data wire region, be positioned at the passivation layer being formed by described insulation film of the described pixel electrode of covering of pixel electrode area, data wire region, source region, drain region, described data wire extra play, described source electrode, described drain electrode; Wherein, within the edge of described pixel electrode is positioned at the coverage of described passivation layer.
It should be noted that, within the edge of described pixel electrode is positioned at the coverage of described passivation layer, refer to that pixel electrode is passivated layer and covers completely, and its edge has been fully retracted in the edge of passivation layer.This structure can be by carving and realizing the first transparent conductive film (forming the rete of pixel electrode) excessively.Public electrode and pixel electrode short circuit that this can effectively be avoided follow-up formation, cause bad.
And, preferably, within the edge of the described data wire extra play after etching processing is also positioned at the coverage of described passivation layer.This can effectively be avoided the public electrode of follow-up formation by data wire extra play and data wire short circuit, causes bad.
S14, on described passivation layer, deposit the second transparent conductive film, form the public electrode with slit by composition PROCESS FOR TREATMENT.
Wherein, preferably, the thickness of the second transparent conductive film is greater than the thickness of the first transparent conductive film, and the thickness of pixel electrode is less than the thickness of public electrode.
It should be noted that, in the present embodiment, because data wire top is provided with data wire extra play, can effectively reduce the resistance on data wire, improve the quality of products; And in data pads region (Pad region), data wire extra play can play the effect of protected data line (concrete reality is data cable lead wire).And in the present embodiment, the thickness of pixel electrode is less than the thickness of public electrode, the intersection that has guaranteed like this public electrode and passivation layer there will not be tomography bad, further guaranteed product quality, exemplary, the thickness of this first transparent conductive film is
the thickness of this second transparent conductive film is
Wherein, step S13 can be made by following methods, as shown in Fig. 5～Fig. 9.
S131, as shown in Figure 5, on this insulation film 26, be coated with photoresist 27, through overexposure, after development, on this insulation film, form and comprise the photoresist reserve area 271 of respective data lines region, pixel electrode area, source region, drain region, and the photoresist that exposes described insulation film is removed region completely.That is, what now use is common mask plate (monotone mask plate), but not the duotone mask plates such as halftoning mask, gray scale mask plate.
S132, as shown in Figure 6, etch away described photoresist by the first etching processing and remove the insulation film 26 in region 271 completely, form the passivation layer 261 that is positioned at described the first transparent conductive film 25 of covering that comprises described pixel electrode area, described data wire 21 regions, described source electrode 22 regions, described drain electrode 23 regions.
S133, as shown in Figure 7, etches away described the first transparent conductive film 251 exposing by the second etching processing, form and comprise the data wire extra play 252 that is positioned at data wire region and the pixel electrode 253 that is positioned at pixel electrode area; Wherein, within the edge of described pixel electrode 253 is positioned at the coverage of described passivation layer 261.
Concrete, cross and carve that to process be by controlling etch period, make within the edge of pixel electrode 253 is positioned at the coverage of passivation layer 261, thereby guaranteed that pixel electrode 253 and the public electrode forming afterwards can not be shorted together, and have guaranteed product quality.
S134, as shown in Figure 8, peels off remaining photoresist.
Above-mentioned is a kind of implementation of the present embodiment S13, has used common mask plate to realize composition PROCESS FOR TREATMENT; Certainly, this step can also realize by other means, such as using double-colored mask plate, does not repeat herein.Afterwards, same as the prior art, as shown in Figure 9, on this passivation layer 261, form the public electrode 28 with slit by composition technique.
The structure on grid is as example is illustrated take semiconductor active layer for above-mentioned steps S12 and S13, and the array base palte finally making as shown in Figure 9.Structure for semiconductor active layer below grid, also can adopt manufacture method same as described above to realize, and the structure of the final array base palte forming is as shown in Fig. 9 '.
It should be noted that; in the method step providing in the embodiment of the present invention, the order of S133 and S134 can be exchanged; because in the time that the first transparent conductive film 25 is carried out to etching; passivation layer 261 has served as the protective effect of photoresist; like this, apparently can reach identical object with above-mentioned implementation method.And, the method step S12～S14 can also be used for the manufacturing process of the array base palte of grid above semiconductor active layer, concrete is after above-mentioned steps S11b6, on described data wire, described source electrode, described drain electrode and described second gate insulating barrier, carry out above-mentioned steps S12～S14, do not repeat them here.
The manufacture method of the array base palte that the embodiment of the present invention provides, depositing successively after the first transparent conductive film and insulation film, form pixel electrode and patterned passivation layer by a composition PROCESS FOR TREATMENT, and within the edge of the pixel electrode after etching processing is positioned at the scope of this passivation layer, compare prior art and can in the manufacturing process of array base palte, reduce mask technique number of times, thereby reduction manufacturing cost, simplification of flowsheet, enhances productivity.
It should be noted that, in above-mentioned steps S11a3, can adopt existing manufacturing process, first deposited semiconductor film on gate insulation layer 24, and form semiconductor active layer 34 by a composition technique; Depositing metal films again, and form by a composition technique figure that comprises data wire 21, source electrode 22, drain electrode 23.Step S11a3 adopts twice composition technique to complete like this.In order further to reduce the number of times of mask technique, optional, the semiconductor active layer of step S11a3, data wire, source electrode, drain electrode can also form by a composition PROCESS FOR TREATMENT, specifically can be made by following methods, as shown in Figure 10～Figure 16,
S11a31, on gate insulation layer 24 deposited semiconductor film 31, as shown in figure 10;
S11a32, on this semiconductive thin film 31, deposit the second metallic film 32, as shown in figure 11;
S11a33, on this second metallic film 32, be coated with photoresist 33, utilize gray scale mask plate or pellicle mask board to explosure, on this second metallic film, form photoresist half reserve area 332 of the complete reserve area 331 of photoresist of respective data lines region, source region, drain region, corresponding channel region after developing, and the photoresist that exposes described the second metallic film removes region completely, as shown in figure 12.
S11a34, etch away photoresist by etching processing and remove the second metallic film 32 and the semiconductive thin film 31 in region completely, as shown in figure 13.
S11a35, get rid of the photoresist 332 of photoresist half reserve area 332 by ashing processing, exposed portions serve the second metallic film 321, as shown in figure 14.
S11a36, described the second metallic film 321 exposing is carried out to etching, to form raceway groove 34, as shown in figure 15.
S11a37, peel off the photoresist of the complete reserve area 331 of photoresist, to obtain comprising semiconductor active layer 31, the figure of data wire 21, source electrode 22, drain electrode 23, as shown in figure 16.
So, because active layer, data wire and source electrode, drain electrode make by a composition technique, from and reduced mask 1 time, make only to have used mask technique 4 times in the process of manufacturing this array base palte, thereby further reduce manufacturing cost, simplification of flowsheet, enhances productivity.
The array base palte that the embodiment of the present invention provides, comprising with reference to figure 9 or Fig. 9 ':
Wherein, described data wire extra play 252, described pixel electrode 253, described passivation layer 261 can utilize common mask plate to obtain by a composition PROCESS FOR TREATMENT.
Wherein, be formed on grid line, grid 201, gate insulation layer, semiconductor active layer, data wire 21, source electrode 22, drain electrode 23 on this substrate 20, its concrete structure can be as shown in Figure 9, is formed on grid line (not shown), grid 201 on described substrate; Be formed on the gate insulation layer 24 on described substrate 20, described grid line, described grid 201; Be formed on the semiconductor active layer 31 on described gate insulation layer 24; Be formed on source electrode 22, the drain electrode 23 on described semiconductor active layer 31 and be formed on the data wire 21 on described gate insulation layer 24; In addition,, as shown in Fig. 9 ', its structure can also be formed in semiconductor active layer 34 and the doped semiconductor active layer 36 on described substrate 20; Wherein, described doped semiconductor active layer 36 is positioned at the both sides of described semiconductor active layer 34; Be formed on the first grid insulating barrier 38 on described substrate 20, described semiconductor active layer 34 and described doped semiconductor active layer 36; Be formed on grid line (not shown), grid 201 on described first grid insulating barrier 38; Be formed on the second insulating barrier 37 on described grid line (not shown), grid 201; Be formed on data wire 21, source electrode 22, drain electrode 23 on described second gate insulating barrier 37; Wherein, described source electrode 22 is connected with the described doped semiconductor active layer 36 of described semiconductor active layer 34 1 sides by the 5th via hole 35, and described drain electrode 23 is connected with the described doped semiconductor active layer 36 of described semiconductor active layer opposite side by the 6th via hole 35.
It should be noted that, because data wire 21 tops are formed with data wire extra play 252, can effectively reduce like this resistance on data wire, improve the quality of products.
The array base palte that the embodiment of the present invention provides, depositing successively after the first transparent conductive film and insulation film, form pixel electrode and patterned passivation layer by a composition PROCESS FOR TREATMENT, and within the edge of the pixel electrode after etching processing is positioned at the scope of this passivation layer, and, above data wire, be formed with data wire extra play, compare prior art, in the manufacturing process of array base palte, reduce mask technique number of times (being masking process number of times), thereby reduction manufacturing cost, simplification of flowsheet, enhance productivity, and can effectively reduce the resistance on data wire, thereby further improve the quality of products.
Preferably, the thickness of pixel electrode is less than the thickness of public electrode, like this, has guaranteed that the intersection of public electrode and passivation layer there will not be tomography bad, has further guaranteed product quality.Concrete, this pixel electrode can be that thickness is
indium tin oxide films, this public electrode can be that thickness is
indium tin oxide films.
The embodiment of the present invention also provides a kind of display unit, and it comprises above-mentioned any one array base palte.Described display unit can be: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, any be familiar with those skilled in the art the present invention disclose technical scope in; can expect easily changing or replacing, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (14)
1. a manufacture method for array base palte, is characterized in that, comprising:
On substrate, form the figure that comprises grid line, grid, gate insulation layer, semiconductor active layer, data wire, source electrode and drain electrode;
In described gate insulation layer, described semiconductor active layer, described data wire, described source electrode and described drain electrode, deposit successively the first transparent conductive film and insulation film;
Form and comprise the pixel electrode being connected with described drain electrode being formed by described the first transparent conductive film that is positioned at pixel electrode area by a composition PROCESS FOR TREATMENT, be positioned at the data wire extra play being formed by described the first transparent conductive film in data wire region, be positioned at the passivation layer being formed by described insulation film of the described pixel electrode of covering of pixel electrode area, data wire region, source region, drain region, described data wire extra play, described source electrode, described drain electrode; Wherein, within the edge of described pixel electrode is positioned at the coverage of described passivation layer;
On described passivation layer, deposit the second transparent conductive film, form the public electrode with slit by composition PROCESS FOR TREATMENT.
2. the manufacture method of array base palte according to claim 1, is characterized in that, described on substrate form comprise that the figure of grid line, grid, gate insulation layer, semiconductor active layer, data wire, source electrode and drain electrode comprises:
On substrate, deposit the first metallic film, form the figure that comprises grid line, grid by composition PROCESS FOR TREATMENT;
On described grid line, grid and described substrate, form gate insulation layer;
On described gate insulation layer, form the figure that comprises semiconductor active layer, data wire, source electrode, drain electrode.
3. the manufacture method of array base palte according to claim 1, is characterized in that, described on substrate form comprise that the figure of grid line, grid, gate insulation layer, semiconductor active layer, data wire, source electrode and drain electrode comprises:
Deposited semiconductor film on substrate, and form by a composition PROCESS FOR TREATMENT figure that comprises semiconductor active layer;
On described semiconductor active layer, form first grid insulating barrier, and on described first grid insulating barrier, form the first via hole and the second via hole by a composition PROCESS FOR TREATMENT, wherein, described the first via hole, the second via hole lay respectively at the two ends of described semiconductor active layer, and expose described semiconductor active layer;
On described first grid insulating barrier, deposit the first metallic film, and form by a composition PROCESS FOR TREATMENT figure that comprises grid line, grid;
Pass through ion implantation technology take described grid as mask, make the described semiconductor active layer outside described grid coverage be converted into doped semiconductor active layer;
On described grid line, grid, form second gate insulating barrier, and on described second gate insulating barrier, form the 3rd via hole and the 4th via hole by a composition PROCESS FOR TREATMENT; Wherein, corresponding described the first via hole of described the 3rd via hole, and expose described the first via hole; Corresponding described the second via hole of described the 4th via hole, and expose described the second via hole;
On described second gate insulating barrier, form the figure that comprises data wire, source electrode and drain electrode.
4. according to the manufacture method of the arbitrary described array base palte of claim 1～3, it is characterized in that, form and comprise the pixel electrode being connected with described drain electrode being formed by described the first transparent conductive film that is positioned at pixel electrode area by a composition PROCESS FOR TREATMENT, be positioned at the data wire extra play being formed by described the first transparent conductive film in data wire region, be positioned at pixel electrode area, data wire region, source region, the described pixel electrode of covering of drain region, described data wire extra play, described source electrode, the passivation layer being formed by described insulation film of described drain electrode, wherein, the edge of described pixel electrode is positioned within the coverage of described passivation layer and comprises:
On described insulation film, be coated with photoresist, form and comprise the photoresist reserve area of respective data lines region, pixel electrode area, source region, drain region on described insulation film through overexposure, after developing, and the photoresist that exposes described insulation film is removed region completely;
Etch away described photoresist by the first etching processing and remove the insulation film in region completely, form the passivation layer that is positioned at described the first transparent conductive film of covering that comprises described pixel electrode area, described data wire region, described source region, described drain region;
Etch away described the first transparent conductive film exposing by the second etching processing, form and comprise the data wire extra play that is positioned at data wire region and the pixel electrode that is positioned at pixel electrode area; Wherein, within the edge of described pixel electrode is positioned at the coverage of described passivation layer;
Peel off remaining photoresist.
5. according to the manufacture method of the arbitrary described array base palte of claim 1～3, it is characterized in that, form and comprise the pixel electrode being connected with described drain electrode being formed by described the first transparent conductive film that is positioned at pixel electrode area by a composition PROCESS FOR TREATMENT, be positioned at the data wire extra play being formed by described the first transparent conductive film in data wire region, be positioned at pixel electrode area, data wire region, source region, the described pixel electrode of covering of drain region, described data wire extra play, described source electrode, the passivation layer being formed by described insulation film of described drain electrode, wherein, the edge of described pixel electrode is positioned within the coverage of described passivation layer and comprises:
On described insulation film, be coated with photoresist, form and comprise the photoresist reserve area of respective data lines region, pixel electrode area, source region, drain region on described insulation film through overexposure, after developing, and the photoresist that exposes described insulation film is removed region completely;
Etch away described photoresist by the first etching processing and remove the insulation film in region completely, form the patterned passivation layer that is positioned at described the first transparent conductive film of covering that comprises described pixel electrode area, described data wire region, described source region, described drain region;
Peel off residue photoresist;
Etch away described the first transparent conductive film exposing by the second etching processing, form and comprise the data wire extra play that is positioned at data wire region and the pixel electrode that is positioned at pixel electrode area; Wherein, within the edge of described pixel electrode is positioned at the coverage of described passivation layer.
6. the manufacture method of array base palte according to claim 2, is characterized in that, on described gate insulation layer, forms and comprises that the figure of semiconductor active layer, data wire, source electrode, drain electrode comprises:
Deposited semiconductor film on described gate insulation layer;
On described semiconductive thin film, deposit the second metallic film;
On described the second metallic film, be coated with photoresist, utilize gray scale mask plate or pellicle mask board to explosure, on described the second metallic film, form the complete reserve area of photoresist of respective data lines region, source region, drain region after developing, photoresist half reserve area of corresponding channel region, and the photoresist that exposes described the second metallic film is removed region completely;
Etch away photoresist by etching processing and remove described the second metallic film and the semiconductive thin film in region completely;
Get rid of the photoresist of described photoresist half reserve area by ashing processing, exposed portions serve the second metallic film;
Described the second metallic film exposing is carried out to etching, to form raceway groove;
Peel off the photoresist of the complete reserve area of photoresist, to obtain comprising semiconductor active layer, the figure of data wire, source electrode, drain electrode.
7. the manufacture method of array base palte according to claim 1, is characterized in that, the thickness of described pixel electrode is less than the thickness of described public electrode.
8. the manufacture method of array base palte according to claim 7, is characterized in that, the thickness of described pixel electrode is
the thickness of described public electrode is
9. an array base palte, is characterized in that, comprising:
Substrate;
Be formed on grid line, grid, gate insulation layer, semiconductor active layer, data wire, source electrode and drain electrode on described substrate;
Be formed on the conduction that comprises described data wire top data wire extra play, be formed on the pixel electrode of pixel electrode area; Wherein, described data wire extra play is identical with layer and material with described pixel electrode;
Be formed on the passivation layer comprising on described data wire extra play and described pixel electrode; Wherein, within the edge of described pixel electrode is positioned at the coverage of described passivation layer, and the edge of described pixel electrode and the edge of described passivation layer vicinity;
Be formed on the public electrode on described passivation layer.
10. array base palte according to claim 9, is characterized in that, the grid line, grid, gate insulation layer, semiconductor active layer, data wire, source electrode and the drain electrode that are formed on described substrate comprise:
Be formed on grid line, grid on described substrate;
Be formed on the gate insulation layer on described substrate, described grid line, grid;
Be formed on the semiconductor active layer on described gate insulation layer;
Be formed on source electrode on described semiconductor active layer, drain and be formed on the data wire on described gate insulation layer.
11. array base paltes according to claim 9, is characterized in that, the grid line, grid, gate insulation layer, semiconductor active layer, data wire, source electrode and the drain electrode that are formed on described substrate comprise:
Be formed on semiconductor active layer and doped semiconductor active layer on described substrate; Wherein, described doped semiconductor active layer is positioned at the both sides of described semiconductor active layer;
Be formed on the first grid insulating barrier on described substrate, described semiconductor active layer and described doped semiconductor active layer;
Be formed on grid line, grid on described first grid insulating barrier;
Be formed on the second gate insulating barrier on described grid line, grid;
Be formed on data wire, source electrode, drain electrode on described second gate insulating barrier; Wherein, described source electrode is connected with the described doped semiconductor active layer of described semiconductor active layer one side by the 5th via hole, and described drain electrode is connected with the described doped semiconductor active layer of described semiconductor active layer opposite side by the 6th via hole.
12. according to the arbitrary described array base palte of claim 9～11, it is characterized in that, the thickness of described pixel electrode is less than the thickness of described public electrode.
13. array base paltes according to claim 12, is characterized in that, the thickness of described pixel electrode is
the thickness of described public electrode is
14. 1 kinds of display unit, is characterized in that, comprise the array base palte described in claim 9-13 any one.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN201210195627.8A CN102723309B (en) | 2012-06-13 | 2012-06-13 | Array substrate and manufacturing method thereof as well as display device |
| PCT/CN2012/086309 WO2013185454A1 (en) | 2012-06-13 | 2012-12-10 | Array substrate, fabrication method thereof, and display device |
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| CN201210195627.8A CN102723309B (en) | 2012-06-13 | 2012-06-13 | Array substrate and manufacturing method thereof as well as display device |
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| CN102723309B (en) * | 2012-06-13 | 2014-07-02 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof as well as display device |
| CN103579104A (en) * | 2012-08-02 | 2014-02-12 | 北京京东方光电科技有限公司 | Array substrate, preparation method thereof and display device |
| CN104617040A (en) | 2015-02-05 | 2015-05-13 | 京东方科技集团股份有限公司 | Manufacturing method of array substrate, display substrate and display device |
| CN105826328B (en) | 2016-05-03 | 2019-03-05 | 京东方科技集团股份有限公司 | Array substrate and its manufacturing method, display device |
| CN106229347B (en) * | 2016-08-24 | 2019-06-07 | 武汉华星光电技术有限公司 | A kind of low-temperature polysilicon film transistor and its manufacturing method |
| CN108847408A (en) * | 2018-06-04 | 2018-11-20 | 深圳市华星光电技术有限公司 | A kind of manufacturing method and tft array substrate of tft array substrate |
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| JP4645488B2 (en) * | 2006-03-15 | 2011-03-09 | ソニー株式会社 | Liquid crystal device and electronic device |
| KR20080110063A (en) * | 2007-06-14 | 2008-12-18 | 엘지디스플레이 주식회사 | Liquid crystal display device and method of manufacturing the same |
| JP2009036947A (en) * | 2007-08-01 | 2009-02-19 | Seiko Epson Corp | Method for manufacturing liquid crystal device, and liquid crystal device |
| JP5329062B2 (en) * | 2007-08-29 | 2013-10-30 | 株式会社ジャパンディスプレイ | Organic EL display device |
| CN101577254B (en) * | 2009-03-30 | 2011-03-23 | 上海广电光电子有限公司 | Method for manufacturing thin film transistor array substrate |
| CN102142396B (en) * | 2011-03-02 | 2013-09-18 | 深超光电（深圳）有限公司 | Fringe electric field type liquid crystal display array substrate and manufacture method thereof |
| CN102723309B (en) * | 2012-06-13 | 2014-07-02 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof as well as display device |
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| CN101546733A (en) * | 2008-03-28 | 2009-09-30 | 北京京东方光电科技有限公司 | Method for manufacturing TFT-LCD array substrate and color film substrate |
| EP2302445A1 (en) * | 2009-09-23 | 2011-03-30 | LG Display Co., Ltd. | Liquid crystal display device and method of driving the same |
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