CN105070765B - Thin film transistor (TFT), array substrate, display device and manufacturing method - Google Patents

Thin film transistor (TFT), array substrate, display device and manufacturing method Download PDF

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CN105070765B
CN105070765B CN201510570320.5A CN201510570320A CN105070765B CN 105070765 B CN105070765 B CN 105070765B CN 201510570320 A CN201510570320 A CN 201510570320A CN 105070765 B CN105070765 B CN 105070765B
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layer
electrode
source electrode
thin film
film transistor
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CN105070765A (en
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齐峰
王珂
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BOE Technology Group Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

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  • Engineering & Computer Science (AREA)
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  • Crystallography & Structural Chemistry (AREA)
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  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

The invention discloses a kind of thin film transistor (TFT), array substrate, display device and manufacturing methods, belong to field of display technology.Thin film transistor (TFT) includes source electrode, drain electrode, active layer, gate insulation layer and grid；Active layer and drain electrode are located on the same floor, and the material of active layer includes metal oxide, and the material of drain electrode includes the metal oxide of conductor；Source electrode and gate insulation layer are located at the same side of active layer, and source electrode and gate insulation layer are in contact with the same side of active layer, and gate insulation layer is located between source electrode and drain electrode, and the thickness of gate insulation layer is greater than the thickness of source electrode, and the material of source electrode includes metal；Grid being in contact on one side far from active layer with gate insulation layer.The material of the drain electrode of thin film transistor (TFT) of the invention includes the metal oxide of conductor, the material of source electrode includes metal, source electrode and data line are that source layer is formed by patterning processes, so the material of data line and the material of source electrode include metal, solve the problems, such as signal delay.

Description

Thin film transistor, array substrate, display device and manufacturing method
Technical Field
The invention relates to the technical field of display, in particular to a thin film transistor, an array substrate, a display device and a manufacturing method.
Background
The liquid crystal display gradually develops towards large size, high image quality and low energy consumption, and the structure of the liquid crystal display comprises a liquid crystal layer arranged between two parallel substrates, wherein the lower substrate is an array substrate, the upper substrate is a color film substrate, and the rotation direction of liquid crystal molecules is controlled by changing the voltage on the array substrate, so that the purpose of controlling the transmittance of incident light of each pixel point to achieve display is achieved.
The array substrate comprises a substrate, a data line, a source electrode, a drain electrode, a pixel electrode, a grid line and a grid insulating layer, wherein each electrode and each signal line are mainly formed on the substrate of the array substrate through a composition process, the data line and the source electrode are formed simultaneously in one composition process, and the grid line and the grid electrode are formed simultaneously in one composition process.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems:
the existing source electrode and data line materials can select conductive metal oxide, and the use of conductive metal oxide as data line can cause serious signal delay phenomenon, thereby affecting the display quality of the liquid crystal display.
Disclosure of Invention
In order to solve the problems in the prior art, embodiments of the present invention provide a thin film transistor, an array substrate, a display device, and a manufacturing method. The technical scheme is as follows:
a thin film transistor includes a source electrode, a drain electrode, an active layer, a gate insulating layer, and a gate electrode;
the active layer and the drain electrode are positioned on the same layer, the material of the active layer comprises metal oxide, and the material of the drain electrode comprises conductive metal oxide;
the source electrode and the gate insulating layer are positioned on the same side of the active layer, the source electrode and the gate insulating layer are in contact with the same side of the active layer, the gate insulating layer is positioned between the source electrode and the drain electrode, the thickness of the gate insulating layer is greater than that of the source electrode, and the source electrode is made of metal;
the grid electrode is in contact with one surface, far away from the active layer, of the grid insulating layer.
An array substrate including a gate line, a data line, and a plurality of pixel units into which the gate line, the data line, and the data line are divided, the pixel units including a pixel electrode and the thin film transistor,
the pixel electrode, the active layer of the thin film transistor and the drain electrode are located on the same layer, the drain electrode is connected with the pixel electrode, and the material of the pixel electrode comprises a conductive metal oxide.
Optionally, the array substrate further comprises a passivation layer covering the source electrode, the gate electrode, the drain electrode and the pixel electrode.
Optionally, a buffer metal layer is further disposed below the source electrode of the thin film transistor, and the buffer metal layer is located between the source electrode and the active layer.
Optionally, the array substrate further includes a common electrode, and the common electrode is located on the passivation layer.
A display device comprises a display panel, and is characterized in that the display panel comprises the array substrate.
A method of manufacturing an array substrate, the method comprising:
forming a metal oxide layer on a substrate base plate, the metal oxide layer including a first portion, a second portion and a third portion, the first portion being an active layer, the second portion being between the first portion and the third portion, depositing a source layer on the metal oxide layer, the source layer including a metal,
patterning the source layer by a one-step composition process to form a pattern comprising a source electrode of the thin film transistor;
depositing a gate insulating layer and a gate electrode layer on the source electrode, the active layer, the second portion, and the third portion;
and patterning the gate insulating layer and the gate electrode layer by a one-step patterning process to form a pattern including a gate electrode and a gate insulating layer of the thin film transistor, and forming the second portion into a pattern including a drain electrode of the thin film transistor, and forming the third portion into a pattern including a pixel electrode of the thin film transistor.
Optionally, the patterning the second portion to include a drain electrode of the thin film transistor, and the patterning the third portion to include a pixel electrode of the thin film transistor include:
and bombarding the metal oxide layers corresponding to the second part and the third part by using vacuum plasma gas, forming a pattern comprising the drain electrode on the second part, and forming a pattern comprising the pixel electrode on the third part.
Optionally, the manufacturing method of the array substrate further includes:
depositing a passivation layer on the source electrode, the gate electrode, the drain electrode and the pixel electrode.
Optionally, the manufacturing method of the array substrate further includes:
and depositing a common electrode layer on the passivation layer, and patterning the common electrode layer through a one-time composition process to form a pattern of a common electrode.
Optionally, the material of the metal oxide layer includes a single-layer metal oxide composed of any one of aluminum zinc oxide, indium gallium zinc oxide, and indium tin zinc oxide, or a multi-layer metal oxide composed of any several of aluminum zinc oxide, indium gallium zinc oxide, and indium tin zinc oxide.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
the active layer and the drain electrode of the thin film transistor are positioned on the same layer, the material of the active layer comprises metal oxide, the material of the drain electrode comprises conductive metal oxide, the material of the source electrode comprises metal, the source electrode is positioned on the active layer and is in contact with one side surface of the active layer, and the source electrode and the data line are formed by the source electrode layer through one-time composition process, so that the material of the data line is the same as that of the source electrode and comprises metal, and the problem of signal delay is solved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an array substrate according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of an array substrate according to a second embodiment of the present invention;
fig. 4 is a schematic structural diagram of an array substrate according to a second embodiment of the present invention;
fig. 5 is a schematic structural diagram of an array substrate according to a second embodiment of the present invention;
fig. 6 is a schematic structural diagram of an array substrate according to a second embodiment of the present invention;
fig. 7 to 21 are schematic views illustrating a manufacturing process of an array substrate according to a fourth embodiment of the present invention.
Wherein,
1 source electrode, 2 drain electrode, 3 active layer, 4 gate insulating layer,
5 a gate electrode, 6 a substrate, 7 a pixel electrode, 8 a buffer metal layer,
9 a passivation layer, 10 a common electrode, 11 a metal oxide layer, 12 a source layer,
a layer of 13 photoresist, 14 gate layer,
a gate line, a data line, a thin film transistor,
d a first part, E a second part, F a third part,
the G photoresist is completely left in the region,
h photoresist half-retaining region, H1 first photoresist half-retaining region, H2 second photoresist half-retaining region.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Example one
As shown in fig. 1, an embodiment of the present invention provides a thin film transistor including a source electrode 1, a drain electrode 2, an active layer 3, a gate insulating layer 4, and a gate electrode 5;
the active layer 3 and the drain electrode 2 are positioned on the same layer, the material of the active layer 3 comprises metal oxide, and the material of the drain electrode 2 comprises conductive metal oxide;
the source electrode 1 and the gate insulating layer 4 are positioned on the same side of the active layer 3, the source electrode 1 and the gate insulating layer 4 are in contact with the same side of the active layer 3, the gate insulating layer 4 is positioned between the source electrode 1 and the drain electrode 2, the thickness of the gate insulating layer 4 is greater than that of the source electrode 1, and the source electrode 1 is made of metal;
the gate electrode 5 is in contact with a side of the gate insulating layer 4 remote from the active layer 3.
In the embodiment of the invention, the active layer 3 and the drain electrode 2 of the thin film transistor are located in the same layer, the material of the active layer 3 comprises a metal oxide, the material of the drain electrode 2 comprises a conductive metal oxide, the thickness of the gate insulating layer 4 is greater than that of the source electrode 1, short circuit between the gate electrode 5 and the source electrode 1 is avoided, the material of the source electrode 1 comprises a metal, the source electrode 1 is located above the active layer 3 and is in contact with one side surface of the active layer 3, and the source electrode 1 and the data line are formed by a patterning process, so that the material of the data line and the material of the source electrode 1 both comprise metals, and the metal material can better receive and transmit signals, thereby solving the problem of signal delay.
Example two
As shown in fig. 2 and referring to fig. 3, an embodiment of the present invention provides an array substrate, which includes a plurality of pixel units formed on a substrate 6 and divided by gate lines a, data lines B, and gate lines a and data lines B, the pixel units including pixel electrodes 7 and thin film transistors C as described in the first embodiment,
as shown in fig. 3, the pixel electrode 7, the active layer 3 of the thin film transistor C, and the drain electrode 2 are located in the same layer, the drain electrode 2 is connected to the pixel electrode 7, and the material of the pixel electrode 7 includes a conductive metal oxide.
As shown in fig. 3, in the embodiment of the invention, the active layer 3, the drain electrode 2, and the pixel electrode 7 of the array substrate are located in the same layer, the material of the active layer 3 includes a metal oxide, the material of the drain electrode 2 and the pixel electrode 7 both include a conductive metal oxide, the thickness of the gate insulating layer 4 is greater than the thickness of the source electrode 1, so as to prevent a short circuit from occurring between the gate electrode 5 and the source electrode 1 due to contact, the material of the source electrode 1 includes a metal, the source electrode 1 is located above the active layer 3 and contacts with one side of the active layer 3, and the source electrode 1 and the data line B are formed by patterning process, so the material of the data line B and the material of the source electrode 1 both include metals, and the metal materials can better receive and transmit signals, thereby solving the problem of signal delay.
Optionally, as shown in fig. 4, a buffer metal layer 8 is further disposed below the source 1 of the thin film transistor, the buffer metal layer 8 is located between the source 1 and the active layer 3, and the buffer metal layer 8 can enable the source 1 to be better deposited on the active layer 3.
Optionally, as shown in fig. 5, the array substrate further includes a passivation layer 9, and the passivation layer 9 covers the source electrode 1, the gate electrode 5, the drain electrode 2, and the pixel electrode 7.
The passivation layer 9 may protect the source electrode 1, the gate electrode 5, the drain electrode 2, and the pixel electrode 7.
Optionally, the material of the passivation layer 9 comprises SiNx.
SiNx is used as a material of the passivation layer 9, during deposition, the used gas comprises ammonia gas which contains more hydrogen, so that the resistance of the drain electrode 2 and the pixel electrode 7 which are formed by the metal oxide which is converted into a conductor in the deposition process can be further reduced, and meanwhile, the SiNx is used for replacing SiO2As the material of the passivation layer 9, the oxidation of the source electrode 1 during the deposition of the passivation layer 9 can also be avoided, since SiO is deposited2When it is necessary to use N2O gas, N2Oxygen in the O gas oxidizes the source electrode 1, which is a material including metal.
Optionally, as shown in fig. 6, the array substrate further includes a common electrode 10, and the common electrode 10 is located on the passivation layer 9.
If the array substrate in this embodiment is also used for manufacturing a display panel in a multi-dimensional electric field mode, a common electrode needs to be manufactured on the array substrate, as shown in fig. 6, a common electrode layer is deposited on the passivation layer 9, and a common electrode 10 is formed through a patterning process.
In the embodiment of the invention, the active layer 3, the drain electrode 2 and the pixel electrode 7 of the array substrate are located in the same layer, the material of the active layer 3 comprises a metal oxide, the material of the drain electrode 2 and the pixel electrode 7 both comprise a conductive metal oxide, the material of the source electrode 1 comprises a metal, the source electrode 1 is located above the active layer 3 and is in contact with one side of the active layer 3, and the source electrode 1 and the data line B are formed by the patterning process of the source layer 12, so that the material of the data line B and the material of the source electrode 1 both comprise metals, and the problem of signal delay is solved.
EXAMPLE III
An embodiment of the present invention provides a display device, including a display panel, where the display panel includes the array substrate according to the second embodiment.
In the embodiment of the invention, the active layer 3, the drain electrode 2 and the pixel electrode 7 of the array substrate adopted by the display panel in the display device are located in the same layer, the material of the active layer 3 comprises a metal oxide, the materials of the drain electrode 2 and the pixel electrode 7 both comprise a conductive metal oxide, the material of the source electrode 1 comprises a metal, the source electrode 1 is located above the active layer 3 and is in contact with one side surface of the active layer 3, and the source electrode 1 and the data line B are formed by the patterning process of the source layer 12, so that the material of the data line B and the material of the source electrode 1 both comprise metals, and the metal materials can better receive and transmit signals, thereby solving the problem of signal delay.
Example four
The embodiment of the invention provides a manufacturing method of an array substrate, which comprises the following steps:
step 101: as shown in fig. 7, a metal oxide layer 11 is formed on the substrate base plate 6, the metal oxide layer 11 includes a first portion D, a second portion E and a third portion F, the first portion D is the active layer 3, the second portion E is located between the first portion D and the third portion F, a source layer 12 is deposited on the metal oxide layer 11, a material of the source layer 12 includes a metal,
specifically, as shown in fig. 7, a metal oxide layer 11 is formed on a substrate base plate 6;
thereafter, as shown in fig. 7, a source layer 12 is deposited on the metal oxide layer 11.
Step 102: patterning the source layer 12 by a one-time patterning process to form a pattern including the source electrode 1 of the thin film transistor;
specifically, as shown in fig. 8, a layer of photoresist 13 is coated on the source layer 12;
then, exposing and developing the photoresist 13 by using a halftone or gray tone mask, as shown in fig. 9, so that the photoresist 13 forms a photoresist complete retention region G and a photoresist semi-retention region H, wherein the photoresist complete retention region G at least corresponds to the region where the source electrode 1 is located, and the photoresist semi-retention region H at least corresponds to a portion of the active layer 3, the drain electrode 2 and the pixel electrode 7;
thereafter, as shown in fig. 10 and referring to fig. 9, the metal oxide layer 11 and the source layer 12 except for the photoresist completely-remaining region G and the photoresist semi-remaining region H are completely etched away by one etching process;
thereafter, as shown in fig. 11 and with reference to fig. 10, the photoresist 13 in the photoresist half-remaining region H is removed by an ashing process to expose the source layer 12 in the region, as shown in fig. 11 and with reference to fig. 10, which also thins the photoresist 13 in the photoresist full-remaining region G;
then, as shown in fig. 12 and referring to fig. 10, the source layer 12 corresponding to the photoresist half-remaining region H is completely etched away by one etching process;
thereafter, as shown in FIG. 11, the remaining photoresist G is stripped, and as shown in FIG. 12, the source electrode 1 is patterned.
Step 103: as shown in fig. 13, the gate insulating layer 4 and the gate electrode layer 14 are deposited on the source electrode 1, the active layer 3, the second portion E and the third portion F of the metal oxide layer 11;
specifically, as shown in fig. 13, the gate insulating layer 4 is first deposited on the source electrode 1, the active layer 3, the second portion E and the third portion F of the metal oxide layer 11;
thereafter, as shown in fig. 13, a gate electrode layer 14 is deposited on the gate insulating layer 4.
Step 104: the gate insulating layer 4 and the gate electrode layer 14 are patterned by a single patterning process to form a pattern including the gate electrode 5 and the gate insulating layer 4 of the thin film transistor, and the second portion E is patterned to form a pattern including the drain electrode 2 of the thin film transistor, and the third portion F is patterned to form a pattern including the pixel electrode 7 of the thin film transistor.
Specifically, as shown in fig. 14, a layer of photoresist 13 is coated on the gate layer 14;
then, exposing and developing the photoresist 13 by using a halftone or gray tone mask, as shown in fig. 15, so that the photoresist 13 forms a photoresist complete retention region G and a photoresist semi-retention region H, where the photoresist semi-retention region H is divided into a first photoresist semi-retention region H1 and a second photoresist semi-retention region H2, the photoresist complete retention region G at least corresponds to the region where the gate 5 is located, the region where the gate 5 is located corresponds to a portion where the active layer 3 is located, the first photoresist semi-retention region H1 at least corresponds to the region where the source 1 is located, and the second photoresist semi-retention region H2 at least corresponds to the second portion E and the third portion F of the metal oxide layer 11, that is, the regions where the drain 2 and the pixel electrode 7 are located;
as shown in fig. 16, and referring to fig. 15, the gate insulating layer 4 and the gate electrode layer 14 except for the photoresist-completely-remaining region G and the photoresist-semi-remaining region H are completely etched away by one etching process;
thereafter, as shown in fig. 17, and with reference to fig. 16, the photoresist 13 in the first photoresist semi-reserved region H1 and the second photoresist semi-reserved region H2 is removed by an ashing process, which also thins the photoresist 13 in the photoresist complete reserved region G, as shown in fig. 17, and with reference to fig. 16, exposing the gate layer 14 in the first photoresist semi-reserved region H1 and the second photoresist semi-reserved region H2;
as shown in fig. 18 and referring to fig. 16, the gate layer 14 and the gate insulating layer 4 corresponding to the first photoresist semi-reserved region H1 are completely etched away by one etching process, exposing the source 1;
as shown in fig. 19, and referring to fig. 16, the gate electrode layer 14 and the gate insulating layer 4 corresponding to the second photoresist semi-reserved region H2 are completely etched away by one etching process, exposing the metal oxide layer 11 of the second portion E and the third portion F;
finally, as shown in fig. 20, the remaining photoresist G is stripped, the gate electrode 5 is patterned, the second portion E of the metal oxide layer 11 is patterned to include the drain electrode 2 of the thin film transistor, and the third portion F of the metal oxide layer 11 is patterned to include the pixel electrode 7 of the thin film transistor.
In the embodiment of the invention, the active layer 3, the drain electrode 2 and the pixel electrode 7 of the array substrate are located in the same layer, the material of the active layer 3 includes a metal oxide, the material of the drain electrode 2 and the pixel electrode 7 both include a conductive metal oxide, the material of the source electrode 1 includes a metal, the source electrode 1 is located above the active layer 3 and is in contact with one side of the active layer 3, and the source electrode 1 and the data line B are formed by the patterning process of the source layer 12, so that the material of the data line B and the material of the source electrode 1 both include metals, and the metal material can better receive and transmit signals, thereby solving the problem of signal delay.
Alternatively, patterning the second portion E to include the drain electrode 2 of the thin film transistor and patterning the third portion F to include the pixel electrode 7 of the thin film transistor include:
as shown in fig. 19, and referring to fig. 20, the metal oxide layer 11 corresponding to the second portion E and the third portion F is bombarded with vacuum plasma gas, a pattern including the drain electrode 2 is formed in the second portion E, and a pattern including the pixel electrode 7 is formed in the third portion F.
As shown in fig. 16 and referring to fig. 20, if the gate layer 14 and the gate insulating layer 4 corresponding to the second photoresist semi-reserved region H2 are completely etched by a dry etching process, the metal oxide layer 11 corresponding to the second portion E and the third portion F will exhibit a tendency of conductor during the dry etching process to form a pattern of the drain electrode 2 and a pattern of the pixel electrode 7, respectively, and a gas used in the dry etching process includes CF4And O2Or He and O2Wherein CF4The plasma gas of (2) or the plasma gas of He can function to make the metal oxide conductive;
if the drain electrode 2 and the pixel electrode 7 formed after dry etching have better conductor tendency, the surfaces of the drain electrode 2 and the pixel electrode 7 can be bombarded by vacuum plasma gas, and ammonia gas or hydrogen gas can be selected.
In the embodiment of the invention, the drain electrode 2 and the pixel electrode 7 of the array substrate are positioned on the same layer, and the material of the drain electrode 2 and the pixel electrode 7 comprises the conductive metal oxide, so that the composition process is saved, and meanwhile, the aperture opening ratio of the array substrate can be increased, the backlight power consumption can be reduced, and the energy can be saved because the material of the drain electrode 2 comprises the metal oxide.
Optionally, the manufacturing method of the array substrate further includes:
a passivation layer 9 is deposited on the source electrode 1, the gate electrode 5, the drain electrode 2 and the pixel electrode 7.
As shown in fig. 21, a passivation layer 9 is deposited on the source electrode 1, the gate electrode 5, the drain electrode 2, and the pixel electrode 7, and the passivation layer 9 may protect the source electrode 1, the gate electrode 5, the drain electrode 2, and the pixel electrode 7.
Optionally, as shown in fig. 6, the method for manufacturing an array substrate further includes:
a common electrode layer is deposited on the passivation layer 9 and patterned by a one-step patterning process to form a pattern of a common electrode 10.
If the array substrate in this embodiment is also used for manufacturing a display panel in a multi-dimensional electric field mode, a common electrode layer may be deposited on the passivation layer 9, and a pattern of the common electrode 10 may be formed through a patterning process. As shown in fig. 6, a common electrode layer is deposited on the passivation layer 9, and a pattern of the common electrode 10 is formed through a one-time patterning process.
Optionally, the material of the metal oxide layer 11 includes a single-layer metal oxide made of any one of aluminum zinc oxide, indium gallium zinc oxide, and indium tin zinc oxide, or a multi-layer metal oxide made of any several of aluminum zinc oxide, indium gallium zinc oxide, and indium tin zinc oxide.
In the embodiment of the invention, the active layer 3, the drain electrode 2 and the pixel electrode 7 of the array substrate are located in the same layer, the material of the active layer 3 includes a metal oxide, the material of the drain electrode 2 and the pixel electrode 7 both include a conductive metal oxide, the material of the source electrode 1 includes a metal, the source electrode 1 is located above the active layer 3 and is in contact with one side of the active layer 3, and the source electrode 1 and the data line B are formed by the patterning process of the source layer 12, so that the material of the data line B and the material of the source electrode 1 both include metals, and the metal material can better receive and transmit signals, thereby solving the problem of signal delay.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (11)

1. A thin film transistor includes a source electrode, a drain electrode, an active layer, a gate insulating layer, and a gate electrode;
the active layer and the drain electrode are positioned on the same layer, the material of the active layer comprises metal oxide, and the material of the drain electrode comprises conductive metal oxide;
the source electrode and the gate insulating layer are positioned on the same side of the active layer, the source electrode and the gate insulating layer are in contact with the same side of the active layer, the gate insulating layer is positioned between the source electrode and the drain electrode, the gate insulating layer is positioned between the gate electrode and the active layer, the thickness of the gate insulating layer is larger than that of the source electrode, the gate electrode is insulated from the source electrode through the gate insulating layer, the source electrode is made of metal, and the source electrode and the data line are formed by the source electrode layer through a one-step composition process;
the grid electrode is in contact with one surface, far away from the active layer, of the grid insulating layer.
2. An array substrate comprising a gate line, a data line and a plurality of pixel units into which the gate line and the data line are divided, the pixel units comprising a pixel electrode and the thin film transistor of claim 1,
the pixel electrode, the active layer of the thin film transistor and the drain electrode are located on the same layer, the drain electrode is connected with the pixel electrode, and the material of the pixel electrode comprises a conductive metal oxide.
3. The array substrate of claim 2, further comprising a passivation layer covering the source electrode, the gate electrode, the drain electrode and the pixel electrode.
4. The array substrate of claim 2, wherein a buffer metal layer is further disposed under the source electrode of the thin film transistor, and the buffer metal layer is located between the source electrode and the active layer.
5. The array substrate of claim 3, further comprising a common electrode on the passivation layer.
6. A display device comprising the array substrate according to any one of claims 2 to 5.
7. A method for manufacturing an array substrate, the method comprising:
forming a metal oxide layer on a substrate base plate, the metal oxide layer including a first portion, a second portion and a third portion, the first portion being an active layer, the second portion being between the first portion and the third portion, depositing a source layer on the metal oxide layer, the source layer including a metal,
patterning the source layer by a one-step composition process to form a pattern comprising a source electrode of the thin film transistor and a pattern comprising a data line;
depositing a gate insulating layer and a gate electrode layer on the source electrode, the active layer, the second portion, and the third portion;
and patterning the gate insulating layer and the gate electrode layer by a one-step patterning process to form a pattern including a gate electrode and a gate insulating layer of the thin film transistor, and forming the second portion into a pattern including a drain electrode of the thin film transistor, and forming the third portion into a pattern including a pixel electrode of the thin film transistor.
8. The method of claim 7, wherein patterning the second portion to include a drain electrode of the thin film transistor and patterning the third portion to include a pixel electrode of the thin film transistor comprises:
and bombarding the metal oxide layers corresponding to the second part and the third part by using vacuum plasma gas, forming a pattern comprising the drain electrode on the second part, and forming a pattern comprising the pixel electrode on the third part.
9. The method of claim 7, wherein the method of fabricating the array substrate further comprises:
depositing a passivation layer on the source electrode, the gate electrode, the drain electrode and the pixel electrode.
10. The method of claim 9, wherein the method of fabricating the array substrate further comprises:
and depositing a common electrode layer on the passivation layer, and patterning the common electrode layer through a one-time composition process to form a pattern of a common electrode.
11. The method according to any one of claims 7 to 10, wherein the material of the metal oxide layer comprises a single layer of metal oxide consisting of any one of aluminum zinc oxide, indium gallium zinc oxide and indium tin zinc oxide, or a multi-layer of metal oxide consisting of any several of aluminum zinc oxide, indium gallium zinc oxide and indium tin zinc oxide.
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