CN104681627B - Array substrate, thin film transistor (TFT) and production method, display device - Google Patents
Array substrate, thin film transistor (TFT) and production method, display device Download PDFInfo
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- 238000000059 patterning Methods 0.000 claims abstract description 55
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The invention belongs to field of display technology more particularly to a kind of array substrates, thin film transistor (TFT) and production method, display device.The array substrate includes substrate (1), the active layer (2) of same layer setting, source electrode (3), drain electrode (4), pixel electrode (5) on substrate (1)；Gate insulating layer (6) on active layer (2)；Grid (7) on gate insulating layer (6)；Active layer (2), source electrode (3), drain electrode (4), pixel electrode (5), gate insulating layer (6) and grid (7) are formed by a patterning processes, and source electrode (3) is connect by active layer (2) with drain electrode (4).The technical problems such as the structure that array substrate of the invention solves prior art array substrate is complex, manufacture craft is more, production efficiency is low, higher cost can replace existing array substrate, be applied in field of display technology.
Description
Technical field
The invention belongs to field of display technology more particularly to a kind of array substrates, thin film transistor (TFT) and production method, display
Device.
Background technique
With the rapid development of display technology, people are to characteristic requirements such as the resolution ratio of display, response time, power consumptions
It is higher and higher.In this case, as the size of display is increasing and the development of the display technologies such as 3D, exist to setting
The mobility of TFT (Thin Film Transistor, thin film transistor (TFT)) on display array substrate requires higher and higher.
The mobility of TFT refers to average drift velocity of the carrier in the active layer of TFT (electrons and holes) under unit electric field effect.
The requirement to mobility actually is had been unable to meet with amorphous silicon production active layer, people have begun using with higher migration
The metal oxide materials of rate.
MOS Technology has been increasingly becoming large scale, high image quality, the mainstream skill of low power consumption display product at present
Art, major display commercial city is in volume production or active development.Senior super dimension field switch technology (ADvanced Super
Dimension Switch, abbreviation ADS) Thin Film Transistor-LCD (Thin Film Transistor can be improved
Liquid Crystal Display, abbreviation TFT-LCD) product picture quality, have high-resolution, high transmittance, low function
The advantages that consumption, wide viewing angle, high aperture, low aberration, ripple without water of compaction (push mura).
However, the preparation process of the oxide TFT array substrate of ADS mode, it usually needs the road 7-9 exposure mask (mask) work
TFT in skill, especially array substrate just needs 5 masking process, therefore complex manufacturing technology, and production efficiency is lower, cost
It is higher.
Summary of the invention
The embodiment of the present invention provides a kind of array substrate, thin film transistor (TFT) and production method, display device, to solve
The technical problems such as thin film transistor (TFT), array substrate complex manufacturing technology, the lower, higher cost of production efficiency in the prior art, should
The structure of array substrate is simple, and manufacture craft is less, thus high production efficiency, cost is relatively low.
In order to achieve the above objectives, the embodiment of the present invention adopts the following technical scheme that
A kind of array substrate, comprising:
Substrate；
The active layer of same layer setting, source electrode, drain electrode, pixel electrode on the substrate；
Gate insulating layer on the active layer；
Grid on the gate insulating layer；
The active layer, source electrode, drain electrode, pixel electrode, gate insulating layer and grid pass through a patterning processes shape
At the source electrode is connect by the active layer with the drain electrode.
Above scheme is preferably, the array substrate further include:
Inter-level dielectric (Inter Level on the pixel electrode, source electrode, drain electrode, grid
Dielectric, abbreviation ILD), the inter-level dielectric includes the via hole of the corresponding source electrode；
Data line on the inter-level dielectric, the data line are connect by the via hole with the source electrode.
Any of the above-described scheme is preferably, the array substrate further include:
Passivation layer (passivation, abbreviation PVX) on the data line and the inter-level dielectric；
Public electrode on the passivation layer.
Any of the above-described scheme is preferably, the array substrate further include: the organic resin layer on the passivation layer,
The public electrode is located on the organic resin layer.
A kind of production method of array substrate, comprising the following steps:
Production metal oxide thin films, grid insulating film, grid film are stacked gradually on substrate；
By a patterning processes, the metal oxide thin films are formed comprising active layer and are located at pixel
Electrode zone, source electrode region, drain regions figure, by the grid insulating film formed include gate insulating layer figure
The grid film is formed the figure comprising grid by shape；The source electrode is connect by the active layer with the drain electrode；
The figure positioned at pixel electrode area, source electrode region and drain regions is subjected to conductor, forms picture
Plain electrode, source electrode and drain electrode.
Above scheme is preferably, after the formation pixel electrode, source electrode and drain electrode further include:
Production covers the interlayer medium film of the pixel electrode, source electrode, drain electrode, grid, passes through a composition work
The interlayer medium film is formed the inter-level dielectric comprising via hole by skill, and the via hole corresponds to the source electrode；
Production covers the data line film of the via hole, includes by data line film formation by a patterning processes
The figure of data line, the data line are connect by the via hole with the source electrode.
Any of the above-described scheme is preferably, described to pass through a patterning processes and form the data line film comprising data
After the figure of line further include:
The passivation layer film of production the covering data line and the inter-level dielectric, will be described blunt by a patterning processes
Change layer film and forms passivation layer；
Public electrode film is made on the passivation layer, is formed the public electrode film by a patterning processes
Figure comprising public electrode.
Any of the above-described scheme is preferably, described to pass through a patterning processes for passivation layer film formation passivation layer packet
It includes:
The organic resin film of the production covering passivation layer film；
Organic resin by the organic resin film in passivation layer region retains, the organic resin removal in other regions,
Form organic resin layer；
The passivation layer film exposed is removed, passivation layer is formed；
It is described that public electrode film is made on the passivation layer specifically: to make common electrical on the organic resin layer
Very thin films.
Any of the above-described scheme is preferably, it is described pass through a patterning processes by the public electrode film formation include
After the figure of public electrode, array substrate is made annealing treatment, the annealing temperature is 200 DEG C -250 DEG C.
Any of the above-described scheme is preferably, described to pass through a patterning processes, by the metal oxide thin films
Formed comprising active layer and positioned at pixel electrode area, source electrode region, drain regions figure, by the gate insulator
Film forms the figure comprising gate insulating layer, and the grid film is formed the figure comprising grid, comprising the following steps:
Photoresist is coated on the grid film；Single exposure, development are carried out to photoresist by intermediate tone mask plate,
Retain photoresist region so that photoresist forms half, all risk insurance stays photoresist region and remove photoresist region entirely, described half retains
Photoresist region includes source electrode region, drain regions and pixel electrode area, and it includes grid that all risk insurance, which stays photoresist region,
Polar region domain, the region in addition to half retains photoresist region, all risk insurance stays photoresist region are full removal photoresist region；
It is thin to etch away the corresponding grid film in full removal photoresist region, grid insulating film and metal oxide semiconductor
Film；
By first time cineration technics, removal half retains the photoresist in photoresist region, and removes all risk insurance and stay photoresist area
The part photoresist in domain；
It etches away described half and retains the corresponding grid film in photoresist region and grid insulating film, so as to by the grid
Film forms the figure comprising grid, forms the figure comprising gate insulating layer by the grid insulating film；
By photoresist stripping process, the photoresist that all risk insurance stays photoresist region is removed.
Any of the above-described scheme is preferably, and the metal oxide thin films are IGZO (Indium Gallium
Zinc Oxide, indium gallium zinc oxide) film.
Any of the above-described scheme is preferably, and the material of the interlayer medium film includes SiNx.
A kind of thin film transistor (TFT), comprising:
Substrate；
The active layer of same layer setting, source electrode, drain electrode on the substrate；
Gate insulating layer on the active layer；
Grid on the gate insulating layer；
The active layer, source electrode, drain electrode, gate insulating layer and grid are formed by a patterning processes, the source
Electrode is connect by the active layer with the drain electrode.
A kind of production method of thin film transistor (TFT), comprising the following steps:
Production metal oxide thin films, grid insulating film, grid film are stacked gradually on substrate；
By a patterning processes, the metal oxide thin films are formed comprising active layer and are located at source electricity
Polar region domain, drain regions figure, by the grid insulating film formed include gate insulating layer figure, by the grid
Film forms the figure comprising grid；The source electrode is connect by the active layer with the drain electrode；
Conductor is carried out positioned at the figure of source electrode region and drain regions by described, forms source electrode and drain electrode.
A kind of display device comprising array substrate described in any of the above-described scheme.
Array substrate provided in an embodiment of the present invention, active layer, source electrode, drain electrode, pixel electrode are arranged in same layer,
Gate insulating layer is located on active layer, and grid is located on gate insulating layer, simplifies the structure of the array substrate of the prior art, side
Active layer, source electrode, drain electrode, pixel electrode, gate insulating layer and grid formed by a patterning processes, and it is active
Layer, source electrode, drain electrode, pixel electrode, gate insulating layer and grid are formed by a patterning processes, reduce array substrate
Masking process, shorten the manufacturing time of array substrate, improve the manufacture efficiency of array substrate, reduce array substrate
Production cost.
Detailed description of the invention
Fig. 1 is the schematic cross-section of the array substrate in one embodiment of the invention.
Fig. 2 is the schematic cross-section of the array substrate in another embodiment of the present invention.
Fig. 3 is the schematic cross-section of the array substrate in another embodiment of the present invention.
Fig. 4 is the schematic cross-section of the array substrate in another embodiment of the present invention.
Fig. 5 is that production metal oxide thin films, grid are stacked gradually on substrate in one embodiment of the invention
Schematic cross-section after insulation film, grid film.
Fig. 6 is in one embodiment of the invention by a patterning processes, formed pixel electrode area, source electrode region,
The schematic cross-section after mask lithography glue is coated in the graphic procedure of drain regions, gate insulating layer and grid.
Fig. 7 is in one embodiment of the invention by a patterning processes, formed pixel electrode area, source electrode region,
In the graphic procedure of drain regions, gate insulating layer and grid, etch away the corresponding grid film in full removal photoresist region,
Schematic cross-section after grid insulating film and metal oxide thin films.
Fig. 8 is in one embodiment of the invention by a patterning processes, formed pixel electrode area, source electrode region,
In the graphic procedure of drain regions, gate insulating layer and grid, by first time cineration technics, removal half retains photoresist area
The photoresist in domain, and remove all risk insurance and stay the schematic cross-section after the part photoresist in photoresist region.
Fig. 9-1 is to form pixel electrode area, source electrode area by a patterning processes in one embodiment of the invention
Domain, drain regions, gate insulating layer and grid graphic procedure in, it is thin to etch away the corresponding grid in half reservation photoresist region
Schematic cross-section after film and grid insulating film.
Fig. 9-2 is to form pixel electrode area, source electrode area by a patterning processes in one embodiment of the invention
Domain, drain regions, gate insulating layer and grid graphic procedure in, it is thin to etch away the corresponding grid in half reservation photoresist region
After film and grid insulating film, the schematic cross-section of conductor is carried out.
Figure 10 is the production method flow diagram of the array substrate in one embodiment of the invention.
Figure 11 is the production method part flow diagram of the array substrate in one embodiment of the invention.
Figure 12 is the production method part flow diagram of the array substrate in one embodiment of the invention.
Figure 13 is that will be passivated layer film in the production method of the array substrate in one embodiment of the invention and form passivation layer
Flow diagram.
Figure 14 is the production method part flow diagram of the array substrate in one embodiment of the invention.
Appended drawing reference: 1- substrate, 2- active layer, 3- source electrode, 4- drain electrode, 5- pixel electrode, 6- gate insulating layer, 7-
Grid, 8- inter-level dielectric, 9- via hole, 10- data line, 11- passivation layer, 12- organic resin layer, 13- public electrode, 14- are partly led
Body metal-oxide film, 15- grid insulating film, 16- grid film, 17- photoresist, 18- all risk insurance stay photoresist region,
19- half retains photoresist region, and 20- removes photoresist region entirely.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
It is well known that thin film transistor (TFT) (TFT) includes: grid, source electrode and drain electrode.Generally, the source electrode of TFT
It can be considered as with drain electrode equivalent；It is i.e. electric except any one in the two poles of the earth in TFT in addition to grid, can be known as to source
Pole, another pole are known as drain electrode.Specifically, in embodiments of the present invention in order to avoid obscuring caused by appellation, by TFT and number
It is known as source electrode according to one pole of line electric connection, the pole that TFT and pixel electrode are electrically connected is known as drain electrode.Certainly, if
TFT and one pole of data line electrical connection are known as drain electrode, the pole that TFT and pixel electrode are electrically connected is known as source electrode,
It is also possible.
A kind of array substrate is provided in one embodiment of the invention, as shown in Figure 1, comprising: substrate 1；Same layer is set on substrate 1
Active layer 2, source electrode 3, drain electrode 4, the pixel electrode 5 set；Gate insulating layer 6 on the active layer；Positioned at described
Grid 7 on gate insulating layer；The active layer 2, source electrode 3, drain electrode 4, pixel electrode 5, gate insulating layer 6 and grid 7
It is formed by a patterning processes, the source electrode 3 is connect by the active layer 2 with the drain electrode 4.
In the embodiment of the present invention, as shown in Figure 1, source electrode 3 is connect by active layer 2 with drain electrode 4, drain electrode 4 and picture
Plain electrode 5 connects.These are the slightly changes that the spirit based on the embodiment of the present invention carries out, and should all fall into protection model of the invention
It encloses.
In array substrate provided in an embodiment of the present invention, active layer, source electrode, drain electrode, pixel electrode are arranged same
Layer, gate insulating layer are located on active layer, and grid is located on gate insulating layer, simplifies the knot of the array substrate of the prior art
Structure facilitates active layer, source electrode, drain electrode, pixel electrode, gate insulating layer and grid and is formed by a patterning processes,
And active layer, source electrode, drain electrode, pixel electrode, gate insulating layer and grid are formed by a patterning processes, reduce battle array
The masking process number of column substrate, shortens the Production Time of array substrate, improves the producing efficiency of array substrate, reduces
The production cost of array substrate.
It should be noted that generally also needing setting data line for array substrate.For the present embodiment preferably
Ground, array substrate as shown in Figure 2 further include: the inter-level dielectric on pixel electrode 5, source electrode 3, drain electrode 4, grid 7
(Inter Level Dielectric, abbreviation ILD) 8, inter-level dielectric 8 include the via hole 9 of the corresponding source electrode 3；Positioned at layer
Between data line 10 on medium 8, data line 10 connect by via hole 9 with source electrode 3.Data line takes this method setting can be square
Just (such as conductorization is handled) is further processed in the source electrode of pre-production, drain electrode, pixel electrode.Practice process
In, data line and source electrode can also be subjected to same layer setting.The material of data line can for aluminium, copper or other electric conductivities compared with
Good metal material.
Inter-level dielectric 8 is a kind of insulation system, can make pixel electrode 5, source electrode 3, drain electrode 4, grid 7 and other portions
Divide and insulate.The thickness of inter-level dielectric 8 can beThe specific material of inter-level dielectric 8 can be
SiNx, SiON or SiO2Single thin film or silicon nitride (SiNx) and silica (SiO2) laminated film
(being the nitride film of silicon and the laminated film that silica membrane is constituted) or silica and silicon oxynitride (SiON)
Laminated film (being the laminated film that silica membrane and silicon oxynitride film are constituted) or silica, nitrogen oxidation
The laminated film of the nitride of silicon and silicon (is that the nitride film of silica membrane, silicon oxynitride film and silicon is constituted
Laminated film).
The cross section of via hole 9 can be V-type, T-type or U-shaped structure or other structures with phase same-action.It is shown in Fig. 2
It is V-structure.
In order to protect source electrode, drain electrode, pixel electrode, grid, data line etc., them is avoided to be made by oxidation corrosion
With array substrate as shown in Figure 3,4 further include: the passivation layer 11 on data line 10 and inter-level dielectric 8；Positioned at passivation layer
Public electrode 13 on 11.
Passivation layer 11 can be silicon dioxide layer film or the laminated film of silica and silicon oxynitride, passivation
The thickness of layer can beThe thickness of public electrode 13 can be
In another preferred embodiment, the array substrate further include: the organic resin layer 12 on passivation layer 11, it is public
Electrode 13 is located on organic resin layer 12, as shown in Figure 4.The setting of organic resin layer can reduce public electrode and data line
Between parasitic capacitance can also make the surface plate of array substrate to reduce the power consumption of array substrate.
In another embodiment of the present invention, the production method of array substrate as shown in Figure 10, comprising the following steps:
S101, that production metal oxide thin films 14, grid insulating film 15, grid are stacked gradually on substrate is thin
Film 16.
As shown in Figure 5 stacks gradually production metal oxide thin films, grid insulating film, grid on substrate
Schematic cross-section after film.Metal oxide thin films are made on substrate, and sputtering method deposition film forming can be used,
The material of metal-oxide film can be IGZO (Indium Gallium ZincOxide, indium gallium zinc oxide) or ITZO
(indium tin zinc oxide), the thickness of metal oxide thin films is generally
It when making grid insulating film, is made on the substrate for be formed with metal-oxide film.Production method can
Think PECVD (plasma enhanced chemical vapor deposition method), the overall thickness of grid insulating film layer can beGrid insulating film can be the silica membrane of single layer, be also possible to the nitride and dioxy of silicon
The laminated film (being the nitride film of silicon and the laminated film that silica membrane is constituted) of SiClx or the nitridation of silicon
The laminated film of object, silicon oxynitride and silica.If grid insulating film layer be silicon nitride and silica it is compound
The laminated film of the nitride of film or silicon, silicon oxynitride and silica, it is preferred that by silica membrane with partly lead
The contact of body metal-oxide film, the nitride film or silicon oxynitride film that silicon should be avoided are directly and metal oxide semiconductor
Film contacts, this is because when the nitride film or silicon oxynitride film of silicon and metal oxide thin films contact, especially
When it is with IGZO film contacts, the nitride film of silicon or hydrogen (H) meeting in silicon oxynitride film are to semi-conductive metal oxide
Object film carries out conductor, to affect the characteristic of metal oxide thin films.
It when making grid film, is made on the substrate for be formed with grid insulating film.Production method can be to splash
Deposition is penetrated, the material of grid film can be the metals such as molybdenum (Mo), aluminium (Al), with a thickness of
S102, pass through a patterning processes, metal oxide thin films 14 are formed comprising active layer and are located at
Pixel electrode area, source electrode region, drain regions figure, by the grid insulating film formed include gate insulating layer
Figure, by the grid film formed include grid figure；The source electrode passes through the active layer and the drain electrode
Connection.
It is described by a patterning processes, specifically include the techniques such as coating photoresist, exposure, development, etching.Wherein, it exposes
Light technology needs to control photoresist using mask plate in the exposure of different zones.In the entire manufacturing process of array substrate,
Usually the number of mask plate will be used as the number of patterning processes；That is, carrying out a patterning processes is to use one
Secondary mask plate completes composition.Such as Fig. 9-1, this method forms active layer, pixel electrode area, source by a patterning processes
Electrode zone, drain regions, gate insulating layer and gate patterns.
S103, the figure positioned at pixel electrode area, source electrode region and drain regions is subjected to conductor, shape
Pixel electrode, source electrode and drain electrode.
It is by conductor, pixel electrode area, source electrode region, the metal oxide of drain regions is thin such as Fig. 9-2
Film forms respectively pixel electrode, source electrode, drain electrode.Arrow in Fig. 9-2 indicates conductor, and conductorization can reduce data
Contact resistance between line and source electrode can also make metal oxide semiconductor serve as pixel electrode, meanwhile, because only to picture
Plain electrode zone, source electrode region, the corresponding metal oxide thin films of drain regions carry out conductor, so not
Influence the characteristic of the corresponding metal oxide thin films of active layer.
In the production method of array substrate provided in an embodiment of the present invention, by stacking film forming and a patterning processes and lead
Body step, in same layer, gate insulating layer is located on active layer for active layer obtained, source electrode, drain electrode, pixel electrode,
Grid is located on gate insulating layer, and the method reduce the masking process numbers of array substrate, shortens the production of array substrate
Time improves the producing efficiency of array substrate, reduces the production cost of array substrate.
Preferably in embodiment, in the production method of array substrate as shown in figure 11, the formation pixel electrode, source electricity
After pole and drain electrode further include:
S201, production cover the interlayer medium film of the pixel electrode, source electrode, drain electrode, grid, pass through a structure
The interlayer medium film is formed the inter-level dielectric comprising via hole by figure technique, and the via hole corresponds to the source electrode.
Inter-level dielectric is a kind of insulation system, can make pixel electrode, source electrode, drain electrode, grid and other parts into
Row insulation.The thickness of inter-level dielectric can beFilm build method can be PECVD, and specific material can be
The laminated film of the nitride and silica (SiO2) of silicon or the laminated film of silica and silicon oxynitride (SiON),
Or the laminated film of the nitride of silica, silicon oxynitride and silicon.
The cross section of via hole can be V-type, T-type or U-shaped structure or other structures with phase same-action.
S202, production cover the data line film of the via hole, by a patterning processes by the data line film shape
At the figure comprising data line, the data line is connect by the via hole with the source electrode.
Preferably, the production method of array substrate as shown in figure 12, it is described to pass through a patterning processes for the number
It is formed after the figure comprising data line according to line film further include:
The passivation layer film of S301, production the covering data line and the inter-level dielectric, will by a patterning processes
The passivation layer film forms passivation layer.
Passivation layer can be silicon dioxide layer film or the laminated film of silica and silicon oxynitride, passivation layer
Thickness can beFilm build method can be PECVD.Passivation layer can protect source electrode, drain electrode,
Pixel electrode, grid, data line etc. avoid them from being acted on by oxidation corrosion.
S302, public electrode film is made on the passivation layer, it is by a patterning processes that the common electrical is very thin
Film forms the figure comprising public electrode.The thickness of public electrode can beFilm build method can be magnetic control
Sputtering method.
As shown in figure 13, it is described pass through a patterning processes by the passivation layer film formation passivation layer include:
The organic resin film of S401, the production covering passivation layer film.
S402, the organic resin by the organic resin film in passivation layer region retain, the organic resin in other regions
Removal forms organic resin layer.The setting of organic resin layer can reduce the parasitic capacitance between public electrode and data line,
To reduce the power consumption of array substrate, the surface plate of array substrate can also be made.
S403, the passivation layer film exposed is removed, forms passivation layer.
S404, the production public electrode film on the passivation layer specifically: made on the organic resin layer
Public electrode film.
The step forms passivation layer and organic resin layer by a patterning processes, and manufacture craft is easy, production cost
It is lower.
In preferred embodiment, passes through a patterning processes described and form the public electrode film comprising common electrical
After the figure of pole, array substrate is made annealing treatment, the annealing temperature is 200 DEG C -250 DEG C.Annealing be in order to
The stability of oxide array substrate is improved, while reducing the resistivity of pixel electrode；The temperature of annealing should not be greater than
The rear baking temperature of machine resin layer, avoids impacting organic resin layer.
It is described to pass through a patterning processes as shown in Fig. 1,6,7,8,9-1,9-2,14 in another embodiment of the present invention, it will
The metal oxide thin films form comprising active layer and are located at pixel electrode area, source electrode region, drain electrode
The grid insulating film is formed the figure comprising gate insulating layer by the figure in region, includes by grid film formation
The figure of grid, comprising the following steps:
S501, photoresist 17 is coated on the grid film；Photoresist 17 is carried out once by intermediate tone mask plate
Exposure, development, so that photoresist forms half reservation photoresist region 19, all risk insurance stays photoresist region 18 and full removal photoresist area
Domain 20, half, which retains photoresist region 19, includes source electrode region, drain regions and pixel electrode area, and all risk insurance stays photoresist area
Domain 18 includes area of grid, and the region in addition to half retains photoresist region, all risk insurance stays photoresist region is full removal photoresist
Region 20.
S502, the full removal corresponding grid film in photoresist region 20, grid insulating film and semiconductor alloy are etched away
Sull.
Etching away the full removal corresponding grid film in photoresist region 20 can be used the gaseous mixture or Cl2 of SF6 and O2
Dry etching is carried out with the gaseous mixture of O2, etching away the full removal corresponding grid insulating film in photoresist region 20 can be used
The gaseous mixture of CF4 and O2 carries out dry etching, and it is thin to etch away the full removal corresponding metal oxide semiconductor in photoresist region 20
Film can use wet etching.
S503, pass through first time cineration technics, removal half retains the photoresist in photoresist region 19, and removes all risk insurance and stay light
The part photoresist in photoresist region 18.
S504, the corresponding grid film in half reservation photoresist region 19 and grid insulating film are etched away, so as to by described
Grid film forms the figure comprising grid, forms the figure comprising gate insulating layer by the grid insulating film.
Etch away the corresponding grid film in half reservation photoresist region 19 also can be used SF6 and O2 gaseous mixture or
The gaseous mixture of Cl2 and O2 carries out dry etching, and etching away the corresponding grid insulating film in half reservation photoresist region 19 can also be with
Dry etching is carried out using the gaseous mixture of CF4 and O2.
S505, pass through photoresist stripping process, removal all risk insurance stays the photoresist in photoresist region 18.
This method passes through a patterning processes, is respectively formed active layer on the substrate and is located at pixel electrode area
Domain, source electrode region, drain regions figure, also form gate insulating layer and grid, it is easy to operate, it is convenient and efficient,
Reduce production cost.
It may further be preferable that the metal oxide thin films are IGZO (Indium Gallium Zinc
Oxide, indium gallium zinc oxide) film.Sputtering method film forming can be used in the IGZO film, when the sputtering method forms a film,
It is passed through Ar and O2, the O2The percent by volume of the total gas of Zhan is 15%-30%.
Source electrode, drain electrode are formed by IGZO film layer, and instead of the opaque metallic film of the prior art, this method is straight
It connects and increases the transmitance of array substrate, and then improve the integral finish rate of display.IGZO is that one kind contains indium, gallium and zinc
Amorphous oxides, carrier mobility is 20~30 times of amorphous silicon, and the active layer formed by IGZO film can mention significantly
High TFT improves the response speed of pixel to the charge-discharge velocity of pixel electrode, realizes faster refresh rate, while ringing faster
The line scanning rate of pixel should also be substantially increased；Because carrier mobility is higher, the power consumption of display, and phase are reduced
It can reduce with the TFT area that electric current flows through, wiring can also subtract carefully, and the area of lightproof part reduces, and can obtain very
Big aperture opening ratio.
In addition, IGZO film carry out conductor when, dry etching equipment can be used, using SF6 and He combination gas or
It only uses He and (Plasma) processing is ionized to IGZO film, ionization duration is generally 20s-60s；Or use CF4
Ionization processing is carried out to IGZO film in dry etching equipment with the combination gas of O2, duration can be 20s-60s.Conductor energy
The carrier mobility for enough improving IGZO film, further decreases power consumption.
Preferably, the material of the interlayer medium film is the nitride (SiNx) of silicon.The nitride film of silicon is by silicon
Alkane (SiH4) and ammonia (NH3) generate, and contain hydrogen (H) in the nitride (SiNx) of silicon.Hydrogen (H) passes through diffusion, can be with
Oxygen (O) in IGZO film layer corresponding with pixel electrode figure, source electrode figure and drain electrode patterns combines, to make pixel
Electrode zone, source electrode region and the corresponding IGZO film layer of drain regions carry out conductor.When making interlayer medium film,
It uses the nitride (SiNx) of silicon that the IGZO film exposed is made to carry out conductor, eliminates individually thin to the IGZO exposed
Film carries out the step of conductor, to improve production efficiency, reduces production cost.
A kind of thin film transistor (TFT) is provided in another embodiment of the present invention, comprising: substrate；Same layer is arranged on the substrate
Active layer, source electrode, drain electrode；Gate insulating layer on the active layer；Grid on the gate insulating layer；
The active layer, source electrode, drain electrode, gate insulating layer and grid are formed by a patterning processes, and the source electrode passes through
The active layer is connect with the drain electrode.
In thin film transistor (TFT) provided in an embodiment of the present invention, active layer therein, source electrode, drain electrode, pixel electrode are set
It sets in same layer, gate insulating layer is located on active layer, and grid is located on gate insulating layer, simplifies the array base of the prior art
The structure of plate facilitates active layer, source electrode, drain electrode, pixel electrode, gate insulating layer and grid and passes through a patterning processes
It is formed, and active layer, source electrode, drain electrode, pixel electrode, gate insulating layer and grid are formed by a patterning processes, are subtracted
The number of mask in thin film transistor (TFT) manufacture craft is lacked, has shortened the Production Time of thin film transistor (TFT), improve film crystal
The producing efficiency of pipe reduces the production cost of thin film transistor (TFT).
A kind of production method of thin film transistor (TFT) is provided in another embodiment of the present invention, comprising the following steps:
Production metal oxide thin films, grid insulating film, grid film are stacked gradually on substrate；
By a patterning processes, the metal oxide thin films are formed comprising active layer and are located at source electricity
Polar region domain, drain regions figure, by the grid insulating film formed include gate insulating layer figure, by the grid
Film forms the figure comprising grid；The source electrode is connect by the active layer with the drain electrode；
Conductor is carried out positioned at the figure of source electrode region and drain regions by described, forms source electrode and drain electrode.
In the production method of thin film transistor (TFT) provided in an embodiment of the present invention, pass through stacking film forming and a patterning processes
And conductor step, active layer obtained, source electrode, drain electrode are in same layer, and gate insulating layer is located on active layer, grid position
In on gate insulating layer, the method reduce the number of mask in thin film transistor (TFT) manufacture craft, shorten thin film transistor (TFT)
Production Time improves the producing efficiency of thin film transistor (TFT), reduces the production cost of thin film transistor (TFT).
A kind of display device comprising array substrate described in any of the above-described scheme is provided in another embodiment of the present invention.
In display device provided in an embodiment of the present invention, active layer therein, source electrode, drain electrode, pixel electrode setting
In same layer, gate insulating layer is located on active layer, and grid is located on gate insulating layer, simplifies the display device of the prior art
Structure, facilitate active layer, source electrode, drain electrode, pixel electrode, gate insulating layer and grid by a patterning processes shape
At, and active layer, source electrode, drain electrode, pixel electrode, gate insulating layer and grid are formed by a patterning processes, are reduced
Number of mask in display device manufacture craft, shortens the Production Time of display device, improves the production of display device
Efficiency reduces the production cost of display device.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be subject to protection scope described in claim.
Claims (7)
1. a kind of production method of array substrate, which comprises the following steps:
Production metal oxide thin films, grid insulating film, grid film are stacked gradually on substrate；
By a patterning processes, the metal oxide thin films are formed comprising active layer and are located at pixel electrode
Region, source electrode region, drain regions figure, by the grid insulating film formed include gate insulating layer figure,
The grid film is formed into the figure comprising grid；The source electrode is connect by the active layer with the drain electrode；
The figure positioned at pixel electrode area, source electrode region and drain regions is subjected to conductor, forms pixel electricity
Pole, source electrode and drain electrode；
After the formation pixel electrode, source electrode and drain electrode further include:
Production covers the interlayer medium film of the pixel electrode, source electrode, drain electrode, grid, will by a patterning processes
The interlayer medium film forms the inter-level dielectric comprising via hole, and the via hole corresponds to the source electrode；
Production covers the data line film of the via hole, and being formed the data line film by a patterning processes includes data
The figure of line, the data line are connect by the via hole with the source electrode；
Wherein, described to pass through a patterning processes, it includes active layer and position that the metal oxide thin films, which are formed,
In pixel electrode area, source electrode region, drain regions figure, by the grid insulating film formed include gate insulator
The grid film is formed the figure comprising grid by the figure of layer, comprising the following steps:
Photoresist is coated on the grid film；Single exposure, development are carried out to photoresist by intermediate tone mask plate, so that
Photoresist forms half and retains photoresist region, all risk insurance stays photoresist region and remove photoresist region entirely, and described half retains photoetching
Glue region includes source electrode region, drain regions and pixel electrode area, and it includes gate regions that all risk insurance, which stays photoresist region,
Domain, the region in addition to half retains photoresist region, all risk insurance stays photoresist region are full removal photoresist region；
Etch away the corresponding grid film in full removal photoresist region, grid insulating film and metal oxide thin films；
By first time cineration technics, removal half retains the photoresist in photoresist region, and removes all risk insurance and stay photoresist region
Part photoresist；
It etches away described half and retains the corresponding grid film in photoresist region and grid insulating film, so as to by the grid film
The figure comprising grid is formed, the figure comprising gate insulating layer is formed by the grid insulating film；
By photoresist stripping process, the photoresist that all risk insurance stays photoresist region is removed.
2. the production method of array substrate according to claim 1, which is characterized in that described to pass through a patterning processes general
The data line film is formed after the figure comprising data line further include:
The passivation layer film of production the covering data line and the inter-level dielectric, by a patterning processes by the passivation layer
Film forms passivation layer；
Public electrode film is made on the passivation layer, includes by public electrode film formation by a patterning processes
The figure of public electrode.
3. the production method of array substrate according to claim 2, which is characterized in that described to pass through a patterning processes general
The passivation layer film forms passivation layer
The organic resin film of the production covering passivation layer film；
Organic resin by the organic resin film in passivation layer region retains, and the organic resin removal in other regions is formed
Organic resin layer；
The passivation layer film exposed is removed, passivation layer is formed；
It is described that public electrode film is made on the passivation layer specifically: it is very thin that common electrical is made on the organic resin layer
Film.
4. the production method of array substrate according to claim 2, which is characterized in that pass through a patterning processes described
The public electrode film is formed after the figure comprising public electrode, array substrate is made annealing treatment, the annealing
Temperature is 200 DEG C -250 DEG C.
5. the production method of array substrate according to claim 1, which is characterized in that the metal oxide semiconductor is thin
Film is IGZO film.
6. the production method of array substrate according to claim 1, which is characterized in that the material of the interlayer medium film
Include SiNx.
7. a kind of production method of thin film transistor (TFT), which comprises the following steps:
Production metal oxide thin films, grid insulating film, grid film are stacked gradually on substrate；
By a patterning processes, the metal oxide thin films are formed comprising active layer and are located at source electrode area
Domain, drain regions figure, by the grid insulating film formed include gate insulating layer figure, by the grid film
Form the figure comprising grid；The source electrode is connect by the active layer with the drain electrode；
Conductor is carried out positioned at the figure of source electrode region and drain regions by described, forms source electrode and drain electrode；
Wherein, described to pass through a patterning processes, it includes active layer and position that the metal oxide thin films, which are formed,
In source electrode region, the figure of drain regions, the grid insulating film is formed into the figure comprising gate insulating layer, by institute
It states grid film and forms the figure comprising grid, comprising the following steps:
Photoresist is coated on the grid film；Single exposure, development are carried out to photoresist by intermediate tone mask plate, so that
Photoresist forms half and retains photoresist region, all risk insurance stays photoresist region and remove photoresist region entirely, and described half retains photoetching
Glue region includes source electrode region and drain regions, and it includes area of grid that all risk insurance, which stays photoresist region, except half reservation light
It is full removal photoresist region that the region except photoresist region is stayed in photoresist region, all risk insurance；
Etch away the corresponding grid film in full removal photoresist region, grid insulating film and metal oxide thin films；
By first time cineration technics, removal half retains the photoresist in photoresist region, and removes all risk insurance and stay photoresist region
Part photoresist；
It etches away described half and retains the corresponding grid film in photoresist region and grid insulating film, so as to by the grid film
The figure comprising grid is formed, the figure comprising gate insulating layer is formed by the grid insulating film；
By photoresist stripping process, the photoresist that all risk insurance stays photoresist region is removed.
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| CN105070765B (en) * | 2015-09-09 | 2018-11-16 | 京东方科技集团股份有限公司 | Thin film transistor (TFT), array substrate, display device and manufacturing method |
| CN105762195B (en) * | 2016-03-04 | 2019-07-26 | 武汉华星光电技术有限公司 | Metal oxide thin-film transistor and preparation method thereof |
| CN108346620A (en) * | 2017-01-23 | 2018-07-31 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, display device |
| CN107275342B (en) | 2017-06-12 | 2019-11-08 | 京东方科技集团股份有限公司 | A kind of display device and preparation method thereof |
| CN107359126B (en) | 2017-07-11 | 2020-03-10 | 京东方科技集团股份有限公司 | Thin film transistor, preparation method thereof, array substrate and display panel |
| CN107910351B (en) * | 2017-11-14 | 2020-06-05 | 深圳市华星光电技术有限公司 | Manufacturing method of TFT substrate |
| CN108447888B (en) * | 2018-03-15 | 2020-12-25 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display device |
| CN109860305B (en) * | 2018-12-25 | 2020-11-06 | 合肥鑫晟光电科技有限公司 | Thin film transistor, manufacturing method thereof, display substrate and display device |
| CN109755261A (en) * | 2018-12-26 | 2019-05-14 | 深圳市华星光电半导体显示技术有限公司 | A kind of array substrate and preparation method thereof |
| CN110780492A (en) * | 2019-10-28 | 2020-02-11 | 深圳市华星光电半导体显示技术有限公司 | Display panel, preparation method thereof and display device |
| CN111180471A (en) * | 2020-03-02 | 2020-05-19 | 南京中电熊猫平板显示科技有限公司 | Array substrate and manufacturing method thereof |
| CN113728442A (en) * | 2020-03-13 | 2021-11-30 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof |
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