CN113728442A - Array substrate and manufacturing method thereof - Google Patents
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- CN113728442A CN113728442A CN202080000253.2A CN202080000253A CN113728442A CN 113728442 A CN113728442 A CN 113728442A CN 202080000253 A CN202080000253 A CN 202080000253A CN 113728442 A CN113728442 A CN 113728442A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
An array substrate and a manufacturing method thereof comprise: a base substrate (101); the transistor (102) is positioned on the substrate base plate (101), the transistor (102) comprises an active layer (1021), and the active layer (1021) is made of a semiconductor material; the pixel electrode (103) is arranged on the same layer as the active layer (1021), the orthographic projection of the pixel electrode (103) on the substrate (101) and the orthographic projection of the active layer (1021) do not overlap, and the material of the pixel electrode (103) is a conductive semiconductor material; a first inorganic passivation layer (104) on a side of the pixel electrode (103) facing away from the substrate (101); a second inorganic passivation layer (105) on a side of the first inorganic passivation layer (104) facing away from the substrate base plate (101), at least a partial region of the second inorganic passivation layer (105) being in direct contact with the first inorganic passivation layer (104).
Description
The present disclosure relates to the field of display technologies, and in particular, to an array substrate and a method for manufacturing the same.
Thin Film Transistor Liquid Crystal displays (TFT-LCDs) have the characteristics of small size, low power consumption, no radiation, and the like, and occupy a leading position in the current flat panel Display market. The main structure of the TFT-LCD comprises an array substrate and a color film substrate which are arranged in a box-to-box mode, and a liquid crystal molecular layer filled between the array substrate and the color film substrate. In the related art, the TFT mainly has two types, that is, an oxide semiconductor TFT (simply referred to as an oxide TFT) and an amorphous silicon TFT, depending on a channel material. The oxide TFT, which uses an oxide semiconductor material as an active layer, has good uniformity, is particularly suitable for the requirement of large-area display, and has gradually become a mainstream technology of a large-size, high-image-quality, low-power consumption flat panel display product.
Disclosure of Invention
The embodiment of the present disclosure provides an array substrate, including:
a substrate base plate;
the transistor is positioned on the substrate and comprises an active layer, and the active layer is made of semiconductor materials;
the pixel electrode is arranged on the same layer as the active layer, the orthographic projection of the pixel electrode on the substrate and the orthographic projection of the active layer are not overlapped, and the material of the pixel electrode is the semiconductor material which is made of a conductor;
the first inorganic passivation layer is positioned on one side of the pixel electrode, which is far away from the substrate;
a second inorganic passivation layer on a side of the first inorganic passivation layer facing away from the substrate base plate, at least a partial region of the second inorganic passivation layer being in direct contact with the first inorganic passivation layer.
Optionally, in the array substrate provided in this disclosure, the first inorganic passivation layer has a hollow area, and the second inorganic passivation layer covers the pixel electrode and is in direct contact with the pixel electrode at the hollow area.
Optionally, in the array substrate provided in the embodiment of the present disclosure, the transistor further includes: the grid electrode is positioned between the active layer and the substrate base plate, and the first pole and the second pole are positioned on one side, away from the substrate base plate, of the active layer;
the first inorganic passivation layer is positioned between the first pole and the second pole layer and the active layer;
the orthographic projection of the grid electrode on the substrate base plate is positioned in the orthographic projection of the active layer;
an orthographic projection of the first pole on the substrate overlaps with an orthographic projection portion of the first inorganic passivation layer, the first pole comprising a portion in direct contact with the first inorganic passivation layer and a portion in direct contact with the active layer;
an orthographic projection of the second pole on the substrate overlaps with an orthographic projection portion of the first inorganic passivation layer, the second pole including a portion in direct contact with the first inorganic passivation layer, a portion in direct contact with the active layer, and a portion in direct contact with the pixel electrode.
Optionally, in the above array substrate provided by the embodiment of the present disclosure, the gate is one, an orthographic projection of the gate on the substrate coincides with a region of the first inorganic passivation layer directly contacting the first pole, the second pole and the active layer, and a boundary of the gate and a boundary of a central region of the first pole or the second pole adjacent to the active layer have a first distance therebetween;
or, there are two gate electrodes, an orthographic projection of the gate electrode on the substrate coincides with a region of the first inorganic passivation layer directly contacting the first pole and the second pole, and a second distance is formed between a boundary of the gate electrode away from the central region of the active layer and a boundary of the first pole or the second pole adjacent to the central region of the active layer;
the first distance is twice the second distance.
Optionally, in the array substrate provided in the embodiment of the present disclosure, the transistor further includes: the grid electrode is positioned between the active layer and the substrate base plate, and the first pole and the second pole are positioned on one side, away from the substrate base plate, of the active layer;
the first inorganic passivation layer is positioned between the first electrode and the second electrode layer and the second inorganic passivation layer and is connected with the first electrode, the second electrode and the active layer;
the orthographic projection of the grid electrode on the substrate covers the orthographic projection of the active layer;
the first pole is in direct contact with the active layer, and the second pole is in direct contact with the active layer and the pixel electrode.
Optionally, in the array substrate provided in the embodiment of the present disclosure, the transistor further includes: a first electrode and a second electrode between the active layer and the substrate base plate, and a gate electrode between the active layer and the first inorganic passivation layer;
the orthographic projection of the grid electrode on the substrate is superposed with the orthographic projection of the active layer;
the active layer covers the first pole and the second pole, and the bottom of the central region of the active layer is flush with the bottom of the first pole and the bottom of the second pole;
the second electrode is directly connected to the pixel electrode.
Optionally, in the array substrate provided in the embodiment of the present disclosure, the transistor further includes: a gate electrode between the active layer and the substrate base plate, and first and second poles between the active layer and the first inorganic passivation layer;
the first inorganic passivation layer covers the first pole, the second pole, the active layer and the pixel electrode;
the orthographic projection of the grid electrode on the substrate covers the orthographic projection of the active layer;
the first pole is in direct contact with the active layer, and the second pole is in direct contact with the active layer and the pixel electrode.
Optionally, in the array substrate provided in the embodiment of the present disclosure, the array substrate further includes: the strip-shaped common electrode is positioned on one side, away from the substrate base plate, of the second inorganic passivation layer, and the common voltage line is arranged on the same layer as the grid electrode of the transistor;
the orthographic projection of the strip-shaped common electrode on the substrate covers the orthographic projection of the pixel electrode, and the strip-shaped common electrode is electrically connected with the common voltage line through a through hole penetrating through each layer between the grid electrode and the strip-shaped common electrode.
Based on the same inventive concept, the embodiment of the present disclosure further provides a manufacturing method of an array substrate, where the method includes:
providing a substrate base plate;
forming a transistor, a first inorganic passivation layer and a second inorganic passivation layer on the substrate base plate;
wherein the step of forming a transistor comprises:
forming a semiconductor material layer on the substrate base plate, wherein the semiconductor material layer comprises a first part and a second part, the first part is used for forming an active layer, the second part is used for forming a pixel electrode, the orthographic projection of the first part on the substrate base plate is mutually overlapped with the active layer, and the orthographic projection of the second part on the substrate base plate is not overlapped with the active layer;
conducting the second portion to form the pixel electrode;
at least a partial region of the second inorganic passivation layer is in direct contact with the first inorganic passivation layer.
Optionally, in the above manufacturing method provided by the embodiment of the present disclosure, after forming a semiconductor material layer on the substrate, and before the conducting the second portion to form the pixel electrode, the method further includes:
and forming a photoresist layer covering the active layer, and carrying out preliminary conductor treatment on the second part contained in the semiconductor material layer by taking the photoresist layer as a mask.
Optionally, in the above manufacturing method provided in an embodiment of the present disclosure, the forming the first inorganic passivation layer specifically includes:
forming the first inorganic passivation layer having a hollowed-out region at a position of the second portion.
Optionally, in the above manufacturing method provided in this disclosure, the forming the pixel electrode by conducting the second portion specifically includes:
and conducting the second part by using the first inorganic passivation layer with the hollow area as a mask plate to form the pixel electrode.
Fig. 1, fig. 2, fig. 3, fig. 4 and fig. 5 are respectively schematic structural diagrams of an array substrate according to an embodiment of the present disclosure;
fig. 6, fig. 7, fig. 8, fig. 9 and fig. 10 are schematic structural diagrams in the manufacturing process of the array substrate shown in fig. 1, respectively;
fig. 11, 12, 13, 14 and 15 are schematic structural diagrams in the manufacturing process of the array substrate shown in fig. 2, respectively;
fig. 16, 17 and 18 are schematic structural diagrams in the manufacturing process of the array substrate shown in fig. 3, respectively;
fig. 19, fig. 20, fig. 21, fig. 22, fig. 23 and fig. 24 are schematic structural diagrams in the manufacturing process of the array substrate shown in fig. 4, respectively;
fig. 25 and 26 are schematic structural diagrams in the manufacturing process of the array substrate shown in fig. 5, respectively.
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. The thicknesses and shapes of the various film layers in the drawings are not to be considered true proportions, but are merely illustrative of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in the description and claims does not indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. "inner", "outer", "upper", "lower", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
In the related art, the preparation of the array substrate of the oxide technology is generally realized by using an 8-mask process (8mask) or a process with more masks. Specifically, an 8mask process is used to form a gate electrode, an active layer, source and drain electrodes, a first inorganic passivation layer, a resin layer, a second inorganic passivation layer, a pixel electrode, and a common electrode, respectively. Therefore, in the related art, the oxide display product needs a large number of mask plates, and the production cost is high. In addition, crosslinking reaction products, solvents, water, and the like are generated in the form of Outgas during the heat curing of the resin layer, which affects the transistor stability.
In view of the above problems in the related art, embodiments of the present disclosure provide an array substrate, as shown in fig. 1 to 5, including:
a base substrate 101;
a transistor 102 located on the substrate 101, wherein the transistor 102 includes an active layer 1021, and the active layer 1021 is made of a semiconductor material;
a pixel electrode 103 disposed on the same layer as the active layer 1021, wherein an orthogonal projection of the pixel electrode 103 on the substrate 101 and an orthogonal projection of the active layer 1021 do not overlap each other, and a material of the pixel electrode 103 is a conductive semiconductor material;
a first inorganic passivation layer 104 on a side of the pixel electrode 103 facing away from the substrate base 101;
a second inorganic passivation layer 105 on a side of the first inorganic passivation layer 104 facing away from the substrate base plate 101, at least a partial region of the second inorganic passivation layer 105 being in direct contact with the first inorganic passivation layer 104.
In the array substrate provided by the embodiment of the present disclosure, the thicknesses of the first inorganic passivation layer 104 and the second inorganic passivation layer 105 may be adjusted according to the requirement of an actual product on the stability of the transistor 102, so that the first inorganic passivation layer 104 and the second inorganic passivation layer 105 have the functions of water blocking, hydrogen blocking and planarization of the resin layer in the related art, and thus, a resin layer is not required to be disposed, the output of a cross-linking reaction product, a solvent, water and the like of the resin layer in a heating and curing process in an Outgas form is avoided, and the number of mask plates is reduced. In addition, in the present disclosure, the same semiconductor material layer is used, a first portion for forming the active layer 1021 and a second portion for forming the pixel electrode 103 are formed through a single patterning process, and then the second portion of the semiconductor material layer is subjected to a conductor, so that the corresponding semiconductor material layer can be used as the pixel electrode 103. Due to the arrangement, a film layer of the pixel electrode 103 is prevented from being independently arranged, the raw material cost is saved, and the light and thin design of the product is realized. In some embodiments, a mask for fabricating the pixel electrode 103 is also saved.
Optionally, in the array substrate provided in the embodiment of the present disclosure, the material of the first inorganic passivation layer 104 may be silicon oxide having a hydrogen blocking function, and the problem of the related art that the channel region included in the active layer 1021 is made conductive due to the first inorganic passivation layer 104 made of silicon nitride can be effectively avoided by using the first inorganic passivation layer 104 made of silicon oxide. The second inorganic passivation layer 105 may be silicon nitride with a water blocking function, so as to prevent the channel region of the active layer 1021 from being eroded by external water vapor. In addition, the active layer 1021 may be formed of a metal oxide, which may alternatively be, but not limited to, Indium Gallium Zinc Oxide (IGZO). The active layer 1021 of IGZO material has a lower off-state current, which is beneficial to reducing noise.
Optionally, in the array substrate provided in the embodiment of the present disclosure, as shown in fig. 1 to 4, the first inorganic passivation layer 104 has a hollow area, and the second inorganic passivation layer 105 covers the pixel electrode 103 and is in direct contact with the pixel electrode 103 at the hollow area.
Specifically, by providing a hollow-out region in the first inorganic passivation layer 104, a semiconductor material layer in the hollow-out region is conducted with a conductive treatment by ions (Plasma), so as to obtain the pixel electrode 103. Moreover, in the case that the second inorganic passivation layer 105 is made of a silicon nitride material, since the second inorganic passivation layer 105 directly contacts the semiconductor material layer in the hollow area, hydrogen generated in the silicon nitride annealing process easily enters the semiconductor material layer in the hollow area, which is equivalent to performing a conductor processing again, thereby further improving the conductive property of the pixel electrode 103.
Optionally, in the array substrate provided in the embodiment of the present disclosure, as shown in fig. 1 and fig. 2, the transistor 102 further includes: a first pole 1022 and a second pole 1023 on a side of the active layer 1021 facing away from the substrate base 101, and a gate 1024 between the active layer 1021 and the substrate base 101;
the first inorganic passivation layer 104 is located between the layers of the first and second poles 1022 and 1023 and the active layer 1021;
the orthographic projection of the gate 1024 on the substrate base 101 is positioned in the orthographic projection of the active layer 1021;
an orthographic projection of the first pole 1022 on the substrate base plate 101 overlaps with an orthographic projection portion of the first inorganic passivation layer 104, the first pole 1022 including a portion in direct contact with the first inorganic passivation layer 104 and a portion in direct contact with the active layer 1021;
an orthogonal projection of the second pole 1023 on the substrate base 101 overlaps an orthogonal projection portion of the first inorganic passivation layer 104, and the second pole 1023 includes a portion directly contacting the first inorganic passivation layer 104, a portion directly contacting the active layer 1021, and a portion directly contacting the pixel electrode 103.
In the array substrate shown in fig. 1 and 2, the first inorganic passivation layer 104 may serve as an etch stop layer to prevent damage to the active layer 1021 during etching to form the first and second poles 1022 and 1023. In addition, the first inorganic passivation layer 104 with the hollow area can be used as a mask plate, so that only the semiconductor material layer in the hollow area can be subjected to conductor processing, the conductivity of the pixel electrode 103 is realized, the problem of contact resistance between the pixel electrode 103 and the second pole 1023 is solved, good electrical connection between the pixel electrode 103 and the second pole 1023 is ensured, and meanwhile, the mask plate for independently manufacturing the pixel electrode 103 in the related technology is saved.
Specifically, in the present disclosure, the first pole 1022 and the second pole 1023 of the transistor 102 are a drain and a source, respectively, and the functions thereof can be interchanged according to the type of the transistor and the input signal, and are not particularly distinguished herein. Generally, when the transistor 102 is a P-type transistor, the first pole 1022 is a source, and the second pole 1023 is a drain; when the transistor 102 is an N-type transistor, the first pole 1022 is a drain and the second pole 1023 is a source. Specifically, the first pole 1022, the second pole 1023, and the gate 1024 may be formed of molybdenum, aluminum, silver, copper, titanium, platinum, tungsten, tantalum nitride, alloys thereof, combinations thereof, or other suitable materials, which are not limited herein.
Optionally, in the array substrate provided in the embodiment of the present disclosure, as shown in fig. 1, one gate 1024 is provided, an orthographic projection of the gate 1024 on the substrate 101 coincides with an area of the first inorganic passivation layer 104 directly contacting the first pole 1022, the second pole 1023 and the active layer 1021, and a boundary of the gate 1024 is adjacent to the middle of the active layer 1021 between the first pole 1022 and the second pole 1023The boundaries of the heart region have a first distance L therebetweenB；
Alternatively, as shown in fig. 2, there are two gate electrodes 1024, an orthogonal projection of the gate electrode 1024 on the substrate 101 coincides with an area of the first inorganic passivation layer 104 directly contacting the first and second poles 1022 and 1023, and a second distance L 'is provided between a boundary of a central area of the gate electrode 1024 away from the active layer 1021 and a boundary of a central area of the first or second pole 1022 or 1023 adjacent to the active layer 1021'B；
First distance LBIs a second distance L'BTwice or approximately twice, where "approximately" means within an acceptable deviation of the specified value as determined by one of ordinary skill in the art, e.g., "approximately" can mean within one or more standard deviations, or within ± 30%, ± 20%, ± 10%, ± 5% of the stated value.
It is understood that hydrogen in the process of preparing the second inorganic passivation layer 105 may enter the active layer 1021 through the first inorganic passivation layer 104, and the first and second poles 1022 and 1023 above the first inorganic passivation layer 104 may well block the hydrogen from entering the active layer 1021, so that the active layer 1021 in the region between the first and second poles 1022 and 1023 (i.e., the central region of the active layer 1021) may be conducted, and the active layer 1021 covered by the first and second poles 1022 and 1023 is still in a semiconductor state. Specifically, as shown in FIG. 1, LAThe active layer 1021 of the region may be in a conductive state, LBThe active layer 1021 is still in a semiconductor state, i.e., the channel region is formed between two LBThe area is a symmetrical distributed twins channel. In the actual working process, the real influence on the mobility is LBCarrier concentration of the region, i.e. effective length L of the channeleffIs 2LB. Compared with the conventional technique in which the channel length is 2LBA single channel of length LBThe twins channel effectively increases the channel carrier concentration, improves the mobility of the transistor 102 and the working current Ion. L 'as shown in FIG. 2' AThe active layer 1021 of the region may be in a conductor state, L'BThe active layer 1021 in the region is still in a semiconductor state, i.e., formed of two L's by providing a dual gate'BThe area is a symmetrical distributed twins channel. During actual operation, what really affects mobility is L'BCarrier concentration of the region, i.e. effective length L of the channeleffIs 2L'B. Compared to the effective channel length of 2L shown in FIG. 1BThe twin channel of (1) can further increase the channel carrier concentration, improve the mobility of the transistor 102 and improve the working current Ion。
Optionally, in the array substrate provided in the embodiment of the present disclosure, as shown in fig. 3, the transistor 102 includes: a gate 1024 between the active layer 1021 and the substrate 101, and a first pole 1022 and a second pole 1023 on a side of the active layer 1021 facing away from the substrate 101;
the first inorganic passivation layer 104 is located between the layer where the first and second poles 1022 and 1023 are located and the second inorganic passivation layer 105, and is in direct contact with the first pole 1022, the second pole 1023, and the active layer 1021;
an orthographic projection of the gate electrode 1024 on the substrate base plate 101 covers an orthographic projection of the active layer 1021;
the first pole 1022 is in direct contact with the active layer 1021, and the second pole 1023 is in direct contact with the active layer 1021 and the pixel electrode 103.
In the array substrate with the structure shown in fig. 3, after the first inorganic passivation layer 104 covering the transistor 102 and having the hollow area at the position of the pixel electrode 103 is prepared, and before the second inorganic passivation layer 105 is prepared, the first inorganic passivation layer 104 is used as a mask, and a semiconductor material layer in the hollow area is subjected to a conductor processing through ions (Plasma), so that the conductive performance of the pixel electrode 103 is realized, and meanwhile, the mask for separately manufacturing the pixel electrode 103 in the related art is saved.
Optionally, in the array substrate provided in the embodiment of the present disclosure, as shown in fig. 4, the transistor 102 includes: a first pole 1022 and a second pole 1023 between the active layer 1021 and the substrate base plate 101, and a gate 1024 between the active layer 1021 and the first inorganic passivation layer 104;
the orthographic projection of the gate 1024 on the substrate 101 and the orthographic projection of the active layer 1021 are overlapped;
the active layer 1021 covers the first pole 1022 and the second pole 1023, and a bottom of a center area of the active layer 1021 is flush with bottoms of the first pole 1022 and the second pole 1023;
the second electrode 1023 is directly connected to the pixel electrode 103.
For the array substrate with the structure shown in fig. 4, the first inorganic passivation layer 104 having the hollow area can be used as a mask plate, so that the conductive processing of the semiconductor material layer in the hollow area is realized, and the conductive performance of the pixel electrode 103 is ensured, thereby saving the mask plate for separately manufacturing the pixel electrode 103 in the related art. Moreover, since the conductivity of the pixel electrode 103 is better, the contact resistance between the pixel electrode 103 and the second pole 1023 is smaller, which ensures good electrical connection between the pixel electrode 103 and the second pole 1023, and simultaneously saves a mask plate for separately manufacturing the pixel electrode 103 in the related art.
Optionally, in the array substrate provided in the embodiment of the present disclosure, as shown in fig. 5, the transistor 102 further includes: a gate electrode 1024 between the active layer 1021 and the substrate 101, and first and second poles 1022 and 1023 between the active layer 1021 and the first inorganic passivation layer 104;
the first inorganic passivation layer 104 covers the first and second poles 1022 and 1023, the active layer 1021, and the pixel electrode 103;
an orthographic projection of the gate electrode 1024 on the substrate base plate 101 covers an orthographic projection of the active layer 1021;
the first pole 1022 is in direct contact with the active layer 1021, and the second pole 1023 is in direct contact with the active layer 1021 and the pixel electrode 104.
As can be seen from fig. 5, the patterns of the first inorganic passivation layer 104 and the second inorganic passivation layer 105 are consistent, and therefore, in an actual manufacturing process, the first inorganic thin film layer and the second inorganic thin film layer may be sequentially deposited, and a via hole pattern penetrating through the first inorganic passivation layer 104 and the second inorganic passivation layer 105 may be formed by performing a patterning process using the same mask. Thus, a mask can be saved.
Optionally, in the array substrate provided in an embodiment of the present disclosure, as shown in fig. 1 to 5, the array substrate further includes: a strip-shaped common electrode 106 positioned on a side of the second inorganic passivation layer 105 away from the substrate base plate 101, and a common voltage line 107 disposed on the same layer as the gate 1024 of the transistor 102;
an orthographic projection of the strip-shaped common electrode 106 on the substrate base plate 101 covers an orthographic projection of the pixel electrode 103, and the strip-shaped common electrode 106 is electrically connected with the common voltage line 107 through a via hole penetrating through each layer between the gate 1024 and the strip-shaped common electrode 106.
In the present disclosure, the term "same layer arrangement" refers to a layer structure formed by forming a film layer for forming a specific pattern by the same film formation process and then performing a patterning process by one step using the same mask plate. Namely, the one-time composition process corresponds to one mask plate. Depending on the specific pattern, the single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and the specific patterns may be at different heights or have different thicknesses. Therefore, the gate 1024 and the common voltage line 107 are disposed in the same layer, so that the mask process can be reduced, the production efficiency can be improved, and the light and thin design can be realized.
Generally, the array substrate provided in the embodiment of the present disclosure may further include a gate insulating layer 108 between the gate electrode 1024 and the active layer 1021, a gate line (not shown) disposed on the same layer as the gate electrode 1024, and a data line (not shown) disposed on the same layer as the first and second electrodes 1022 and 1023, as shown in fig. 1 to 5. The gate insulating layer 108, the gate lines and the data lines are arranged in the same manner as in the related art, and the manufacturing method is not limited herein.
Based on the same inventive concept, the embodiment of the present disclosure provides a method for manufacturing an array substrate, and because the principle of the method for solving the problem is similar to the principle of the method for solving the problem of the array substrate, the implementation of the method for manufacturing the array substrate provided by the embodiment of the present disclosure may refer to the implementation of the array substrate provided by the embodiment of the present disclosure, and repeated details are omitted.
Specifically, the method for manufacturing an array substrate provided by the embodiment of the present disclosure includes:
providing a substrate base plate;
forming a transistor, a first inorganic passivation layer and a second inorganic passivation layer on a substrate;
wherein the step of forming the transistor comprises:
forming a semiconductor material layer on the substrate base plate, wherein the semiconductor material layer comprises a first part and a second part, the first part is used for forming an active layer, the second part is used for forming a pixel electrode, the orthographic projection of the first part on the substrate base plate is mutually overlapped with the active layer, and the orthographic projection of the second part on the substrate base plate is not mutually overlapped with the active layer;
conducting the second part to form a pixel electrode;
at least a partial region of the second inorganic passivation layer is in direct contact with the first inorganic passivation layer.
Optionally, in the manufacturing method provided by the embodiment of the present disclosure, after the step of performing the step of forming the semiconductor material layer on the substrate and before the step of performing the step of conducting the second portion to form the pixel electrode, the following steps may be further performed:
and forming a photoresist layer covering the active layer, and preliminarily performing conductor treatment on a second part contained in the semiconductor material layer by using the photoresist layer as a mask.
When the semiconductor material layer is made of an oxide such as IGZO, a large amount of oxygen is present in the semiconductor material layer, and the second portion included in the semiconductor material layer for forming the pixel electrode is preliminarily made conductive, whereby the amount of oxygen can be greatly reduced and the second portion for forming the pixel electrode can be made conductive. In the subsequent process of depositing the first inorganic passivation layer made of silicon oxide, oxygen of the silicon oxide can enter the semiconductor material layer after preliminary conductor formation, so that a conductor removing effect is generated, and the conductivity of the pixel electrode is influenced. Based on this, through getting rid of the silicon oxide of pixel electrode top, form the fretwork region of first inorganic passivation layer to can first inorganic passivation layer be the mask plate, realize the secondary conductor to the pixel electrode, solve the de-conductor problem that silicon oxide caused, promote the electric conductivity of pixel electrode.
Optionally, in the manufacturing method provided in the embodiment of the present disclosure, forming the first inorganic passivation layer may be specifically implemented in the following manner:
and forming a first inorganic passivation layer having a hollow area at the position of the second portion.
Optionally, in the manufacturing method provided in the embodiment of the present disclosure, the forming the pixel electrode by converting the second portion into a conductor may specifically include:
and using the first inorganic passivation layer with the hollow area as a mask plate to conduct the conductor on the second part contained in the semiconductor material layer to form a pixel electrode.
It should be noted that, in the manufacturing method provided in the embodiment of the present invention, the patterning process related to forming each layer structure may include not only some or all of the processes of deposition, photoresist coating, mask masking, exposure, development, etching, and photoresist stripping, but also other processes, and specifically, a pattern to be patterned is formed in an actual manufacturing process, which is not limited herein. For example, a post-bake process may also be included after development and before etching.
The deposition process may be a chemical vapor deposition method, a plasma enhanced chemical vapor deposition method, or a physical vapor deposition method, which is not limited herein; the Mask used in the Mask process may be a Half-Tone Mask (Half Tone Mask), a Single Slit diffraction Mask (Single Slit Mask) or a Gray Tone Mask (Gray Tone Mask), which is not limited herein; the etching may be dry etching or wet etching, and is not limited herein.
In order to better understand the above-mentioned fabrication method provided by the embodiments of the present disclosure, the fabrication process of the array substrate shown in fig. 1 to 5 will be described in detail below.
Specifically, the manufacturing process of the array substrate shown in fig. 1 is as follows:
a gate electrode 1024 and a common voltage line 107 are patterned at a time on the substrate base 101, as shown in fig. 6;
sequentially depositing a gate insulating layer 108 and a semiconductor material layer, and patterning the semiconductor material layer to obtain a first portion for forming an active layer 1021 and a second portion for forming a pixel electrode 103, wherein an orthographic projection of the second portion on the substrate base 101 and an orthographic projection of the active layer 1021 do not overlap with each other, as shown in fig. 7;
forming a first inorganic passivation layer 104 by a patterning process, wherein the first inorganic passivation layer 104 has a hollow area at a second part of the semiconductor material layer, and the first inorganic passivation layer 104 is used as a mask to implement a conductive process on the second part of the semiconductor material layer for forming the pixel electrode 103, so as to ensure the conductivity of the pixel electrode 103, thereby completing the fabrication of the pixel electrode 103, as shown in fig. 8;
a first pole 1022 and a second pole 1023 are formed by a patterning process, and the second pole 1023 is directly connected to the pixel electrode 103, so that the transistor 102 is completed, as shown in fig. 9;
depositing a thin film material layer for forming the second inorganic passivation layer 105, and forming a via hole penetrating the first inorganic passivation layer 104, the second inorganic passivation layer 105 and the gate insulating layer 108 at the position of the common voltage line 107, as shown in fig. 10;
a stripe-shaped common electrode 106 electrically connected to the common voltage line 107 at the via hole is formed, and an orthogonal projection of the stripe-shaped common electrode 106 on the substrate base plate 101 covers an orthogonal projection of the pixel electrode 103, as shown in fig. 1.
Thus, the fabrication of the array substrate shown in fig. 1 is completed.
Specifically, the manufacturing process of the array substrate shown in fig. 2 is as follows:
two gates 1024 and a common voltage line 107 are patterned at a time on the substrate base 101, as shown in fig. 11;
sequentially depositing a gate insulating layer 108 and a semiconductor material layer, and patterning the semiconductor material layer to obtain a first portion for forming an active layer 1021 and a second portion for forming a pixel electrode 103, wherein an orthographic projection of the second portion on the substrate base 101 and an orthographic projection of the active layer 1021 do not overlap with each other, as shown in fig. 12;
forming a first inorganic passivation layer 104 by a patterning process, wherein the first inorganic passivation layer 104 has a hollow area at a second part of the semiconductor material layer, and the first inorganic passivation layer 104 is used as a mask to implement a conductive process on the second part of the semiconductor material layer for forming the pixel electrode 103, so as to ensure the conductivity of the pixel electrode 103, thereby completing the fabrication of the pixel electrode 103, as shown in fig. 13;
a first pole 1022 and a second pole 1023 are formed by a patterning process, and the second pole 1023 is directly connected to the pixel electrode 103, so that the transistor 102 is completed, as shown in fig. 14;
depositing a thin film material layer for forming the second inorganic passivation layer 105, and forming a via hole penetrating the first inorganic passivation layer 104, the second inorganic passivation layer 105 and the gate insulating layer 108 at the position of the common voltage line 107, as shown in fig. 15;
a stripe-shaped common electrode 106 electrically connected to the common voltage line 107 at the via hole is formed, and an orthogonal projection of the stripe-shaped common electrode 106 on the substrate base plate 101 covers an orthogonal projection of the pixel electrode 103, as shown in fig. 2.
Thus, the fabrication of the array substrate shown in fig. 2 is completed.
Specifically, the manufacturing process of the array substrate shown in fig. 3 is as follows:
a gate electrode 1024 and a common voltage line 107 are patterned at a time on the substrate base 101, as shown in fig. 6;
sequentially depositing a gate insulating layer 108 and a semiconductor material layer, and patterning the semiconductor material layer to obtain a first portion for forming an active layer 1021 and a second portion for forming a pixel electrode 103, wherein an orthographic projection of the second portion on the substrate base 101 and an orthographic projection of the active layer 1021 do not overlap with each other, as shown in fig. 7;
a first pole 1022 and a second pole 1023 are formed by a patterning process, and the second pole 1023 is directly connected to the pixel electrode 103, so that the transistor 102 is completed, as shown in fig. 16;
forming a first inorganic passivation layer 104 by a patterning process, where the first inorganic passivation layer 104 has a hollow area at a second portion of the semiconductor material layer, and the first inorganic passivation layer 104 is used as a mask to implement a conductive process on the second portion of the semiconductor material layer for forming the pixel electrode 103, so as to ensure the conductivity of the pixel electrode 103, thereby completing the fabrication of the pixel electrode 103, as shown in fig. 17;
depositing a thin film material layer for forming the second inorganic passivation layer 105, and forming a via hole penetrating the first inorganic passivation layer 104, the second inorganic passivation layer 105 and the gate insulating layer 108 at the position of the common voltage line 107, as shown in fig. 18;
a stripe-shaped common electrode 106 electrically connected to the common voltage line 107 at the via hole is formed, and an orthogonal projection of the stripe-shaped common electrode 106 on the substrate base plate 101 covers an orthogonal projection of the pixel electrode 103, as shown in fig. 3.
Thus, the fabrication of the array substrate shown in fig. 3 is completed.
Specifically, the manufacturing process of the array substrate shown in fig. 4 is as follows:
a first pole 1022 and a second pole 1023 are patterned once on the substrate base 101, as shown in fig. 19;
depositing a semiconductor material layer, and patterning the semiconductor material layer to obtain a first portion for forming the active layer 1021 and a second portion for forming the pixel electrode 103, wherein an orthogonal projection of the second portion on the substrate base plate 101 and an orthogonal projection of the active layer 1021 do not overlap with each other, as shown in fig. 20;
forming a photoresist layer 109 at the position of the active layer 1021 through a patterning process, and performing preliminary conductor processing on a second part of the semiconductor material layer for forming the pixel electrode 103 by using the photoresist layer 109 as a mask, so as to realize the conductivity of the pixel electrode 103, as shown in fig. 21;
the gate 1024 and the common voltage line 107 are formed by a patterning process, and thus the fabrication of the transistor 102 is completed, as shown in fig. 22;
forming a first inorganic passivation layer 104 by a patterning process, wherein the first inorganic passivation layer 104 has a hollow area at the second part of the semiconductor material layer, and the first inorganic passivation layer 104 is used as a mask to implement a second partial re-conductor process for forming the pixel electrode 103 in the semiconductor material layer, so as to avoid a de-conductor effect of the first inorganic passivation layer 104 and ensure the electrical conductivity of the pixel electrode 103, thereby completing the fabrication of the pixel electrode 103, as shown in fig. 23;
depositing a thin film material layer for making the second inorganic passivation layer 105, and forming a via hole penetrating the first inorganic passivation layer 104 and the second inorganic passivation layer 105 at the position of the common voltage line 107, as shown in fig. 24;
a stripe-shaped common electrode 106 electrically connected to the common voltage line 107 at the via hole is formed, and an orthogonal projection of the stripe-shaped common electrode 106 on the substrate base plate 101 covers an orthogonal projection of the pixel electrode 103, as shown in fig. 4.
Thus, the array substrate shown in fig. 4 is manufactured.
Specifically, the manufacturing process of the array substrate shown in fig. 5 is as follows:
a gate electrode 1024 and a common voltage line 107 are patterned at a time on the substrate base 101, as shown in fig. 6;
sequentially depositing a gate insulating layer 108 and a semiconductor material layer, and patterning the semiconductor material layer to obtain a first portion for forming an active layer 1021 and a second portion for forming a pixel electrode 103, wherein an orthographic projection of the second portion on the substrate base 101 and an orthographic projection of the active layer 1021 do not overlap with each other, as shown in fig. 7;
forming a photoresist layer 109 at the position of the active layer 1021 through a patterning process, and performing a conductor process on a second portion of the semiconductor material layer used for forming the pixel electrode 103 by using the photoresist layer 109 as a mask to realize conductivity of the pixel electrode 103, thereby completing fabrication of the pixel electrode 103, as shown in fig. 25;
a first pole 1022 and a second pole 1023 are formed by a patterning process, and the second pole 1023 is directly connected to the pixel electrode 103, so that the transistor 102 is completed, as shown in fig. 16;
sequentially depositing a first inorganic thin film layer for fabricating the first inorganic passivation layer 104 and a second inorganic thin film layer for fabricating the second inorganic passivation layer 105, and forming a via hole penetrating the first inorganic passivation layer 104 and the second inorganic passivation layer 105 at a position of the common voltage line 107 through a one-time patterning process, as shown in fig. 26;
a stripe-shaped common electrode 106 electrically connected to the common voltage line 107 at the via hole is formed, and an orthogonal projection of the stripe-shaped common electrode 106 on the substrate base plate 101 covers an orthogonal projection of the pixel electrode 103, as shown in fig. 5.
Thus, the array substrate shown in fig. 5 is completed.
In the array substrate and the manufacturing method thereof provided by the embodiment of the disclosure, the thicknesses of the first inorganic passivation layer and the second inorganic passivation layer can be adjusted according to the requirement of an actual product on the stability of the transistor, so that the first inorganic passivation layer and the second inorganic passivation layer have the functions of water resistance, hydrogen resistance and planarization of the resin layer in the related technology, the resin layer is not required to be arranged, the generation of cross-linking reaction products, solvents, water and the like in the heating and curing process of the resin layer in an Outgas form is avoided, and the number of mask plates is reduced. In addition, in the present disclosure, the same semiconductor material layer is used, the first portion for forming the active layer and the second portion for forming the pixel electrode are formed through a single patterning process, and then the second portion included in the semiconductor material layer is subjected to a conductor, so that the corresponding semiconductor material layer can be used as the pixel electrode. Due to the arrangement, a film layer of the pixel electrode is prevented from being independently arranged, the raw material cost is saved, and the light and thin design of the product is realized. In some embodiments, a mask for manufacturing the pixel electrode is also saved.
It will be apparent to those skilled in the art that various changes and modifications may be made to the disclosed embodiments without departing from the spirit and scope of the disclosed embodiments. Thus, if such modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to encompass such modifications and variations.
Claims (12)
- An array substrate, comprising:a substrate base plate;the transistor is positioned on the substrate and comprises an active layer, and the active layer is made of semiconductor materials;the pixel electrode is arranged on the same layer as the active layer, the orthographic projection of the pixel electrode on the substrate and the orthographic projection of the active layer are not overlapped, and the material of the pixel electrode is the semiconductor material which is made of a conductor;the first inorganic passivation layer is positioned on one side of the pixel electrode, which is far away from the substrate;a second inorganic passivation layer on a side of the first inorganic passivation layer facing away from the substrate base plate, at least a partial region of the second inorganic passivation layer being in direct contact with the first inorganic passivation layer.
- The array substrate of claim 1, wherein the first inorganic passivation layer has a hollowed-out region, and the second inorganic passivation layer covers the pixel electrode and is in direct contact with the pixel electrode at the hollowed-out region.
- The array substrate of claim 2, wherein the transistor further comprises: the grid electrode is positioned between the active layer and the substrate base plate, and the first pole and the second pole are positioned on one side, away from the substrate base plate, of the active layer;the first inorganic passivation layer is positioned between the first pole and the second pole layer and the active layer;the orthographic projection of the grid electrode on the substrate base plate is positioned in the orthographic projection of the active layer;an orthographic projection of the first pole on the substrate overlaps with an orthographic projection portion of the first inorganic passivation layer, the first pole comprising a portion in direct contact with the first inorganic passivation layer and a portion in direct contact with the active layer;an orthographic projection of the second pole on the substrate overlaps with an orthographic projection portion of the first inorganic passivation layer, the second pole including a portion in direct contact with the first inorganic passivation layer, a portion in direct contact with the active layer, and a portion in direct contact with the pixel electrode.
- The array substrate of claim 3, wherein the gate electrode is one, an orthographic projection of the gate electrode on the substrate coincides with a region of the first inorganic passivation layer directly contacting the first pole, the second pole and the active layer, and a boundary of the gate electrode has a first distance from a boundary of the first pole or the second pole adjacent to a central region of the active layer;or, there are two gate electrodes, an orthographic projection of the gate electrode on the substrate coincides with a region of the first inorganic passivation layer directly contacting the first pole and the second pole, and a second distance is formed between a boundary of the gate electrode away from the central region of the active layer and a boundary of the first pole or the second pole adjacent to the central region of the active layer;the first distance is twice the second distance.
- The array substrate of claim 2, wherein the transistor further comprises: the grid electrode is positioned between the active layer and the substrate base plate, and the first pole and the second pole are positioned on one side, away from the substrate base plate, of the active layer;the first inorganic passivation layer is positioned between the first electrode and the second electrode layer and the second inorganic passivation layer and is connected with the first electrode, the second electrode and the active layer;the orthographic projection of the grid electrode on the substrate covers the orthographic projection of the active layer;the first pole is in direct contact with the active layer, and the second pole is in direct contact with the active layer and the pixel electrode.
- The array substrate of claim 2, wherein the transistor further comprises: a first electrode and a second electrode between the active layer and the substrate base plate, and a gate electrode between the active layer and the first inorganic passivation layer;the orthographic projection of the grid electrode on the substrate is superposed with the orthographic projection of the active layer;the active layer covers the first pole and the second pole, and the bottom of the central region of the active layer is flush with the bottom of the first pole and the bottom of the second pole;the second electrode is directly connected to the pixel electrode.
- The array substrate of claim 1, wherein the transistor further comprises: a gate electrode between the active layer and the substrate base plate, and first and second poles between the active layer and the first inorganic passivation layer;the first inorganic passivation layer covers the first pole, the second pole, the active layer and the pixel electrode;the orthographic projection of the grid electrode on the substrate covers the orthographic projection of the active layer;the first pole is in direct contact with the active layer, and the second pole is in direct contact with the active layer and the pixel electrode.
- The array substrate of any one of claims 1-7, further comprising: the strip-shaped common electrode is positioned on one side, away from the substrate base plate, of the second inorganic passivation layer, and the common voltage line is arranged on the same layer as the grid electrode of the transistor;the orthographic projection of the strip-shaped common electrode on the substrate covers the orthographic projection of the pixel electrode, and the strip-shaped common electrode is electrically connected with the common voltage line through a through hole penetrating through each layer between the grid electrode and the strip-shaped common electrode.
- A manufacturing method of an array substrate comprises the following steps:providing a substrate base plate;forming a transistor, a first inorganic passivation layer and a second inorganic passivation layer on the substrate base plate;wherein the step of forming a transistor comprises:forming a semiconductor material layer on the substrate base plate, wherein the semiconductor material layer comprises a first part and a second part, the first part is used for forming an active layer, the second part is used for forming a pixel electrode, the orthographic projection of the first part on the substrate base plate is mutually overlapped with the active layer, and the orthographic projection of the second part on the substrate base plate is not overlapped with the active layer;conducting the second portion to form the pixel electrode;at least a partial region of the second inorganic passivation layer is in direct contact with the first inorganic passivation layer.
- The method of claim 9, wherein after forming a layer of semiconductor material on the substrate base plate and before the conducting the second portion to form the pixel electrode, further comprises:and forming a photoresist layer covering the active layer, and performing preliminary conductor treatment on the second part contained in the semiconductor material layer by using the photoresist layer as a mask.
- The manufacturing method according to claim 9 or 10, wherein the forming of the first inorganic passivation layer specifically comprises:forming the first inorganic passivation layer having a hollowed-out region at a position of the second portion.
- The manufacturing method according to claim 11, wherein the conducting the second portion to form the pixel electrode specifically includes:and conducting the second part by using the first inorganic passivation layer with the hollow area as a mask plate to form the pixel electrode.
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| CN114188353A (en) * | 2021-12-02 | 2022-03-15 | 深圳市华星光电半导体显示技术有限公司 | TFT array substrate and display panel |
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| CN115202126B (en) * | 2022-07-26 | 2024-10-18 | 福州京东方光电科技有限公司 | Array substrate and electronic paper display device |
| CN116419566B (en) * | 2023-02-13 | 2023-09-19 | 北京超弦存储器研究院 | Semiconductor structure, preparation method thereof, memory and electronic equipment |
| CN116449617A (en) * | 2023-04-19 | 2023-07-18 | 厦门天马微电子有限公司 | Display panel and display device |
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