CN114883370A

CN114883370A - Display panel, preparation method thereof and display terminal

Info

Publication number: CN114883370A
Application number: CN202210492251.0A
Authority: CN
Inventors: 刘赟夕; 郑帅
Original assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2022-05-07
Filing date: 2022-05-07
Publication date: 2022-08-09

Abstract

The invention provides a display panel, a preparation method thereof and a display terminal, wherein the display panel comprises a substrate layer, a first metal layer, an active layer and a second metal layer; the first metal layer comprises a first plate of the storage capacitor; the active layer includes a second plate of the storage capacitor; the second metal layer comprises a third polar plate of the storage capacitor, and the third polar plate is electrically connected with the first polar plate; the surface of one side, facing the second metal layer, of the active layer is provided with a barrier layer, the barrier layer comprises a first barrier part, and the first barrier part is positioned on the second polar plate; according to the invention, the barrier layer is arranged on the surface of one side of the active layer facing to the second metal layer, and the first barrier part of the barrier layer can block the second electrode plate from being de-conducted, so that the three-layer interlayer capacitor structure is prepared on the premise of ensuring the flatness of the light-emitting area of the pixel, the capacitance value of the storage capacitor meets the display driving requirement of the display panel, and the display performance of the display panel is improved.

Description

Display panel, preparation method thereof and display terminal

Technical Field

The invention relates to the technical field of display, in particular to a display panel, a preparation method of the display panel and a display terminal.

Background

A conventional pixel Driving circuit of an Organic Light Emitting Diode (OLED) display panel generally includes a switching thin film transistor (Switch TFT), a Driving thin film transistor (Driving TFT), and a storage capacitor (Cst), and a Top-gate thin film transistor (Top-gate TFT) and a Light Emitting material Evaporation (Evaporation) process are conventionally adopted in an array substrate process. In order to improve the mass production characteristics of the OLED display panel and reduce the cost of the array substrate process, one of the current development directions is to adopt a Gate-Source-Drain (GSD) process that can reduce the yellow light process, and to combine with an Ink-jet Printing (IJP) technology, so as to further improve the mass production feasibility of the OLED display panel.

The current Bottom emission (Bottom emission) OLED display panel needs to be provided with a light emitting area independent of a circuit area, which is not beneficial to improving the aperture opening ratio; the Top-emitting (Top emission) OLED display panel does not need to be provided with an independent light-emitting area, so that higher aperture opening ratio can be realized, and the display performance of the OLED display panel is improved. The OLED display panel of the GSD process of top-emitting light can improve the pixel resolution by adopting the design that the storage capacitor is arranged below the light-emitting device.

Since the IJP technology has a high requirement on the flatness of the pixel light-emitting area, the OLED display panel of the current GSD process generally adopts a capacitance structure of upper and lower plates of a light-shielding Layer (LS)/an active layer (IGZO) to ensure the driving performance of the OLED display panel, so that holes do not need to be drilled on a planarization layer, and the flatness of the pixel light-emitting area can be ensured. However, as the resolution is increased, the capacitance values of the upper and lower plate capacitor structures cannot meet the display driving requirements of the OLED display panel, and the display performance of the OLED display panel is affected. If a three-layer interlayer capacitor structure with one electrode plate additionally arranged between the active layer and the planarization layer is adopted to improve the capacitance value, the conductor of the active layer is removed, and the electric conduction cannot be realized. Therefore, it is necessary to improve this defect.

Disclosure of Invention

The embodiment of the invention provides a display panel, which is used for solving the technical problems that a capacitance plate is additionally arranged between an active layer and a planarization layer of the display panel in the prior art, so that the active layer is de-conducted and cannot conduct electricity.

The embodiment of the invention provides a display panel, which comprises a substrate layer, a first metal layer, an active layer and a second metal layer; the first metal layer is positioned on the substrate layer and comprises a first polar plate of the storage capacitor; the active layer is positioned on the first metal layer and comprises a second plate of the storage capacitor; the second metal layer is positioned on the active layer and comprises a third polar plate of the storage capacitor, and the third polar plate is electrically connected with the first polar plate; and a blocking layer is arranged on one side surface of the active layer facing the second metal layer, and comprises a first blocking part, and the first blocking part is positioned on the second polar plate.

In the display panel provided in the embodiment of the present invention, in a direction perpendicular to a light exit side of the display panel, a width of the first blocking portion and a width of the second electrode plate are both greater than a width of the first electrode plate.

In the display panel provided in the embodiment of the present invention, the second plate includes a conductor portion and semiconductor portions located on both sides of the conductor portion, and an orthographic projection of the first plate on the second plate is located on the conductor portion.

In the display panel provided by the embodiment of the invention, the first barrier covers a side surface of the second electrode plate far away from the first electrode plate and a side surface of the second electrode plate.

In the display panel provided by the embodiment of the invention, the active layer includes an active pattern, and the active pattern includes a channel portion and a source contact portion and a drain contact portion located at both sides of the channel portion; the second metal layer comprises a gate, a source and a drain, wherein an orthographic projection of the gate on the active pattern is positioned on the channel part, the source is electrically connected with the source contact part, and the drain is electrically connected with the drain contact part.

In the display panel provided by the embodiment of the invention, the barrier layer includes a second barrier portion and a third barrier portion, the second barrier portion is located on the source contact portion, and the third barrier portion is located on the drain contact portion.

The embodiment of the invention provides a preparation method of a display panel, which comprises the following steps: forming a first metal layer on the substrate layer; the first metal layer is subjected to patterning treatment to form a first plate of a storage capacitor; forming an active layer on the first metal layer; forming a barrier material layer on the surface of one side of the active layer, which is far away from the first metal layer; the active layer is patterned to form a second polar plate of the storage capacitor, and the blocking material layer is patterned to form a first blocking part, and the first blocking part is positioned on the second polar plate; and forming a second metal layer on the first barrier part, wherein the second metal layer is subjected to patterning treatment to form a third polar plate of the storage capacitor, and the third polar plate is electrically connected with the first polar plate.

In the method for manufacturing a display panel according to an embodiment of the present invention, the patterning of the active layer to form the second plate of the storage capacitor, and the patterning of the blocking material layer to form the first blocking portion include: the active layer is patterned to form a conductor structure and a second plate of the storage capacitor, and the blocking material layer is patterned and annealed to form a first blocking portion.

In the preparation method of the display panel provided by the embodiment of the present invention, the preparation method further includes: forming a gate insulating layer on a surface of the first barrier section away from the active layer and a surface of the active layer away from the first metal layer; annealing the gate insulating layer, wherein the region of the conductor structure, which is in contact with the gate insulating layer, is annealed to form a semiconductor structure, and the region of the second electrode plate, which is in contact with the gate insulating layer, is annealed to form a semiconductor part; forming a first contact hole and a second contact hole on the gate insulating layer to expose the semiconductor structure; conducting a conductorization process on the semiconductor structure within the first and second contact holes to form source and drain contacts.

The embodiment of the invention also provides a display terminal which comprises a terminal main body and the display panel, wherein the terminal main body and the display panel are combined into a whole.

Has the beneficial effects that: the display panel provided by the embodiment of the invention comprises a substrate layer, a first metal layer, an active layer and a second metal layer; the first metal layer is positioned on the substrate layer and comprises a first polar plate of the storage capacitor; the active layer is positioned on the first metal layer and comprises a second plate of the storage capacitor; the second metal layer is positioned on the active layer and comprises a third polar plate of the storage capacitor, and the third polar plate is electrically connected with the first polar plate; the surface of one side, facing the second metal layer, of the active layer is provided with a barrier layer, the barrier layer comprises a first barrier part, and the first barrier part is positioned on the second polar plate; according to the invention, the blocking layer is arranged on the surface of one side, facing the second metal layer, of the active layer, and the first blocking part of the blocking layer can block the second electrode plate from being de-conducted, so that the three-layer interlayer capacitor structure is prepared on the premise of ensuring the flatness of the light-emitting area of the pixel, the capacitance value of the storage capacitor meets the display driving requirement of the OLED display panel, and the display performance of the OLED display panel is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below.

Fig. 1 is a schematic diagram of a basic structure of a display panel in the prior art.

Fig. 2 is a schematic diagram of a basic structure of another display panel in the prior art.

Fig. 3 is a schematic diagram of a basic structure of a display panel according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of a basic structure of another display panel according to an embodiment of the present invention.

Fig. 5 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present invention.

Fig. 6a to 6g are schematic diagrams illustrating the basic structure of each component in the process flow of manufacturing the display panel according to the embodiment of the present invention.

Fig. 7a to 7e are schematic diagrams of basic structures of components in the process flow of fig. 6a to 6 b.

Fig. 8a to 8c are schematic diagrams of the basic structure of each component in the process flow from fig. 6b to 6 c.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. In the drawings, the size and thickness of components illustrated in the drawings are not to scale for clarity and ease of understanding and description.

As shown in fig. 1, which is a basic structural diagram of a display panel of the related art, the display panel of the related art generally uses a light shielding Layer (LS) and an active layer (IGZO) as upper and lower plates of C1, so that holes are not perforated in a planarization layer, so that the flatness of a pixel light emitting area can be ensured. However, as the resolution is increased, the capacitance of C1 cannot meet the display driving requirement of the display panel, and the display performance of the display panel is affected.

As shown in fig. 2, which is a schematic diagram of a basic structure of another display panel in the prior art, the other display panel in the prior art usually adopts a light shielding Layer (LS), an active layer (IGZO) and an Anode layer (Anode) as three-layer plates of C2, however, the inkjet printing technology has a high requirement on the flatness of the light-emitting area of the pixel, and if the structure of C2 is adopted, in order to increase the capacitance of C2, holes are inevitably required to be formed on the planarization layer in the pixel opening area, which may cause the deterioration of flatness and affect the yield of the display panel. If a three-layer interlayer capacitor structure with a layer of electrode plate additionally arranged between the active layer and the planarization layer is adopted to improve the capacitance value, the active layer is led to be de-conductor, and therefore the electric conduction cannot be achieved.

As shown in fig. 3, which is a schematic diagram of a basic structure of a display panel provided in an embodiment of the present invention, the display panel includes a substrate layer 10, a first metal layer 20, an active layer 40, and a second metal layer 70; the first metal layer 20 is located on the substrate layer 10, and the first metal layer 20 includes a first plate 201 of a storage capacitor; the active layer 40 is located on the first metal layer 20, and the active layer 40 includes a second plate 401 of the storage capacitor; the second metal layer 70 is located on the active layer 40, the second metal layer 70 includes a third plate 701 of the storage capacitor, and the third plate 701 is electrically connected to the first plate 201; wherein a blocking layer 50 is disposed on a side surface of the active layer 40 facing the second metal layer 70, the blocking layer 50 includes a first blocking portion 501, and the first blocking portion 501 is located on the second electrode plate 401.

It should be noted that, in the embodiment of the present invention, the third plate 701 is electrically connected to the first plate 201 to form a parallel capacitor structure (the capacitor formed by the first plate 201 and the second plate 401 is connected in parallel to the capacitor formed by the second plate 401 and the third plate 701), so as to increase the capacitance value of the storage capacitor. In the drawings, only the film layer structure is shown, and the wiring connection condition is not shown.

It can be understood that, in the present invention, the barrier layer 50 is disposed on the surface of the active layer 40 facing the side of the second metal layer 70, and the first barrier portion 501 of the barrier layer 50 can block the second electrode 401 from de-conducting, so that the three-layer interlayer capacitor structure is prepared on the premise of ensuring the flatness of the pixel light-emitting area, so that the capacitance value of the storage capacitor meets the display driving requirement of the display panel, thereby improving the display performance of the display panel.

The barrier layer 50 may block H and O elements, and may maintain the conductive property of the active layer 40 therebelow, and the material of the barrier layer 50 may be dense alumina, for example. The material of the active layer 40 is a metal oxide, such as Indium Gallium Zinc Oxide (IGZO).

In one embodiment, in a direction perpendicular to a light emitting side of the display panel, a width of the first blocking portion 501 and a width of the second plate 401 are both greater than a width of the first plate 201.

It can be understood that, in the present embodiment, by setting the width of the first barrier 501 and the width of the second plate 401 to be greater than the width of the first plate 201, the facing area between the first plate 201 and the second plate 401 can be increased, and the capacitance value of the capacitor formed by the first plate 201 and the second plate 401 can be increased.

In one embodiment, the second plate 401 includes a conductor portion 4011 and semiconductor portions 4012 located on two sides of the conductor portion 4011, and an orthogonal projection of the first plate 201 on the second plate 401 is located on the conductor portion 4011.

It can be understood that, since the first barrier 501 is located on the second plate 401, and the first barrier 501 does not cover the side of the second plate 401, the region where the side of the second plate 401 contacts the gate insulating layer 60 is de-conducted to form the semiconductor portion 4012, and the semiconductor portion 4012 cannot conduct electricity, in this embodiment, by disposing the orthographic projection of the first plate 201 on the second plate 401 on the conductor portion 4011, the area facing the first plate 201 and the conductor portion 4011 of the second plate 401 can be maximized, so as to increase the capacitance value of the capacitance formed by the first plate 201 and the second plate 401.

In one embodiment, the active layer 40 includes an active pattern 402, and the active pattern 402 includes a channel portion 4021 and source and

drain contacts

4022 and 4023 located at both sides of the channel portion 4021; the second metal layer 70 includes a gate 702, a source 703 and a drain 704, an orthogonal projection of the gate 702 on the active pattern 402 is located on the channel 4021, the source 703 is electrically connected to the source contact 4022, and the drain 704 is electrically connected to the drain contact 4023.

It is understood that the second plate 401 and the active pattern 402 of the storage capacitor may be formed in a single photo-masking process, and the third plate 701 and the gate 702, the source 703 and the drain 704 of the storage capacitor may be formed in a single photo-masking process. In addition, the third electrode plate 701 of the storage capacitor is arranged on the same layer as the gate 702, the source 703 and the drain 704, and holes do not need to be punched on the planarization layer 90, so that the flatness of a pixel light-emitting area can be ensured, and the yield of ink-jet printing is improved.

In one embodiment, the barrier layer 50 includes a second barrier 502 and a third barrier 503, the second barrier 502 is located on the source contact 4022, and the third barrier 503 is located on the drain contact 4023.

It can be understood that, in the present embodiment, by providing the second barrier 502 and the third barrier 503 on the upper surface of the active pattern 402, the second barrier 502 and the third barrier 503 can block the lower active pattern 402 from being deconducted, so that the lateral areas of the source contact 4022 and the drain contact 4023 can be increased, the conductive effect of the source 703 and the source contact 4022 can be improved, and the conductive effect of the drain 704 and the drain contact 4023 can be improved.

In one embodiment, the display panel further includes a buffer layer 30, a passivation layer 80, an anode layer 12, a pixel defining layer 13, an organic light emitting layer 14, and a cathode layer 15. The first metal layer 20 further includes a light shielding layer 202, and an orthographic projection of the channel portion 4021 on the first metal layer 20 is located on the light shielding layer 202. The buffer layer 30 is positioned between the first metal layer 20 and the active layer 40. The active pattern 402 further includes the semiconductor structure 42 located at one end of the source contact 4022 away from the channel portion 4021 and one end of the drain contact 4023 away from the channel portion 4021. The source electrode 703 overlaps the source contact 4022 through the first contact hole 601, and the drain electrode 704 overlaps the drain contact 4023 through the second contact hole 602. Passivation layer 80 is located between second metal layer 70 and planarization layer 90. The anode layer 12 is disposed on the planarization layer 90, and the anode layer 12 is electrically connected to the source electrode 703 through the fourth contact hole 11. A pixel defining layer 13 is positioned on the planarization layer 90 and the anode layer 12, the pixel defining layer 13 including a plurality of pixel openings. An organic light emitting layer 14 is positioned on the anode layer 12 within the pixel opening. The cathode layer 15 is positioned on the organic light emitting layer 14 and the pixel defining layer 13.

Next, referring to fig. 4, a basic structure diagram of another display panel according to an embodiment of the present invention is shown, and different from fig. 3, in this embodiment, the first blocking portion 501 covers a side surface of the second electrode plate 401 away from the first electrode plate 201 and a side surface of the second electrode plate 401.

It is understood that, in this embodiment, by making the first blocking portion 501 cover the upper surface and the side surface of the second plate 401, the second plate 401 can be prevented from forming the semiconductor portion 4012 (as shown in fig. 3) due to de-conduction, so that the width of the second plate 401 in the direction perpendicular to the light-emitting side of the display panel can be reduced to improve the resolution of the display panel.

In one embodiment, the second barrier 502 covers a side surface of the source contact 4022 away from the first metal layer 20 and a side surface of the source contact 4022 away from one end of the channel 4021, and the third barrier 503 covers a side surface of the drain contact 4023 away from the first metal layer 20 and a side surface of the drain contact 4023 away from one end of the channel 4021, so as to avoid forming the semiconductor structure 42 (as shown in fig. 3) at two ends of the active pattern 402, so as to further increase lateral areas of the source contact 4022 and the drain contact 4023, improve the conductive effects of the source 703 and the source contact 4022, and improve the conductive effects of the drain 704 and the drain contact 4023.

Next, referring to fig. 5, a flowchart of a method for manufacturing a display panel according to an embodiment of the present invention is shown, where the method includes:

s1, forming a first metal layer on the substrate layer;

s2, forming a first plate of a storage capacitor by patterning the first metal layer;

s3, forming an active layer on the first metal layer;

s4, forming a barrier material layer on the surface of one side, away from the first metal layer, of the active layer;

s5, patterning the active layer to form a second plate of the storage capacitor, and patterning the barrier material layer to form a first barrier, wherein the first barrier is located on the second plate;

and S6, forming a second metal layer on the first barrier, wherein the second metal layer is patterned to form a third plate of the storage capacitor, and the third plate is electrically connected with the first plate.

It can be understood that, in the invention, the blocking material layer is formed on the surface of one side of the active layer, which is far away from the first metal layer, and the first blocking part formed by patterning the blocking material layer can block the second electrode plate from being annealed, so that the three-layer interlayer capacitor structure is prepared on the premise of ensuring the flatness of the light emitting area of the pixel, and the capacitance value of the storage capacitor meets the display driving requirement of the display panel, so as to improve the display performance of the display panel.

The first barrier section may be made of dense alumina, for example, and may block H element and O element, and may maintain the conductive property of the second electrode below the first barrier section. The material of the active layer is a metal oxide, such as Indium Gallium Zinc Oxide (IGZO). Wherein the barrier material layer is, for example, aluminum, and in the process of forming the aluminum thin film on the IGZO, the aluminum thin film takes oxygen in the IGZO to form oxygen vacancies to realize the first conductimerization of the IGZO, and after the patterning process in step S5 is completed, the aluminum thin film is subjected to an Annealing process to form dense aluminum oxide (i.e., a first barrier portion).

In one embodiment, the step S5 includes: the active layer is patterned to form a conductor structure and a second plate of the storage capacitor, and the blocking material layer is patterned and annealed to form a first blocking portion.

It is understood that after the step S5, the active layer is conducted to form the conductor structure and the second plate, respectively, and the blocking material layer is patterned and annealed to form the first blocking portion, which can block the second plate therebelow from being conducted.

In one embodiment, between the step S5 and the step S6, the method further comprises: forming a gate insulating layer on a surface of the first barrier section away from the active layer and a surface of the active layer away from the first metal layer; annealing the gate insulating layer, wherein the region of the conductor structure, which is in contact with the gate insulating layer, is annealed to form a semiconductor structure, and the region of the second electrode plate, which is in contact with the gate insulating layer, is annealed to form a semiconductor part; forming a first contact hole and a second contact hole on the gate insulating layer to expose the semiconductor structure; conducting the semiconductor structure in the first contact hole and the second contact hole to form a source contact portion and a drain contact portion.

It can be understood that, since the gate insulating layer is to be formed on the active layer and the first barrier portion, and oxygen in the gate insulating layer is diffused into the active layer during the annealing process, a region of the conductor structure in contact with the gate insulating layer is annealed to form a semiconductor structure, a region of the second plate in contact with the gate insulating layer is annealed to form a semiconductor portion, and then a first contact hole and a second contact hole are formed on the gate insulating layer on the semiconductor structure, and the semiconductor structure in the first contact hole and the second contact hole is subjected to a conductor treatment (second conductor treatment) to form a source contact portion and a drain contact portion, and the semiconductor structure not exposed between the first contact hole and the second contact hole is a channel portion, thereby completing the active pattern.

Specifically, referring to fig. 6a to 6g, which are schematic diagrams illustrating a basic structure of each component in a process flow of manufacturing a display panel according to an embodiment of the present invention, as shown in fig. 6a, a first metal layer 20 is formed on a substrate layer 10, and the first metal layer 20 is patterned to form a light shielding layer 202 and a first plate 201 of a storage capacitor. The first metal layer 20 is divided into three layers, the lower layer contains one or more alloys of Mo, Ti and Ni, the middle layer is Cu or Cu alloy, and the upper layer contains one or more alloys of Mo, Ti and Ni. Wherein, the thickness range of the lower layer is 50-500 angstroms, the thickness range of the middle layer is 2000-10000 angstroms, and the thickness range of the upper layer is 50-500 angstroms.

Next, as shown in fig. 6b, a buffer layer 30 is formed on the first metal layer 20, the buffer layer 30 is one or a combination of silicon nitride and silicon oxide, and the thickness of the buffer layer 30 is in a range of 2000 to 10000 angstroms; then, an active layer 40 and a blocking material layer 51 are sequentially formed on the buffer layer 30, and a conductor structure 41 and a second plate 401 of the storage capacitor, a first blocking portion 501 on the second plate 401, a second blocking portion 502 on the conductor structure 41, and a third blocking portion 503 are formed by using a Half-tone Mask (Half-tone Mask), where the first blocking portion 501, the second blocking portion 502, and the third blocking portion 503 are collectively referred to as a blocking layer 50. The thickness of the active layer 40 is 100-1000 angstroms, and the thickness of the barrier layer 50 is 100-500 angstroms. In the direction perpendicular to the light-emitting side of the display panel, the difference between the width of the first barrier 501/the second plate 401 and the width of the first plate 201 is greater than 5 times the thickness of the active layer 40 in the direction from the first metal layer 20 to the active layer 40.

Next, as shown in fig. 6c, a gate insulating layer 60 is formed on the active layer 40 and the barrier layer 50, the material of the gate insulating layer 60 is silicon oxide, and through an annealing process, a semiconductor region (i.e., the semiconductor structure 42 and the semiconductor portion 4012) is formed in a region where the gate insulating layer 60 is in direct contact with the active layer 40 due to oxygen diffusion; then, a photomask is used to form the first contact hole 601, the second contact hole 602, and the third contact hole 603, and then Plasma (He Plasma) processing is performed on the semiconductor structure 42 in the first contact hole 601 and the second contact hole 602 to form the source contact portion 4022 and the drain contact portion 4023, and the semiconductor structure 42 not exposed between the first contact hole 601 and the second contact hole 602 is the channel portion 4021, so that the active pattern 402 is prepared. Wherein the thickness of the gate insulating layer 60 is 1000 to 3000 angstroms.

Next, as shown in fig. 6d, a second metal layer 70 is formed on the gate insulating layer 60, the second metal layer 70 is patterned to form a gate 702, a source 703, a drain 704 and a third plate 701 of the storage capacitor, the third plate 701 is electrically connected to the first plate 201 (not shown), the source 703 is electrically connected to the source contact 4022 through the first contact hole 601, the source 703 is electrically connected to the light-shielding layer 202 through the third contact hole 603, and the drain 704 is electrically connected to the drain contact 4023 through the second contact hole 602. The second metal layer 70 is divided into three layers, the lower layer contains one or more alloys of Mo, Ti, and Ni, the middle layer is Cu or Cu alloy, and the upper layer contains one or more alloys of Mo, Ti, and Ni. Wherein, the thickness range of the lower layer is 50-500 angstroms, the thickness range of the middle layer is 2000-10000 angstroms, and the thickness range of the upper layer is 50-500 angstroms.

Next, as shown in fig. 6e, a passivation layer 80 and a planarization layer 90 are sequentially formed on the second metal layer 70, the passivation layer 80 is made of silicon oxide, and the planarization layer 90 is an organic layer; a halftone Mask (Half-tone Mask) is then used to form the fourth contact hole 11 on the passivation layer 80 and the planarization layer 90. Wherein, the thickness range of the passivation layer 80 is 1000-5000 angstroms.

Next, as shown in fig. 6f, an anode layer 12 of the top-emitting OLED device is formed on the planarization layer 90, and the anode layer 12 is electrically connected to the source electrode 703 through the fourth contact hole 11. The anode layer 12 is a stacked structure of ITO/Ag/ITO.

Next, as shown in fig. 6g, a pixel defining layer 13 is formed on the planarization layer 90 and the anode layer 12, a plurality of pixel openings are formed on the pixel defining layer 13, an organic light emitting layer 14 is formed in the pixel openings using the IJP process, and finally a cathode layer 15 is formed on the pixel defining layer 13 and the organic light emitting layer 14, so that a display panel can be manufactured. The pixel defining layer 13 is an organic photoresist.

Referring to fig. 7a to 7e, which are schematic diagrams illustrating the basic structure of each component in the process flow of fig. 6a to 6b, first, as shown in fig. 7a, an active layer 40(IGZO) and a barrier material layer 51(Al) are sequentially formed on a buffer layer 30. Specifically, an Al thin film is prepared on the IGZO through sputtering (sputter), oxygen in the IGZO is extracted by the Al thin film to form oxygen vacancies in the preparation process, and the first conductimerization of the IGZO is realized, wherein an aluminum oxide thin film is formed on one side, close to the IGZO, of the Al thin film.

Next, as shown in fig. 7b, a corresponding Photoresist (PR) pattern 52 is formed on the barrier material layer 51 using a half-tone mask. Where a1 denotes a fully exposed region (light-transmitting), a2 denotes a partially exposed region (semi-light-transmitting), and A3 denotes a non-exposed region (light-shielding).

Next, as shown in fig. 7c, a first acid solution wet etching is performed by optimizing parameters to simultaneously remove the barrier material layer 51 and the active layer 40 in the region not covered by the photoresist pattern 52 (i.e., a1), and the active layer 40 forms the conductor structure 41 and the first plate 201 of the storage capacitor; the photoresist pattern 52 in the partially exposed region (i.e., a2) is then removed by a one-step ashing (Ash) process, exposing the barrier material layer 51 where openings are desired.

Next, as shown in fig. 7d, a second alkaline solution wet etching is performed by optimizing the parameters to remove the barrier material layer 51 in the a2 area, exposing the underlying conductor structure 41. The alkaline solution contains KOH, NaOH, TMAH and the like, and for example, the alkaline developer does not react with the IGZO, so that the surface of the IGZO is prevented from being damaged.

Next, as shown in fig. 7e, after removing the photoresist pattern 52, the barrier material layer 51(Al thin film) is converted into a barrier layer 50 (dense alumina) using an annealing process, and the barrier layer 50 includes a first barrier 501, a second barrier 502, and a third barrier 503.

Referring to fig. 8a to 8c, which are schematic diagrams illustrating the basic structure of each component in the process flow of fig. 6b to 6c, first, as shown in fig. 8a, a gate insulating layer 60 is formed on the barrier layer 50 and the active layer 40, the gate insulating layer 60 is annealed to diffuse oxygen into the active layer 40 in a region where the gate insulating layer 60 is in direct contact with the active layer 40, and a semiconductor structure 42 and a semiconductor portion 4012 are formed by deconduction in a region where the active layer 40 is in contact with the gate insulating layer 60; the barrier layer 50 has a function of blocking H element and O element, and a region protected by the barrier layer 50 maintains a conductor property, thereby forming the conductor structure 41 and the conductor portion 4011.

Next, as shown in fig. 8b, a first contact hole 601, a second contact hole 602, and a third contact hole 603 are formed on the gate insulating layer 60 using a mask.

Next, as shown in fig. 8c, Plasma (He Plasma) processing (second subconductor) is performed on the semiconductor structure 42 in the first contact hole 601 and the second contact hole 602 to form a source contact portion 4022 and a drain contact portion 4023, and the semiconductor structure 42 not exposed between the first contact hole 601 and the second contact hole 602 is a channel portion 4021, whereby the active pattern 402 is prepared.

An embodiment of the present invention further provides a display terminal, including a terminal main body and the display panel, where the terminal main body and the display panel are combined into a whole, and a structure and a manufacturing method of the display panel refer to fig. 3 to 8c and related descriptions, which are not described herein again. The display terminal provided by the embodiment of the invention can be as follows: products or components with display functions such as mobile phones, tablet computers, notebook computers, televisions, digital cameras, navigators and the like.

In summary, the display panel provided in the embodiments of the present invention includes a substrate layer, a first metal layer, an active layer, and a second metal layer; the first metal layer is positioned on the substrate layer and comprises a first polar plate of the storage capacitor; the active layer is positioned on the first metal layer and comprises a second plate of the storage capacitor; the second metal layer is positioned on the active layer and comprises a third polar plate of the storage capacitor, and the third polar plate is electrically connected with the first polar plate; the surface of one side, facing the second metal layer, of the active layer is provided with a barrier layer, the barrier layer comprises a first barrier part, and the first barrier part is positioned on the second polar plate; according to the invention, the blocking layer is arranged on the surface of one side, facing the second metal layer, of the active layer, and the first blocking part of the blocking layer can block the second electrode plate from being de-conductive, so that the three-layer interlayer capacitor structure is prepared on the premise of ensuring the flatness of the light emitting area of the pixel, the capacitance value of the storage capacitor meets the display driving requirement of the OLED display panel, the display performance of the OLED display panel is improved, and the technical problem that the active layer is de-conductive and cannot be conductive due to the fact that the capacitor electrode plate is additionally arranged between the active layer and the planarization layer of the display panel in the prior art is solved.

The display panel, the manufacturing method thereof and the display terminal provided by the embodiment of the invention are described in detail above. It should be understood that the exemplary embodiments described herein should be considered merely illustrative for facilitating understanding of the method of the present invention and its core ideas, and not restrictive.

Claims

1. A display panel, comprising:

a substrate layer;

the first metal layer is positioned on the substrate layer and comprises a first polar plate of the storage capacitor;

an active layer on the first metal layer, the active layer including a second plate of the storage capacitor;

the second metal layer is positioned on the active layer and comprises a third polar plate of the storage capacitor, and the third polar plate is electrically connected with the first polar plate;

and a blocking layer is arranged on one side surface of the active layer facing the second metal layer, and comprises a first blocking part, and the first blocking part is positioned on the second polar plate.

2. The display panel of claim 1, wherein a width of the first barrier portion and a width of the second plate are each greater than a width of the first plate in a direction perpendicular to a light exit side of the display panel.

3. The display panel according to claim 2, wherein the second plate includes a conductor part and semiconductor parts on both sides of the conductor part, and an orthographic projection of the first plate on the second plate is on the conductor part.

4. The display panel of claim 2, wherein the first barrier covers a side surface of the second plate away from the first plate and a side surface of the second plate.

5. The display panel according to claim 1, wherein the active layer includes an active pattern including a channel portion and source and drain contacts at both sides of the channel portion;

the second metal layer comprises a gate, a source and a drain, wherein an orthographic projection of the gate on the active pattern is positioned on the channel part, the source is electrically connected with the source contact part, and the drain is electrically connected with the drain contact part.

6. The display panel of claim 5, wherein the barrier layer comprises a second barrier portion and a third barrier portion, the second barrier portion being on the source contact portion, the third barrier portion being on the drain contact portion.

7. A method for manufacturing a display panel, comprising:

forming a first metal layer on the substrate layer;

the first metal layer is subjected to patterning treatment to form a first plate of a storage capacitor;

forming an active layer on the first metal layer;

forming a barrier material layer on the surface of one side of the active layer, which is far away from the first metal layer;

the active layer is patterned to form a second polar plate of the storage capacitor, and the blocking material layer is patterned to form a first blocking part, and the first blocking part is positioned on the second polar plate;

and forming a second metal layer on the first barrier part, wherein the second metal layer is subjected to patterning treatment to form a third polar plate of the storage capacitor, and the third polar plate is electrically connected with the first polar plate.

8. The method of manufacturing a display panel according to claim 7, wherein the active layer is patterned to form the second plate of the storage capacitor, and the blocking material layer is patterned to form the first blocking portion, comprising:

the active layer is patterned to form a second plate of the storage capacitor and a conductor structure, and the barrier material layer is patterned and annealed to form a first barrier.

9. The method for manufacturing a display panel according to claim 8, further comprising:

forming a gate insulating layer on a surface of the first barrier section away from the active layer and a surface of the active layer away from the first metal layer;

annealing the gate insulating layer, wherein the region of the conductor structure, which is in contact with the gate insulating layer, is annealed to form a semiconductor structure, and the region of the second electrode plate, which is in contact with the gate insulating layer, is annealed to form a semiconductor part;

forming a first contact hole and a second contact hole on the gate insulating layer to expose the semiconductor structure;

conducting the semiconductor structure in the first contact hole and the second contact hole to form a source contact portion and a drain contact portion.

10. A display terminal comprising a terminal body and the display panel according to any one of claims 1 to 6, the terminal body being integrated with the display panel.