KR100600848B1 - Flat Panel Display and Method for fabricating the Same - Google Patents

Abstract

The present invention relates to a flat panel display and a manufacturing method thereof.

A method of manufacturing a flat panel display device according to the present invention includes forming a semiconductor layer in a second region of an insulating substrate and forming a first electrode of a capacitor in a third region; Forming a gate insulating film; Forming a pixel electrode on a first region of the gate insulating film, and forming a first conductive pattern on the semiconductor layer; Implanting impurities of a predetermined conductivity type into the semiconductor layer and the first electrode; Forming a second conductive pattern on the pixel electrode, a gate electrode on the first conductive pattern, and a second electrode on the gate insulating film on the first electrode; Etching the first conductive pattern under the gate electrode; Forming an interlayer insulating film on the entire surface of the substrate; Forming first to fourth contact holes exposing portions of the source / drain electrode, the pixel electrode, and the first electrode, respectively; A source electrode contacting the source region through the first contact hole, a third electrode extending from the source electrode and connected to the first electrode through a third contact hole, and through the second and fourth contact holes Forming a drain electrode connected to the drain region and the pixel electrode; Forming a photosensitive film such that a portion of the interlayer insulating film corresponding to the pixel electrode is exposed; Etching the lower interlayer insulating layer and the second conductive pattern using the photosensitive layer to form openings.

Description

Flat Panel Display and Method for Fabricating the Same

1 is a cross-sectional structure diagram of a conventional organic light emitting display device;

2A to 2G are cross-sectional structure diagrams of an organic light emitting display device according to an embodiment of the present invention;

Explanation of symbols on the main parts of the drawings

100: insulation substrate 110: buffer area

120: semiconductor layer 125: channel region

121, 123: high and low concentration source region

122, 124: high concentration and low concentration drain region

127, 157, and 177: first, second and third electrodes of the capacitor

130: gate insulating film 140: pixel electrode

155: gate 160: interlayer insulating film

161-164: Contact hole 171, 172: Source / drain area

180: protective film 181: opening

190: organic EL layer 200: cathode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display and a method for manufacturing the same, and more particularly, to a flat panel display and a method for manufacturing the same, which simplify the process and improve capacitance.

1 shows a cross-sectional structure of a conventional organic light emitting display device. Referring to FIG. 1, a method of manufacturing a conventional organic light emitting display device is as follows.

First, a transparent insulating substrate 10 made of glass, synthetic resin, or the like is provided, wherein the insulating substrate 10 includes a first region 10-1 where pixel electrodes are to be formed and a second region 10 where a thin film transistor is to be formed. -2) and the third region 10-3 in which the capacitor is to be formed. A buffer layer 11 is formed on the substrate 10, a polysilicon film is coated on the buffer layer 11, and the polysilicon film is patterned using a mask for forming a semiconductor layer (not shown). The semiconductor layer 13 is formed in the two regions 10-2.

Thereafter, a gate insulating layer 15 is formed on the buffer layer 11 including the semiconductor layer 13, and a gate metal is deposited on the gate insulating layer 15. The gate metal is patterned by using a gate forming mask (not shown in the drawing) to form the gate electrode 16 in a portion of the gate insulating layer 15 corresponding to the semiconductor layer 13. When forming the gate electrode 16, the lower electrode 17 of the capacitor 52 is simultaneously formed in the third region 10-3. One of N-type or P-type impurities, for example, P-type impurities, is ion-implanted into the semiconductor layer 13 to form source / drain regions 13-1 and 13-2. At this time, the portion 13-3 between the source / drain regions 13-1 and 13-2 in the semiconductor layer 13 serves as a channel layer.

Next, an interlayer insulating film 19 is formed on the gate insulating film 15 including the gate electrode 16 and the lower electrode 17 of the capacitor. The interlayer insulating layer 19 and the gate insulating layer 15 are etched to form contact holes 20-1 and 20-2 exposing the source / drain regions 13-1 and 13-2. .

Subsequently, a source / drain metal is deposited on the interlayer insulating film 19, and patterned using a source / drain electrode forming mask (not shown) to form the source / drain regions 13-1 and ( 13-2) and source / drain electrodes 22-1 and 22-2 which are respectively contacted through the contact holes 20-1 and 20-2, and the source / drain electrodes 22 are formed. One of -1) and (22-2), for example, the upper electrode 22-3 of the capacitor 52 extending from the source electrode 22-1 is formed. As a result, the thin film transistor 51 and the capacitor 52 of the organic light emitting display device are formed. At this time, the portion of the interlayer insulating film 19 formed between the upper and lower electrodes 17 and 22-3 of the capacitor 52 serves as a dielectric of the capacitor.

After the source / drain electrodes 22-1, 22-2 and the upper electrode 22-3 are formed, a passivation film 25 is formed on the interlayer insulating film 19, and a via hole forming mask (Fig. (Not shown) to etch the passivation film 25 to expose one of the source / drain electrodes 22-1 and 22-2, for example, a drain electrode 22-2. (26) is formed.

Thereafter, a transparent conductive film, for example, ITO, is deposited on the passivation film 25, and then patterned ITO using a pixel electrode forming mask (not shown) to form the pixel electrode 27 as an anode electrode. Form. In this case, the pixel electrode 27 is electrically connected to the drain electrode 22-2 through the via hole 26.

When the anode electrode 27 is formed in this manner, the planarization film 28 is formed on the passivation film 25 including the anode electrode 27 and planarized using an opening forming mask (not shown). A portion of the film 28 corresponding to the anode electrode is etched to form the opening 28-1, thereby exposing the anode electrode 27.

Thereafter, by depositing an organic material having a predetermined color on the planarization film 28 including the openings 28-1, the organic EL layer 29 which emits red, green, and blue light by the flow of current itself. ). The cathode electrode 30 is formed by depositing a cathode metal on the planarization film 28 including the organic EL layer 29 to form the organic EL element 53.

According to the conventional method of manufacturing an organic light emitting display device as described above, a process for forming a semiconductor layer, a process for forming a gate electrode, a process for forming a contact hole for a source / drain electrode, a source / drain electrode 7 mask processes are required, such as a process for forming a hole, a process for forming a via hole, a process for forming a pixel electrode, and a process for forming an opening, resulting in complexity of the process, an increase in manufacturing cost, and a decrease in yield. There was this. In order to reduce the mask process, when the planarization film made of acryl or the like is not used, since the organic EL layer is deposited on the edge portion of the pixel electrode, which is a transparent electrode, a strong electric field is applied to the edge portion when voltage is applied to the pixel electrode. There was a problem of shortening the life.

In addition, after the via hole is formed, the lower layer, particularly the gate electrode and the source / drain electrode, are damaged when the transparent conductive layer for forming the pixel electrode is etched. In addition, since light emitted from the organic EL layer passes through various film qualities such as a multilayer insulating film, for example, a gate insulating film, an interlayer insulating film, and a protective film, there is a problem in that the luminance is lowered.

In addition, the flat panel display device described above has a problem in that the on / off current ratio is lowered due to the leakage current of the thin film transistor, thereby degrading the characteristics of the device. There was a problem that required or applied complex methods such as anodization.

Accordingly, an object of the present invention is to provide a flat panel display device and a method of manufacturing the same, which solve the problems of the prior art as described above, simplify the process, and improve capacitance.

Another object of the present invention is to provide a flat panel display device and a method of manufacturing the same, which can form an LDD structure or an offset structure without an additional process by using a transparent conductive film for pixel electrodes as an ion stopper.

In order to achieve the above object, the present invention provides an insulating substrate including a first region in which a pixel electrode is to be formed, a second region in which a thin film transistor is to be formed, and a third region in which a capacitor is formed; A pixel electrode formed in the first region; A thin film transistor including a semiconductor layer having a source / drain region, a gate electrode, and a source / drain electrode formed in the second region; And a capacitor having first to third electrodes formed in the third region, wherein one of the source / drain electrodes is connected to the pixel electrode, and the other of the source / drain electrodes is a third electrode of the capacitor. It is characterized by providing a flat panel display device connected to.

The first electrode of the capacitor is made of the same material as the semiconductor layer and is doped with the same conductive material as that of the source / drain region. The second electrode is made of the same material as the gate electrode. It is made of the same material as the drain electrode.

The present invention also provides an insulating substrate having a first region where a pixel electrode is to be formed, a second region where a thin film transistor is to be formed, and a third region where a capacitor is to be formed; Forming a semiconductor layer in the second region, and forming a first electrode of the capacitor in the third region; Forming a gate insulating film; Forming a pixel electrode on a first region of the gate insulating film, and forming a first conductive pattern on the semiconductor layer; Implanting impurities of a predetermined conductivity type into the semiconductor layer and the first electrode; Forming a second conductive pattern on the pixel electrode, a gate electrode on the first conductive pattern, and a second electrode on the gate insulating film on the first electrode; Etching the first conductive pattern under the gate electrode; Forming an interlayer insulating film on the entire surface of the substrate; Forming first and second contact holes exposing portions of the source / drain electrodes, respectively, and third and fourth contact holes exposing portions of the pixel electrode and the first electrodes, respectively; A source electrode contacting the source region through the first contact hole, a third electrode extending from the source electrode and connected to the first electrode through a third contact hole, and through the second and fourth contact holes Forming a drain electrode connected to the drain region and the pixel electrode; Forming a photosensitive film such that a portion of the interlayer insulating film corresponding to the pixel electrode is exposed; And forming an opening by etching the interlayer insulating layer and the second conductive pattern thereunder using the photosensitive film.

The first conductive pattern is formed of the same material as the pixel electrode, and serves as an ion stopper during the ion implantation process, and the gate electrode is formed to be smaller than the width of the first conductive pattern, thereby etching the first conductive pattern. The second conductive pattern is formed to be the same as or larger than the width of the pixel electrode to act as an etch barrier when the first conductive pattern is etched to protect the pixel electrode.

Forming a protective film before applying the photosensitive film; Etching the passivation layer, the interlayer insulating layer, and the first conductive pattern using the photosensitive layer as a mask to form an opening; The method may further include removing the remaining photoresist film.

Hereinafter, a manufacturing method of a flat panel display device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

2A through 2F are cross-sectional views illustrating a method of manufacturing an organic light emitting display device according to an exemplary embodiment of the present invention.

Referring to FIG. 2A, a first region 101 in which an organic light emitting diode including a pixel electrode is to be formed, a second region 101 in which a TFT is formed, and a third region 103 in which a capacitor is formed are provided. A transparent insulating substrate 100 is provided. A buffer layer 110 is formed on the insulating substrate 100, and an amorphous silicon film is deposited thereon. The amorphous silicon film is crystallized into a polysilicon film using a conventional crystallization method, and then the polysilicon film is patterned using a first mask (not shown) to form a semiconductor layer for TFT in the second region 102 ( The first electrode 127 for the capacitor is formed in the 120 and the third region 103.

Referring to FIG. 2B, a gate insulating layer 130 is deposited on the buffer layer 110 including the semiconductor layer 120 and the first electrode 127, and a transparent conductive layer is entirely deposited on the gate insulating layer 130. Subsequently, the transparent conductive film is patterned using a second mask (not shown in the drawing) to form the pixel electrode 140 in the first region 101, and at the same time, the semiconductor layer 120 in the second region 102. The first conductive pattern 142 is formed on the upper side of the. In this case, the first conductive pattern 142 is patterned to have a width larger than the width of the gate electrode to be formed in a subsequent process.

Next, a high concentration source / drain regions 121 and 122 are implanted by ion implanting n-type or p-type high concentration impurities, for example, P-type impurities, into the semiconductor layer 120 using the first conductive pattern 142 as a mask. ). At this time, since the P-type high concentration impurity is implanted into the first electrode 127 of the capacitor, the first electrode 127 becomes a doped polysilicon film and becomes a conductive material.

Referring to FIG. 2C, the gate electrode material is deposited on the entire surface of the substrate, and then the gate electrode material is patterned using a third mask (not shown in the drawing) to form a third gate electrode material on the first conductive pattern 142. The second electrode 157 for the capacitor is formed on the conductive pattern 152, the second conductive pattern 151, and the first electrode 127 of the third region 103 on the pixel electrode 140.

In the embodiment of the present invention, the second electrode 157 for the capacitor is made of a single gate electrode material, but may be formed of an ITO film in the process of FIG. 2B instead of a single gate electrode material, and also an ITO film and a gate electrode. It may be formed by a laminated structure of materials.

Subsequently, when the first conductive pattern 142 is etched using the third conductive pattern 152 as a mask, the gate electrode 155 having the stacked structure including the gate electrode material 152 and the transparent conductive material 142. ). In this case, the second conductive pattern 151 is formed to be equal to or larger than the width of the pixel electrode 140 below, and serves as an etching barrier when the first conductive pattern 142 is etched.

Next, a low concentration source / drain region 123 is implanted into the semiconductor layer 120 using a low concentration impurity of the same conductivity type as the high concentration source / drain regions 121 and 122 by using the gate electrode 155 as a mask. , 124 is formed to form an LDD structure. In this case, if the ion implantation process of low concentration impurities is omitted, the low concentration source / drain regions 123 and 124 may act as offset regions to form an offset structure.

Therefore, in the present invention, the first conductive pattern 142 serves as an ion stopper in the ion implantation process for forming the high concentration source / drain regions 121 and 122, and the gate electrode 155 has a low concentration source / drain. Since it acts as an ion stopper at the time of ion implantation to form a region, a mask process for a separate LDD region or an offset region is not required, so that one mask process can be omitted.

Referring to FIG. 2D, the interlayer insulating layer 160 is deposited on the entire surface of the substrate, and then the interlayer insulating layer 160 is etched using a fourth mask (not shown) as a mask to contact the contact holes 161-164. To form. The first and second contact holes 161 and 162 are formed to expose a portion of the high concentration source / drain regions 121 and 122, and the third contact hole 163 is the first electrode 127 of the capacitor. The fourth electrode 164 is formed to expose a portion of the second conductive pattern 151 on the pixel electrode 140.

In an embodiment of the present invention, in the process of forming a contact hole for electrically connecting the source / drain electrode and the source / drain region, a contact hole for electrically connecting one of the source / drain electrodes and the pixel electrode is formed at the same time. By zooming in, one mask process can be omitted.

Referring to FIG. 2E, a source / drain electrode material is deposited on the interlayer insulating layer 160 including the first to fourth contact holes 161 to 164, and then a fifth mask (not shown) is used. The source / drain electrode material is patterned to form a source electrode 171 electrically contacting the source region 121 through the first contact hole 161, and second and fourth contact holes 162 and 164. ) Forms a drain electrode 172 in electrical contact with the drain region 122 and the pixel electrode 140.

At the same time, a third electrode 177 extending from the source electrode 171 and electrically contacting the first electrode 127 through the third contact hole 163 is formed. Accordingly, the capacitor may include a first capacitor, a second electrode 157, and a third electrode 177 formed of a dielectric film including a first electrode 127, a second electrode 157, and a gate insulating layer 130 formed therebetween. Since the second capacitors made of a dielectric film made of an interlayer insulating film formed therebetween are connected in parallel, the capacitance can be improved more than that of a device which is usually composed of a single capacitor, and thus the aperture ratio can be improved.

As shown in FIG. 2G, a passivation layer 180 is formed on the interlayer insulating layer 160 including the source / drain electrodes 171 and 172 and the third electrode 177 of the capacitor. Applying a photosensitive film (not shown in the figure) on the protective film 180, and then patterning the photoresist using a sixth mask (not shown in the figure), and using the patterned photoresist as a mask to the protective film ( The 180 is etched to form an opening 181 exposing a portion of the pixel electrode 140. The photoresist film remaining after the opening 181 is formed is removed. As the passivation layer 180, a nitride layer or an oxide layer is used.

In this case, when the opening 181 is formed, the edge portion of the pixel electrode 140 is covered by the passivation layer 180 so as not to be exposed. This is to prevent the organic EL layer formed in a subsequent process from being damaged by a strong electric field formed at the edge portion of the pixel electrode 140.

In the exemplary embodiment of the present invention, an opening is formed by depositing the passivation layer 180 and then applying a photoresist layer. However, when the opening is formed, the photoresist layer is immediately applied without depositing the passivation layer 180 on the interlayer insulating layer 160. The remaining photoresist used as a mask may be used as a protective film.

As shown in FIG. 2G, when the organic EL layer 190 is formed in the opening 140 and the cathode 200 is formed thereon, an organic light emitting display device according to an exemplary embodiment of the present invention is obtained.

According to the manufacturing method of the organic light emitting display device as described above, an additional mask process is omitted by forming a source / drain region of the LDD structure or the offset structure using the transparent conductive film for pixel electrodes as an ion stopper. can do. In addition, the additional mask process can be omitted by forming the source / drain electrodes and the pixel electrode without a separate mask process. Therefore, since only six mask processes are performed to fabricate an organic light emitting display device having a thin film transistor having an LDD or offset structure, the process can be simplified.

In addition, since the pixel electrode is formed on the gate insulating film instead of the protective film, it is possible to prevent the lowering of luminance due to multiple reflections of light emitted from the organic EL layer as well as lower portions such as source / drain electrodes according to the pixel electrode formation. Damage to the membrane can be prevented.

In addition, since the capacitor has a structure in which two capacitors are connected in parallel, the capacitance can be improved, and thus the aperture ratio can be improved.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (14)

An insulating substrate having a first region where a pixel electrode is to be formed, a second region where a thin film transistor is to be formed, and a third region where a capacitor is to be formed; A pixel electrode formed in the first region; A thin film transistor including a semiconductor layer having a source / drain region, a gate electrode, and a source / drain electrode formed in the second region; A capacitor having first to third electrodes formed in the third region, And one of the source / drain electrodes is connected to the pixel electrode, and the other of the source / drain electrodes is connected to a third electrode of the capacitor. The flat panel display of claim 1, wherein the first electrode of the capacitor is made of the same material as the semiconductor layer and is doped with the same conductive material as the source / drain regions. The flat panel display of claim 1, wherein the gate electrode comprises the same material as the pixel electrode. The flat panel display of claim 1, wherein the second electrode of the capacitor is formed of the same material as the gate electrode. The flat panel display of claim 1, wherein the third electrode of the capacitor is made of the same material as the source / drain electrodes. The flat panel display of claim 1, wherein the source / drain region has an LDD structure or an offset structure. Providing an insulating substrate having a first region where a pixel electrode is to be formed, a second region where a thin film transistor is to be formed, and a third region where a capacitor is to be formed; Forming a semiconductor layer in the second region, and forming a first electrode of the capacitor in the third region; Forming a gate insulating film; Forming a pixel electrode on a first region of the gate insulating film, and forming a first conductive pattern on the semiconductor layer; Implanting impurities of a predetermined conductivity type into the semiconductor layer and the first electrode; Forming a second conductive pattern on the pixel electrode, a gate electrode on the first conductive pattern, and a second electrode on the gate insulating film on the first electrode; Etching the first conductive pattern under the gate electrode; Forming an interlayer insulating film on the entire surface of the substrate; Forming first and second contact holes exposing portions of the source / drain electrodes, respectively, and third and fourth contact holes exposing portions of the pixel electrode and first electrodes, respectively; A source electrode contacting the source region through the first contact hole, a third electrode extending from the source electrode and connected to the first electrode through a third contact hole, and through the second and fourth contact holes Forming a drain electrode connected to the drain region and the pixel electrode; Forming a photosensitive film such that a portion of the interlayer insulating film corresponding to the pixel electrode is exposed; And forming an opening by etching the interlayer insulating layer and the second conductive pattern thereunder using the photosensitive film. The method of claim 7, wherein the first conductive pattern is made of the same material as the pixel electrode and acts as an ion stopper during the ion implantation process. The method of claim 7, wherein the gate electrode is formed smaller than the width of the first conductive pattern to act as an etch barrier when the first conductive pattern is etched. The flat panel display device of claim 7, wherein the second conductive pattern is formed to be equal to or larger than the width of the pixel electrode to act as an etch barrier to etch the first conductive pattern. Way. The flat panel display device of claim 7, wherein the first conductive pattern serves as a gate electrode, and the gate electrode has a two-layer structure. The method of claim 7, wherein the remaining photoresist serves as a protective film. 8. The method of claim 7, further comprising: forming a protective film before applying the photosensitive film; Etching the passivation layer, the interlayer insulating layer, and the second conductive pattern using the photosensitive layer as a mask to form an opening; And removing the remaining photoresist. The method of claim 7, wherein the opening is smaller than the area of the pixel electrode.

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