CN104681627A - Array substrate, thin-film transistor and manufacturing methods thereof as well as display device - Google Patents

Array substrate, thin-film transistor and manufacturing methods thereof as well as display device Download PDF

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CN104681627A
CN104681627A CN 201510105369 CN201510105369A CN104681627A CN 104681627 A CN104681627 A CN 104681627A CN 201510105369 CN201510105369 CN 201510105369 CN 201510105369 A CN201510105369 A CN 201510105369A CN 104681627 A CN104681627 A CN 104681627A
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electrode
film
layer
gate
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王珂
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京东方科技集团股份有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66969Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Abstract

The invention belongs to the technical field of display, and particularly relates to an array substrate, a thin-film transistor and manufacturing methods thereof as well as a display device. The array substrate comprises a substrate (1), and an active layer (2), a source electrode (3), a drain electrode (4) and a pixel electrode (5) which are arranged on the same layer of the substrate (1), as well as a grid insulation layer (6) positioned on the active layer (2) and a grid electrode (7) positioned on the grid insulation layer (6), wherein the active layer (2), the source electrode (3), the drain electrode (4), the pixel electrode (5), the grid insulation layer (6) and the grid electrode (7) are formed through a one-time patterning process; the source electrode (3) is connected with the drain electrode (4) through the active layer (2). The array substrate solves the technical problems that the existing array substrate is relatively complicated in structure, more in manufacturing process, low in production efficiency, relatively high in cost and the like, can substitute the existing array substrate, and is applicable to the technical field of display.

Description

阵列基板、薄膜晶体管及制作方法、显示装置 An array substrate, a thin film transistor and a method of manufacturing a display device

技术领域 FIELD

[0001] 本发明属于显示技术领域,尤其涉及一种阵列基板、薄膜晶体管及制作方法、显示装置。 [0001] The present invention belongs to the technical field of display, in particular, relates to an array substrate, a thin film transistor and a method of manufacturing a display device.

背景技术 Background technique

[0002] 随着显示技术的飞速发展,人们对显示器的分辨率、响应时间、功耗等特性要求也越来越高。 [0002] With the rapid development of display technologies, people resolution of the display, the response time and power consumption characteristics are increasingly high requirements. 在这种情况下,随着显示器的尺寸越来越大以及3D等显示技术的发展,对设置在显示器阵列基板上的TFT (Thin Film Transistor,薄膜晶体管)的迀移率要求越来越高。 In this case, as the size of the display is increasing and the development of 3D and other display technologies, Gan to TFT (Thin Film Transistor, TFT) disposed on the array substrate of the shift of increasingly demanding. TFT的迀移率是指TFT的有源层中载流子(电子和空穴)在单位电场作用下的平均飘移速度。 The TFT Gan shift rate is the TFT active layer of carriers (electrons and holes) average drift velocity in the electric field units. 实际上用非晶硅制作有源层已不能满足对迀移率的要求,人们已经开始使用具有较高迀移速率的金属氧化物材料。 Actually making the active layer of amorphous silicon can not meet the requirements for Gan shift rate, people have started to use a metal oxide material having a higher Gan shift rate.

[0003] 目前金属氧化物技术已经逐渐成为大尺寸、高画质、低功耗显示器产品的主流技术,各大显示器商都在量产或者积极开发。 [0003] At present metal oxide technology has gradually become a large-size, high-quality, low-power display products of mainstream technology, the major display suppliers are in production or in active development. 高级超维场转换技术(ADvanced Super Dimension Switch,简称ADS)可以提高薄膜晶体管液晶显不器(Thin Film Transistor Liquid Crystal Display,简称TFT-LCD)产品的画面品质,具有高分辨率、高透过率、低功耗、宽视角、高开口率、低色差、无挤压水波纹(push mura)等优点。 Advanced super dimension conversion technique (ADvanced Super Dimension Switch, referred to as ADS) can be increased a thin film transistor liquid crystal display does not filter (Thin Film Transistor Liquid Crystal Display, referred to as TFT-LCD) products picture quality, high resolution, high transmittance , low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, no pressing ripple (push mura) etc.

[0004] 然而,ADS模式的氧化物TFT阵列基板的制备过程,通常需要7-9道掩膜(mask)工艺,尤其是阵列基板中的TFT就需要5道掩膜工艺,因此制作工艺复杂,生产效率较低,成本较高。 [0004] However, the preparation of the oxide TFT array substrate ADS mode, usually 7-9-mask (mask) process, in particular the array substrate in a TFT requires five mask process, so the production process is complicated, low productivity, high cost.

发明内容 SUMMARY

[0005] 本发明的实施例提供一种阵列基板、薄膜晶体管及制作方法、显示装置,用以解决现有技术中薄膜晶体管、阵列基板制作工艺复杂、生产效率较低、成本较高等技术问题,该阵列基板的结构简单,制作工艺较少,从而生产效率高,成本较低。 Example [0005] The present invention provides an array substrate, a thin film transistor and a manufacturing method, a display device for solving the prior art thin film transistor array substrate fabrication process complexity, low efficiency, high cost and other technical problems, simple structure of the array substrate, less production process, whereby high productivity and low cost.

[0006] 为达到上述目的,本发明的实施例采用如下技术方案: [0006] To achieve the above object, embodiments of the present invention adopts the following technical solutions:

[0007] 一种阵列基板,包括: [0007] An array substrate, comprising:

[0008] 基板; [0008] a substrate;

[0009] 在所述基板上同层设置的有源层、源电极、漏电极、像素电极; An active layer, a source electrode [0009] the same layer disposed on the substrate, the drain electrode, a pixel electrode;

[0010] 位于所述有源层上的栅极绝缘层; [0010] positioned a gate insulating layer on the active layer;

[0011] 位于所述栅极绝缘层上的栅极; [0011] a gate on the gate insulating layer;

[0012] 所述有源层、源电极、漏电极、像素电极、栅极绝缘层和栅极通过一次构图工艺形成,所述源电极通过所述有源层与所述漏电极连接。 [0012] the active layer, a source electrode, a drain electrode, a pixel electrode, a gate insulating layer and a gate electrode through one patterning process for forming the source electrode through the active layer, the drain and the electrode connection.

[0013] 上述方案优选的是,所述阵列基板还包括: [0013] The scheme is preferred that the array substrate further comprises:

[0014] 位于所述像素电极、源电极、漏电极、栅极上的层间介质(Inter Level Dielectric,简称ILD),所述层间介质包括对应所述源电极的过孔; [0014] positioned to the pixel electrode, a source electrode, a drain electrode, an interlayer dielectric on the gate electrode (Inter Level Dielectric, referred to as the ILD), said interlayer dielectric comprises a through hole corresponding to the source electrode;

[0015] 位于所述层间介质上的数据线,所述数据线通过所述过孔与所述源电极连接。 [0015] positioned in the inter-layer data line on the media, the data line through the via hole to the source electrode.

[0016] 上述任一方案优选的是,所述阵列基板还包括: [0016] The preceding embodiment is preferred that the array substrate further comprises:

[0017] 位于所述数据线和所述层间介质上的钝化层(passivation,简称PVX); [0017] positioned between said data lines and said layer is a passivation layer on the medium (passivation, referred to as PVX);

[0018] 位于所述钝化层上的公共电极。 [0018] positioned in the common electrode on the passivation layer.

[0019] 上述任一方案优选的是,所述阵列基板还包括:位于所述钝化层上的有机树脂层, 所述公共电极位于所述有机树脂层上。 [0019] The preceding embodiment is preferred that the array substrate further comprising: an organic resin layer on the passivation layer, the common electrode located on the organic resin layer.

[0020] 一种阵列基板的制作方法,包括以下步骤: Production Method [0020] An array substrate, comprising the steps of:

[0021] 在基板上依次层叠制作半导体金属氧化物薄膜、栅极绝缘薄膜、栅极薄膜; [0021] are sequentially laminated fabricating a semiconductor metal oxide thin film, a gate insulating film, a gate electrode film on the substrate;

[0022] 通过一次构图工艺,将所述半导体金属氧化物薄膜形成包含有源层以及位于像素电极区域、源电极区域、漏电极区域的图形,将所述栅极绝缘薄膜形成包含栅极绝缘层的图形,将所述栅极薄膜形成包含栅极的图形;所述源电极通过所述有源层与所述漏电极连接; [0022] through one patterning process, the semiconductive metal oxide thin film is formed comprising a gate insulating layer including an active layer, and a pixel electrode, graphics source electrode region, a drain region, the gate insulating film is formed pattern, the gate electrode film forming a pattern comprising a gate electrode; the source electrode through the active layer and the drain electrode is connected;

[0023] 将所述位于像素电极区域、源电极区域和漏电极区域的图形进行导体化,形成像素电极、源电极和漏电极。 [0023] the located pixel electrode, a source electrode region and a pattern drain electrode region is a conductor, a pixel electrode, a source electrode and a drain electrode.

[0024] 上述方案优选的是,所述形成像素电极、源电极和漏电极之后还包括: [0024] The above-described embodiment is preferable that the pixel electrode, the source electrode and the drain electrode further comprises:

[0025] 制作覆盖所述像素电极、源电极、漏电极、栅极的层间介质薄膜,通过一次构图工艺将所述层间介质薄膜形成包含过孔的层间介质,所述过孔对应所述源电极; [0025] Production cover the pixel electrode, a source electrode, a drain electrode, between the gate of the interlayer dielectric film, through one patterning process to the interlayer dielectric film is formed comprising a through the inter-layer hole medium, the via hole corresponding to the said source electrode;

[0026] 制作覆盖所述过孔的数据线薄膜,通过一次构图工艺将所述数据线薄膜形成包含数据线的图形,所述数据线通过所述过孔与所述源电极连接。 [0026] Production cover the data line of the through hole of the film, through one patterning process to the data line film-forming pattern comprising a data line, the data line through the via hole to the source electrode.

[0027] 上述任一方案优选的是,所述通过一次构图工艺将所述数据线薄膜形成包含数据线的图形之后还包括: [0027] any of the above embodiment is preferable that after the data line film-forming pattern comprising a data line of the through one patterning process further comprises:

[0028] 制作覆盖所述数据线和所述层间介质的钝化层薄膜,通过一次构图工艺将所述钝化层薄膜形成钝化层; [0028] Production cover between said data lines and said layer of passivation layer medium, and the passivation layer forming a passivation layer is formed by one patterning process to the;

[0029] 在所述钝化层上制作公共电极薄膜,通过一次构图工艺将所述公共电极薄膜形成包含公共电极的图形。 [0029] Production common electrode film on the passivation layer, forming a pattern comprising a common electrode through one patterning process to the common electrode film.

[0030] 上述任一方案优选的是,所述通过一次构图工艺将所述钝化层薄膜形成钝化层包括: [0030] The preceding embodiment is preferred that the through one patterning process the layer thin-film passivation forming a passivation layer comprising:

[0031] 制作覆盖所述钝化层薄膜的有机树脂薄膜; [0031] Production covering the organic resin film of the passivation layer film;

[0032] 将所述有机树脂薄膜在钝化层区域的有机树脂保留,其他区域的有机树脂去除, 形成有机树脂层; [0032] The organic resin film in an organic resin passivation layer region retained, the organic resin other regions is removed, the organic resin layer is formed;

[0033] 将暴露出的钝化层薄膜去除,形成钝化层; [0033] The exposed passivation layer is removed, forming a passivation layer;

[0034] 所述在所述钝化层上制作公共电极薄膜具体为:在所述有机树脂层上制作公共电极薄膜。 [0034] The production of the common electrode film in particular on the passivation layer: create a common electrode film on said organic resin layer.

[0035] 上述任一方案优选的是,在所述通过一次构图工艺将所述公共电极薄膜形成包含公共电极的图形之后,对阵列基板进行退火处理,所述退火温度为200°C _250°C。 [0035] The preceding embodiment is preferred that, after a patterning process to the common electrode film is formed pattern comprising a common electrode of the pass and the array substrate is annealed, said annealing temperature is 200 ° C _250 ° C .

[0036] 上述任一方案优选的是,所述通过一次构图工艺,将所述半导体金属氧化物薄膜形成包含有源层以及位于像素电极区域、源电极区域、漏电极区域的图形,将所述栅极绝缘薄膜形成包含栅极绝缘层的图形,将所述栅极薄膜形成包含栅极的图形,包括以下步骤: [0036] The preceding embodiment is preferred that the through one patterning process, the semiconductive metal oxide thin film is formed comprising an active layer, and a pixel electrode, graphics source electrode region, a drain region, the the gate insulating film forming a pattern comprising the gate insulating layer, the gate electrode film forming a pattern comprising a gate electrode, comprising the steps of:

[0037] 在所述栅极薄膜上涂覆光刻胶;通过半色调掩膜板对光刻胶进行一次曝光、显影, 使得光刻胶形成半保留光刻胶区域、全保留光刻胶区域和全去除光刻胶区域,所述半保留光刻胶区域包括源电极区域、漏电极区域和像素电极区域,所述全保留光刻胶区域包括栅极区域,除半保留光刻胶区域、全保留光刻胶区域之外的区域为全去除光刻胶区域; [0037] applying a photoresist on the gate electrode film; the photoresist once exposed to light through a halftone mask, developed, so that photoresist forms a semi-retained regions of the photoresist, the whole retained photoresist region and full removal of the resist region, the half-retained regions of the photoresist includes a source electrode region, the drain region and the pixel electrode region, the full retention photoresist region including a gate region, in addition to semi-retained regions of the photoresist, full retention outside regions of the photoresist region is fully removed regions of the photoresist;

[0038] 刻蚀掉全去除光刻胶区域对应的栅极薄膜、栅极绝缘薄膜和半导体金属氧化物薄膜; [0038] etched off full removal of the gate film of the photoresist region corresponding to the gate insulating film and a semiconductor metal oxide thin film;

[0039] 通过第一次灰化工艺,去除半保留光刻胶区域的光刻胶,且去除全保留光刻胶区域的部分光刻胶; [0039] By the first ashing process to remove partially-retained regions of the photoresist of the photoresist, and removing portions of the photoresist full retention photoresist region;

[0040] 刻蚀掉所述半保留光刻胶区域对应的栅极薄膜和栅极绝缘薄膜,以便由所述栅极薄膜形成包含栅极的图形,由所述栅极绝缘薄膜形成包含栅极绝缘层的图形; [0040] etching away the half-retained photoresist region corresponding to the gate electrode film and the gate insulating film, so as to pattern comprising a gate electrode is formed by the gate electrode film is formed comprising a gate of said gate insulating film pattern of the insulating layer;

[0041] 通过光刻胶剥离工艺,去除所述全保留光刻胶区域的光刻胶。 [0041] by a photoresist stripping process, removing said full retention photoresist resist region.

[0042] 上述任一方案优选的是,所述半导体金属氧化物薄膜是IGZO(Indium Gallium Zinc Oxide,铟镓锌氧化物)薄膜。 [0042] any of the above embodiment is preferable that the semiconductor metal oxide thin film is IGZO (Indium Gallium Zinc Oxide, Indium Gallium Zinc Oxide) film.

[0043] 上述任一方案优选的是,所述层间介质薄膜的材料包含SiNx。 [0043] The preceding embodiment is preferred that the interlayer material of the dielectric thin film comprises SiNx.

[0044] -种薄膜晶体管,包括: [0044] - thin-film transistor, comprising:

[0045] 基板; [0045] a substrate;

[0046] 在所述基板上同层设置的有源层、源电极、漏电极; An active layer, a source electrode [0046] The same layer disposed on the substrate, a drain electrode;

[0047] 位于所述有源层上的栅极绝缘层; [0047] positioned a gate insulating layer on the active layer;

[0048] 位于所述栅极绝缘层上的栅极; [0048] a gate on the gate insulating layer;

[0049] 所述有源层、源电极、漏电极、栅极绝缘层和栅极通过一次构图工艺形成,所述源电极通过所述有源层与所述漏电极连接。 [0049] the active layer, a source electrode, a drain electrode, a gate insulating layer and a gate electrode through one patterning process for forming the source electrode through the active layer, the drain and the electrode connection.

[0050] 一种薄膜晶体管的制作方法,包括以下步骤: [0050] A method of making a thin film transistor, comprising the steps of:

[0051] 在基板上依次层叠制作半导体金属氧化物薄膜、栅极绝缘薄膜、栅极薄膜; [0051] are sequentially laminated fabricating a semiconductor metal oxide thin film, a gate insulating film, a gate electrode film on the substrate;

[0052] 通过一次构图工艺,将所述半导体金属氧化物薄膜形成包含有源层以及位于源电极区域、漏电极区域的图形,将所述栅极绝缘薄膜形成包含栅极绝缘层的图形,将所述栅极薄膜形成包含栅极的图形;所述源电极通过所述有源层与所述漏电极连接; [0052] through one patterning process, the semiconductive metal oxide thin film formed pattern comprising an active layer, and a source electrode region, a drain region, the gate insulating film forming a pattern comprising the gate insulating layer, and the gate electrode film forming a pattern comprising a gate electrode; the source electrode through the active layer, a drain of said electrode connection;

[0053] 将所述位于源电极区域和漏电极区域的图形进行导体化,形成源电极和漏电极。 [0053] The pattern of the located on the source electrode region and the drain region is a conductor, a source electrode and a drain electrode.

[0054] 一种包含上述任一方案所述的阵列基板的显示装置。 [0054] A display device array substrate of any preceding embodiment said inclusion.

[0055] 本发明实施例提供的阵列基板,有源层、源电极、漏电极、像素电极设置在同一层, 栅极绝缘层位于有源层上,栅极位于栅极绝缘层上,简化了现有技术的阵列基板的结构,方便了有源层、源电极、漏电极、像素电极、栅极绝缘层和栅极通过一次构图工艺形成,且有源层、源电极、漏电极、像素电极、栅极绝缘层和栅极通过一次构图工艺形成,减少了阵列基板的掩膜工艺,缩短了阵列基板的制造时间,提高了阵列基板的制造效率,降低了阵列基板的生产成本。 [0055] The array substrate according to an embodiment of the present invention, the active layer, a source electrode, a drain electrode, a pixel electrode disposed in the same layer, a gate insulating layer on the active layer, a gate electrode located on the gate insulating layer, simplifying the structure of the array substrate of the prior art, facilitates active layer, a source electrode, a drain electrode, a pixel electrode, a gate insulating layer and a gate electrode formed through one patterning process, and the active layer, a source electrode, a drain electrode, a pixel electrode , a gate insulating layer and a gate electrode through one patterning process for forming the reduced mask process of the array substrate, shortens the manufacturing time of the array substrate and improve the manufacturing efficiency of the array substrate, reduces the production cost of the array substrate.

附图说明 BRIEF DESCRIPTION

[0056] 图1为本发明一实施例中的阵列基板的截面不意图。 [0056] FIG. 1 is not intended cross section of the array substrate in an embodiment of the present invention.

[0057] 图2为本发明另一实施例中的阵列基板的截面示意图。 [0057] FIG. 2 is a schematic cross section of an array substrate according to another embodiment of the present invention.

[0058] 图3为本发明另一实施例中的阵列基板的截面示意图。 [0058] FIG. 3 is a schematic cross section of an array substrate according to another embodiment of the present invention.

[0059] 图4为本发明另一实施例中的阵列基板的截面示意图。 [0059] FIG. 4 is a schematic cross section of an array substrate according to another embodiment of the present invention.

[0060] 图5为本发明一实施例中的在基板上依次层叠制作半导体金属氧化物薄膜、栅极绝缘薄膜、栅极薄膜后的截面示意图。 [0060] FIG. 5 semiconductive metal oxide thin film, a gate insulating film, and a cross-sectional schematic view of the gate electrode film embodiment on a substrate sequentially stacked produced an embodiment of the present invention.

[0061] 图6为本发明一实施例中的通过一次构图工艺,形成像素电极区域、源电极区域、 漏电极区域、栅极绝缘层和栅极的图形过程中涂覆掩膜光刻胶后的截面示意图。 After the source electrode region, a drain region, a gate insulating layer and the gate pattern during coating mask photoresist example by a patterning process of an embodiment, the pixel electrode regions [0061] FIG. 6 of the present invention, the schematic sectional view.

[0062] 图7为本发明一实施例中的通过一次构图工艺,形成像素电极区域、源电极区域、 漏电极区域、栅极绝缘层和栅极的图形过程中,刻蚀掉全去除光刻胶区域对应的栅极薄膜、 栅极绝缘薄膜和半导体金属氧化物薄膜后的截面示意图。 [0062] FIG. 7 is an embodiment by a patterning process to form a pixel electrode, a source electrode region, a drain region, a gate insulating layer and a pattern during the gate, the etching away the whole removal lithography invention gate thin film plastic region corresponding to the cross section of the gate insulating film and a semiconductor metal oxide thin film FIG.

[0063] 图8为本发明一实施例中的通过一次构图工艺,形成像素电极区域、源电极区域、 漏电极区域、栅极绝缘层和栅极的图形过程中,通过第一次灰化工艺,去除半保留光刻胶区域的光刻胶,且去除全保留光刻胶区域的部分光刻胶后的截面示意图。 [0063] FIG. 8 patterning process embodiment by forming the pixel electrode region, a source electrode region, a drain region, a gate insulating layer and the gate pattern course, by first ashing process an embodiment of the present invention. , cross-sectional view after removal of partially-retained photoresist regions of the photoresist, and removing portions of the photoresist full retention photoresist region.

[0064] 图9-1为本发明一实施例中的通过一次构图工艺,形成像素电极区域、源电极区域、漏电极区域、栅极绝缘层和栅极的图形过程中,刻蚀掉半保留光刻胶区域对应的栅极薄膜和栅极绝缘薄膜后的截面示意图。 Example by a patterning process to form a pixel electrode, a source electrode region, a drain region, a gate insulating layer and a pattern during the gate, the etching away semiconservative an embodiment [0064] FIG. 9-1 of the present invention gate electrode film and a cross-sectional schematic view of the gate insulating film of the photoresist corresponding to the area.

[0065] 图9-2为本发明一实施例中的通过一次构图工艺,形成像素电极区域、源电极区域、漏电极区域、栅极绝缘层和栅极的图形过程中,刻蚀掉半保留光刻胶区域对应的栅极薄膜和栅极绝缘薄膜后,进行导体化的截面示意图。 [0065] Figure 9-2 of the present invention an embodiment by a patterning process to form a pixel electrode, the source electrode region, a drain region, a gate insulating layer and the gate of the graphics process, etching away half reserved after the photoresist region corresponding to the gate electrode film and the gate insulating film, a schematic cross section of a conductor is performed.

[0066] 图10为本发明一实施例中的阵列基板的制作方法流程示意图。 [0066] FIG. 10 production flowchart of a method of the array substrate in an embodiment of the present invention.

[0067] 图11为本发明一实施例中的阵列基板的制作方法部分流程示意图。 [0067] Figure 11 partially schematic flow chart of manufacturing method of an array substrate according to the one embodiment of the present invention.

[0068] 图12为本发明一实施例中的阵列基板的制作方法部分流程示意图。 [0068] FIG. 12 is partially schematic flow chart of manufacturing method of an array substrate according to the one embodiment of the present invention.

[0069] 图13为本发明一实施例中的阵列基板的制作方法中,将钝化层薄膜形成钝化层的流程示意图。 [0069] FIG 13 a schematic flowchart of method for manufacturing the array substrate of the embodiment, the passivation layer is a thin film forming a passivation layer to an embodiment of the present invention.

[0070] 图14为本发明一实施例中的阵列基板的制作方法部分流程示意图。 [0070] Figure 14 partially schematic flow diagram of method for manufacturing the array substrate of the embodiment in an embodiment of the present invention.

[0071] 附图标记:1-基板,2-有源层,3-源电极,4-漏电极,5-像素电极,6-栅极绝缘层,7-栅极,8-层间介质,9-过孔,10-数据线,11-钝化层,12-有机树脂层,13-公共电极, 14-半导体金属氧化物薄膜,15-栅极绝缘薄膜,16-栅极薄膜,17-光刻胶,18-全保留光刻胶区域,19-半保留光刻胶区域,20-全去除光刻胶区域。 [0071] The reference numerals: Room 1- substrate, 2 an active layer, 3 a source electrode, 4 a drain electrode, 5- pixel electrode 6 a gate insulating layer, 7 a gate, 8-layer medium, 9- vias, 10 data cable, 11 a passivation layer, 12 an organic resin layer, 13 a common electrode, 14 a semiconductor metal oxide thin film, 15 gate insulating film, 16 gate electrode film, 17 photoresist 18 full retention regions of the photoresist, 19- half retained photoresist region 20 wholly removed regions of the photoresist.

具体实施方式 Detailed ways

[0072] 下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。 [0072] below in conjunction with the present invention in the accompanying drawings, technical solutions of embodiments of the present invention are clearly and completely described, obviously, the described embodiments are merely part of embodiments of the present invention, but not all embodiments example. 基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。 Based on the embodiments of the present invention, those of ordinary skill in the art without All other embodiments of the inventive effort shall fall within the scope of the present invention.

[0073] 众所周知,薄膜晶体管(TFT)包括:栅极、源电极和漏电极。 [0073] It is well known thin-film transistor (TFT) comprising: a gate, source and drain electrodes. 通常来讲,TFT的源电极和漏电极可以视为等同的;即除TFT中除栅极以外的两极中,可以将其中任一个称为源电极、另一极称为漏电极。 Generally, TFT source and drain electrodes can be regarded as equivalent; i.e. except the TFT poles other than the gate may be either a called the source electrode and the other electrode is called a drain electrode. 具体的,在本发明实施例中为了避免称谓所导致的混淆,将TFT 与数据线电性连接一极称为源电极、将TFT与像素电极电性连接的一极称为漏电极。 Specifically, in the embodiment of the present invention to avoid obscuring the title caused, the TFT and the data line is electrically connected to an electrode called a source electrode of the TFT and the pixel electrode is electrically connected to a pole called the drain electrode. 当然, 若是将TFT与数据线电性连接一极称为漏电极,将TFT与像素电极电性连接的一极称为源电极,也是可以的。 Of course, if the TFT and the data line is electrically connected to a pole called the drain electrode, and an electrode called a source electrode of the TFT and the pixel electrode is electrically connected, are also possible.

[0074] 本发明一实施例中提供一种阵列基板,如图1所示,包括:基板1 ;在基板1上同层设置的有源层2、源电极3、漏电极4、像素电极5 ;位于所述有源层上的栅极绝缘层6 ;位于所述栅极绝缘层上的栅极7 ;所述有源层2、源电极3、漏电极4、像素电极5、栅极绝缘层6和栅极7通过一次构图工艺形成,所述源电极3通过所述有源层2与所述漏电极4连接。 [0074] The embodiments provide an array substrate, an embodiment of the present invention, shown in Figure 1, comprises: a substrate 1; an active layer with the layer provided on the substrate 12, the source electrode 3 and drain electrode 4, the pixel electrode 5 ; located in the gate insulating layer on the active layer 6; a of the gate electrode on the gate insulating layer 7; the active layer 2, source electrode 3, the drain electrode 4, the pixel electrode 5, a gate insulating layer 6 and gate electrode 7 is formed through one patterning process, the source electrode 3 through the active layer 2 and the drain electrode 4 is connected.

[0075] 本发明实施例中,如图1所示,源电极3通过有源层2与漏电极4连接,漏电极4 与像素电极5连接。 [0075] The embodiments of the present invention, as shown, source electrode 3 is connected through the active layer 2 and the drain electrode 41, the drain electrode 4 connected to the pixel electrode 5. 这些是基于本发明实施例的精神进行的略微改变,均应落入本发明的保护范围。 These are based on the embodiment of the invention in a spirit of slightly altered, shall fall within the invention scope of protection.

[0076] 本发明实施例提供的阵列基板中,有源层、源电极、漏电极、像素电极设置在同一层,栅极绝缘层位于有源层上,栅极位于栅极绝缘层上,简化了现有技术的阵列基板的结构,方便了有源层、源电极、漏电极、像素电极、栅极绝缘层和栅极通过一次构图工艺形成, 且有源层、源电极、漏电极、像素电极、栅极绝缘层和栅极通过一次构图工艺形成,减少了阵列基板的掩膜工艺次数,缩短了阵列基板的制作时间,提高了阵列基板的制作效率,降低了阵列基板的生产成本。 [0076] The array substrate according to an embodiment of the present invention, the active layer, a source electrode, a drain electrode, a pixel electrode disposed in the same layer, a gate insulating layer on the active layer, a gate electrode located on the gate insulating layer, simplification the structure of the array substrate of the prior art, facilitates active layer, a source electrode, a drain electrode, a pixel electrode, a gate insulating layer and a gate electrode formed through one patterning process, and the active layer, a source electrode, a drain electrode, a pixel electrode, the gate insulating layer and a gate electrode through one patterning process is formed, it reduces the number of mask process of the array substrate, reducing the production time of the array substrate and improve the production efficiency of the array substrate, reduces the production cost of the array substrate.

[0077] 需要说明的是,对于阵列基板而言,一般还需设置数据线。 [0077] Incidentally, for the array substrate, generally also set the data line. 对于本实施例而言较佳地,如图2所示的阵列基板还包括:位于像素电极5、源电极3、漏电极4、栅极7上的层间介质(Inter Level Dielectric,简称ILD)8,层间介质8包括对应所述源电极3的过孔9;位于层间介质8上的数据线10,数据线10通过过孔9与源电极3连接。 For the present embodiment in terms of the preferred, the array substrate shown in FIG. 2, further comprising: a pixel electrode 5, the source electrode 3 and drain electrode 4, an interlayer dielectric on the gate electrode 7 (Inter Level Dielectric, referred to as ILD) 8, 8 comprise corresponding to the source electrode via hole 3 of 9 inter-layer dielectric; located interlayer dielectric data lines 8, 10, the data line 10 through the via connected to the source electrode 3 hole 9. 数据线采取该方法设置可以方便前期制作的源电极、漏电极、像素电极进行进一步处理(如导体化处理)。 Data lines to take the method of setting the source electrode can be easily pre-production, the drain electrode, the pixel electrode is further processed (e.g., a conductor processing). 实际运用过程中,也可以将数据线与源电极进行同层设置。 The actual application process, may be data line and the source electrode in the same layer. 数据线的材质可以为铝、铜或其他导电性能较好的金属材质。 Material data line may be aluminum, copper or other conductive properties preferably metal.

[0078] 层间介质8是一种绝缘结构,可以使像素电极5、源电极3、漏电极4、栅极7与其他部分进行绝缘。 [0078] The interlayer dielectric 8 is an insulating structure, the pixel electrode 5, the source electrode 3 and drain electrode 4, a gate 7 is insulated from other portions. 层间介质8的厚度可以是5000 A -6000 A,层间介质8的具体材料可以是SiNx、SiON或者SiO2的单层薄膜,或者是硅的氮化物(SiNx)和二氧化硅(Si02)的复合薄膜(即是硅的氮化物薄膜和二氧化硅薄膜构成的复合薄膜),或者二氧化硅和氮氧化硅(SiON)的复合薄膜(即是二氧化硅薄膜和氮氧化硅薄膜构成的复合薄膜),或者二氧化硅、 氮氧化硅和硅的氮化物的复合薄膜(即是二氧化硅薄膜、氮氧化硅薄膜和硅的氮化物薄膜构成的复合薄膜)。 The interlayer dielectric 8 have a thickness of 5000 A -6000 A, the particular materials of the interlayer dielectric 8 may be SiNx, SiON or SiO2 single layer film, or a silicon nitride (SiNx) and silicon dioxide (Si02) of the composite film (i.e., a composite thin nitride films of silicon and silicon dioxide thin film) or silicon dioxide and silicon oxynitride (SiON) composite film (i.e., a composite silicon dioxide film and silicon oxynitride film composed of film), or silicon dioxide, silicon oxynitride and silicon nitride composite films (ie silicon dioxide film, silicon oxynitride film and silicon nitride film made of composite film).

[0079] 过孔9的横截面可以是V型、T型或U型结构或其他具有相同作用的结构。 Cross section [0079] through hole 9 may be a V-type, T-type or U-shaped structure or other structure having the same effect. 图2所示的是V型结构。 V-shaped configuration shown in FIG.

[0080] 为了保护源电极、漏电极、像素电极、栅极、数据线等,避免它们受到氧化腐蚀作用,如图3、4所示的阵列基板还包括:位于数据线10和层间介质8上的钝化层11 ;位于钝化层11上的公共电极13。 [0080] In order to protect the source electrode, the drain electrode, the pixel electrodes, gate lines, data lines, to prevent them from oxidation corrosion, the array substrate shown in FIG. 3 and 4 in FIG further comprising: a property in the data line 10 and the interlayer dielectric 8 the passivation layer 11 is on; a common electrode 13 on 11 the passivation layer.

[0081] 钝化层11可以为二氧化硅单层薄膜,或者二氧化硅和氮氧化硅的复合薄膜,钝化层的厚度可以是2000 A -3000 A;公共电极13的厚度可以为400A-700A。 [0081] The passivation layer 11 may be a silicon dioxide monolayer film, or silica, and the thickness of the composite film silicon oxynitride passivation layer may be 2000 A -3000 A; thickness of the common electrode 13 may be 400A- 700A.

[0082] 另一优选实施例中,所述阵列基板还包括:位于钝化层11上的有机树脂层12,公共电极13位于有机树脂层12上,如图4所示。 [0082] another preferred embodiment, the array substrate further comprising: a organic resin layer 11 on the passivation layer 12, common electrode 13, the organic resin layer is 12, as shown in FIG. 有机树脂层的设置,可以降低公共电极和数据线之间的寄生电容,从而降低阵列基板的功耗,也可以使阵列基板的表面平板化。 Providing an organic resin layer, can reduce the parasitic capacitance between the common electrode and the data line, thereby reducing the power consumption of the array substrate may be the surface of the array substrate of the flat-panel.

[0083] 本发明另一实施例中,如图10所示的阵列基板的制作方法,包括以下步骤: [0083] Another embodiment of the present invention, a method of manufacturing the array substrate shown in Figure 10, comprising the steps of:

[0084] S101、在基板上依次层叠制作半导体金属氧化物薄膜14、栅极绝缘薄膜15、栅极薄膜16。 [0084] S101, on the substrate are sequentially stacked fabricating a semiconductor metal oxide thin film 14, the gate insulating film 15, gate electrode film 16.

[0085] 如图5所示的在基板上依次层叠制作半导体金属氧化物薄膜、栅极绝缘薄膜、栅极薄膜后的截面示意图。 [0085] Figure 5 in the substrate are stacked fabrication of semiconductor metal oxide film, a gate insulating film, a gate film after cross-sectional schematic. 在基板上制作半导体金属氧化物薄膜,可以使用溅射方法沉积成膜,金属氧化物薄膜的材料可以是IGZO(Indium Gallium ZincOxide,铟镓锌氧化物)或ΙΤΖ0(铟锡锌氧化物),半导体金属氧化物薄膜的厚度一般为400A-500A。 Fabricating a semiconductor metal oxide thin film on a substrate, a sputtering method of depositing a film formation material of the metal oxide thin film may be IGZO (Indium Gallium ZincOxide, indium gallium zinc oxide) or ΙΤΖ0 (indium tin zinc oxide), semiconductors the thickness of the metal oxide thin film is typically 400A-500A.

[0086] 制作栅极绝缘薄膜时,是在形成有金属氧化物薄膜的基板上制作的。 [0086] When making the gate insulating film, it is formed fabricated on a substrate a metal oxide thin film. 制作方法可以为PECVD(等离子体增强化学气相沉积法),栅极绝缘薄膜层的总厚度可以为2000Α-4000Α,栅极绝缘薄膜可以是单层的二氧化硅薄膜,也可以是硅的氮化物和二氧化硅的复合薄膜(即是硅的氮化物薄膜和二氧化硅薄膜构成的复合薄膜),或者是硅的氮化物、氮氧化硅和二氧化硅的复合薄膜。 Manufacturing method may be a PECVD (plasma enhanced chemical vapor deposition), the total thickness of the gate insulating film layer may be 2000Α-4000Α, a gate insulating film may be a single layer of silicon oxide film may be silicon nitride and silica composite film (i.e., a composite thin nitride films of silicon and silicon dioxide thin film) or a composite film of silicon nitride, silicon oxynitride and silicon dioxide. 若栅极绝缘薄膜层是硅的氮化物和二氧化硅的复合薄膜,或硅的氮化物、氮氧化硅和二氧化硅的复合薄膜,优选的是,将二氧化硅薄膜与半导体金属氧化物薄膜接触,应避免硅的氮化物薄膜或氮氧化硅薄膜直接与半导体金属氧化物薄膜接触,这是因为硅的氮化物薄膜或氮氧化硅薄膜与半导体金属氧化物薄膜接触时, 尤其是与IGZO薄膜接触时,硅的氮化物薄膜或氮氧化硅薄膜中的氢(H)会对半导体金属氧化物薄膜进行导体化,从而影响了半导体金属氧化物薄膜的特性。 If the gate insulating film layer is a composite film of nitride and silica-silicon, or silicon nitride, a composite film silicon oxynitride and silicon dioxide, it is preferable that the silicon oxide film and the semiconductor metal oxide contacting the film, to avoid a silicon nitride film or a silicon oxynitride film in direct contact with the semiconductor metal oxide thin film, since the contact film or a silicon oxynitride film and a semiconductive metal oxide thin film of silicon nitride, in particular with IGZO contacting the film, the silicon nitride film or a silicon oxynitride film of hydrogen (H) would semiconducting metal oxide thin film conductor, thereby affecting the semiconductor metal oxide thin film properties.

[0087] 制作栅极薄膜时,是在形成有栅极绝缘薄膜的基板上制作的。 [0087] When making the gate film, it is fabricated on a substrate formed with the gate insulating film. 制作方法可以为溅射沉积,栅极薄膜的材料可以为钼(Μ〇)、铝(Al)等金属,厚度为2000Α-4000Α。 Production methods may be sputter deposited, material of the gate film may be molybdenum (Μ〇), aluminum (Al) metal such thickness 2000Α-4000Α.

[0088] S102、通过一次构图工艺,将半导体金属氧化物薄膜14形成包含有源层以及位于像素电极区域、源电极区域、漏电极区域的图形,将所述栅极绝缘薄膜形成包含栅极绝缘层的图形,将所述栅极薄膜形成包含栅极的图形;所述源电极通过所述有源层与所述漏电极连接。 [0088] S102, through one patterning process, the semiconductor metal oxide thin film 14 is formed a gate insulation comprising an active layer, and a pixel electrode, graphics source electrode region, a drain region, the gate insulating film is formed comprising pattern layer, the gate electrode film forming a pattern comprising a gate electrode; the source electrode is connected through the active layer and the drain.

[0089] 所述通过一次构图工艺,具体包括涂覆光刻胶、曝光、显影、刻蚀等工艺。 [0089] The through one patterning process, including coating a photoresist, exposing, developing and etching processes. 其中,曝光工艺需要使用掩膜板控制光刻胶在不同区域的曝光度。 Wherein an exposure process requires the use of a mask plate to control the exposure of photoresist in different regions. 在阵列基板的整个制作过程中, 通常将使用掩膜板的个数作为构图工艺的次数;也就是说,进行一次构图工艺即为使用一次掩膜板完成构图。 Throughout the production process of the array substrate, typically using the number of mask plate as the number of the patterning process; that is, a patterning process is the use of a mask to complete the patterning. 如图9-1,该方法通过一次构图工艺,形成了有源层、像素电极区域、源电极区域、漏电极区域、栅极绝缘层和栅极图形。 Figure 9-1, the method through one patterning process to form the active layer, a pixel electrode region, a source electrode region, a drain region, a gate insulating layer and a gate electrode pattern.

[0090] S103、将所述位于像素电极区域、源电极区域和漏电极区域的图形进行导体化,形成像素电极、源电极和漏电极。 [0090] S103, the located pixel electrode, a source electrode region and a pattern drain electrode region is a conductor, a pixel electrode, a source electrode and a drain electrode.

[0091] 如图9-2,通过导体化,将像素电极区域、源电极区域、漏电极区域的金属氧化物薄膜分别形成了像素电极、源电极、漏电极。 [0091] Figure 9-2 through a conductor, the pixel electrode, a source electrode region, the metal oxide thin film a drain region are formed of the pixel electrode, the source electrode, the drain electrode. 图9-2中的箭头表示导体化,导体化可以降低数据线与源电极之间的接触电阻,也可以使半导体金属氧化物充当像素电极,同时,因为只对像素电极区域、源电极区域、漏电极区域对应的半导体金属氧化物薄膜进行导体化,所以并不影响有源层对应的半导体金属氧化物薄膜的特性。 Arrows in FIG. 9-2 showing a conductor, a conductor can reduce the contact resistance between the data line and the source electrode may be the semiconductor metal oxide serving as the pixel electrode, while, because only the pixel electrode, a source electrode region, drain region corresponding to the semiconductive metal oxide thin film is a conductor, it does not affect the characteristics of the semiconductor metal oxide thin film of the active layer corresponding to.

[0092] 本发明实施例提供的阵列基板的制作方法中,通过层叠成膜和一次构图工艺及导体化步骤,制得的有源层、源电极、漏电极、像素电极在同一层,栅极绝缘层位于有源层上, 栅极位于栅极绝缘层上,该方法减少了阵列基板的掩膜工艺次数,缩短了阵列基板的制作时间,提高了阵列基板的制作效率,降低了阵列基板的生产成本。 [0092] The manufacturing method of an array substrate provided by the present invention, by laminating a film-forming and patterning process and a conductor step to prepare an active layer, a source electrode, a drain electrode, a pixel electrode in the same layer as the gate insulating layer on the active layer, a gate electrode located on the gate insulating layer, which reduces the number of mask process of the array substrate, reducing the production time of the array substrate and improve the production efficiency of the array substrate, reducing the array substrate Cost of production.

[0093] 较佳地实施例中,如图11所示的阵列基板的制作方法中,所述形成像素电极、源电极和漏电极之后还包括: [0093] Preferably embodiment, as shown in the production method of the array substrate shown in FIG. 11, the pixel electrode, the source electrode and the drain electrode further comprises:

[0094] S201、制作覆盖所述像素电极、源电极、漏电极、栅极的层间介质薄膜,通过一次构图工艺将所述层间介质薄膜形成包含过孔的层间介质,所述过孔对应所述源电极。 [0094] S201, produced covering the pixel electrode, a source electrode, a drain electrode, between the gate of the interlayer dielectric film, through one patterning process to the interlayer dielectric film forming the interlayer dielectric comprises vias, said vias corresponding to the source electrode.

[0095] 层间介质是一种绝缘结构,可以使像素电极、源电极、漏电极、栅极与其他部分进行绝缘。 [0095] The medium is an insulating structure, the pixel electrode, a source electrode, a drain electrode, a gate insulated from other portions of the interlayer. 层间介质的厚度可以是5000/1-6000A,成膜方法可以是PECVD,具体材料可以是硅的氮化物和二氧化硅(Si02)的复合薄膜,或者二氧化硅和氮氧化硅(SiON)的复合薄膜, 或者二氧化硅、氮氧化硅和硅的氮化物的复合薄膜。 The interlayer thickness of the dielectric may be 5000 / 1-6000A, the deposition method may be PECVD, concrete material may be silicon nitride and silicon dioxide (Si02) composite film, or a silicon dioxide, and silicon oxynitride (SiON) the composite film or a composite film of silica, silicon oxynitride and a nitride of silicon.

[0096] 过孔的横截面可以是V型、T型或U型结构或其他具有相同作用的结构。 Cross section [0096] through hole may be a V-type, T-type or U-shaped structure or other structure having the same effect.

[0097] S202、制作覆盖所述过孔的数据线薄膜,通过一次构图工艺将所述数据线薄膜形成包含数据线的图形,所述数据线通过所述过孔与所述源电极连接。 [0097] S202, produced to cover the data line of the through hole of the film, through one patterning process to the data line film-forming pattern comprising a data line, the data line through the via hole to the source electrode.

[0098] 优选的是,如图12所示的阵列基板的制作方法,所述通过一次构图工艺将所述数据线薄膜形成包含数据线的图形之后还包括: [0098] Preferably, the method of manufacturing the array substrate shown in Figure 12, a after passing through one patterning process to the data line film-forming pattern comprising a data line further comprises:

[0099] S301、制作覆盖所述数据线和所述层间介质的钝化层薄膜,通过一次构图工艺将所述钝化层薄膜形成钝化层。 [0099] S301, making cover between said data lines and said layer is a passivation layer of the film medium, through one patterning process of the passivation layer forming a passivation layer.

[0100] 钝化层可以为二氧化硅单层薄膜,或者二氧化硅和氮氧化硅的复合薄膜,钝化层的厚度可以是2000A -3000A,成膜方法可以是PECVD。 [0100] The passivation layer may be a silicon dioxide monolayer film, or silica, and the thickness of the composite film silicon oxynitride passivation layer may be 2000A -3000A, the deposition method may be PECVD. 钝化层可以保护源电极、漏电极、 像素电极、栅极、数据线等,避免它们受到氧化腐蚀作用。 The passivation layer may protect the source electrode, the drain electrode, the pixel electrodes, gate lines, data lines, to prevent them from oxidation corrosion.

[0101] S302、在所述钝化层上制作公共电极薄膜,通过一次构图工艺将所述公共电极薄膜形成包含公共电极的图形。 [0101] S302, making the common electrode film on the passivation layer, forming a pattern comprising a common electrode through one patterning process to the common electrode film. 公共电极的厚度可以为400A-700A,成膜方法可以是磁控溅射法。 The thickness of the common electrode may 400A-700A, the deposition method may be a magnetron sputtering method.

[0102] 如图13所示,所述通过一次构图工艺将所述钝化层薄膜形成钝化层包括: [0102] 13, the through one patterning process of the passivation layer forming a passivation layer comprising:

[0103] S401、制作覆盖所述钝化层薄膜的有机树脂薄膜。 [0103] The organic resin film S401, prepared covering the passivation layer film.

[0104] S402、将所述有机树脂薄膜在钝化层区域的有机树脂保留,其他区域的有机树脂去除,形成有机树脂层。 [0104] S402, the organic resin film remain in the organic resin passivation layer region, the organic resin other regions is removed, the organic resin layer is formed. 有机树脂层的设置,可以降低公共电极和数据线之间的寄生电容, 从而降低阵列基板的功耗,也可以使阵列基板的表面平板化。 Providing an organic resin layer, can reduce the parasitic capacitance between the common electrode and the data line, thereby reducing the power consumption of the array substrate may be the surface of the array substrate of the flat-panel.

[0105] S403、将暴露出的钝化层薄膜去除,形成钝化层。 [0105] S403, the exposed passivation layer is removed, forming a passivation layer.

[0106] S404、所述在所述钝化层上制作公共电极薄膜具体为:在所述有机树脂层上制作公共电极薄膜。 [0106] S404, the production of the common electrode film in particular on the passivation layer: create a common electrode film on said organic resin layer.

[0107] 该步骤,通过一次构图工艺形成了钝化层和有机树脂层,制作工艺简便,生产成本较低。 [0107] The step of forming a passivation layer and an organic resin layer is formed by one patterning process, the production process is simple, low production cost.

[0108] 优选的实施例中,在所述通过一次构图工艺将所述公共电极薄膜形成包含公共电极的图形之后,对阵列基板进行退火处理,所述退火温度为200°C _250°C。 [0108] preferred embodiment, after a patterning process to the common electrode film is formed pattern comprising a common electrode of the pass and the array substrate is annealed, said annealing temperature is 200 ° C _250 ° C. 退火处理是为了提高氧化物阵列基板的稳定性,同时降低像素电极的电阻率;退火处理的温度不应高于有机树脂层的后烘温度,避免对有机树脂层造成影响。 Annealing treatment is to improve the stability of the oxide of the array substrate, while reducing the resistivity of the pixel electrode; temperature of the annealing process should not exceed the baking temperature of the organic resin layer, to avoid the impact on the organic resin layer.

[0109] 本发明另一实施例中,如图1、6、7、8、9-1、9-2、14所示,所述通过一次构图工艺, 将所述半导体金属氧化物薄膜形成包含有源层以及位于像素电极区域、源电极区域、漏电极区域的图形,将所述栅极绝缘薄膜形成包含栅极绝缘层的图形,将所述栅极薄膜形成包含栅极的图形,包括以下步骤: [0109] Another embodiment of the present invention, FIG 1,6,7,8,9-1,9-2,14 shown, the through one patterning process, the semiconductive metal oxide thin film is formed comprising an active layer, and a pixel electrode, graphics source electrode region, a drain region, the gate insulating film forming a pattern comprising the gate insulating layer, the gate electrode film forming a pattern comprising a gate electrode, comprising step:

[0110] S501、在所述栅极薄膜上涂覆光刻胶17 ;通过半色调掩膜板对光刻胶17进行一次曝光、显影,使得光刻胶形成半保留光刻胶区域19、全保留光刻胶区域18和全去除光刻胶区域20,半保留光刻胶区域19包括源电极区域、漏电极区域和像素电极区域,全保留光刻胶区域18包括栅极区域,除半保留光刻胶区域、全保留光刻胶区域之外的区域为全去除光刻胶区域20。 [0110] S501, on the gate film-coated photoresist 17; once exposing the photoresist 17 through a half tone mask, developed, so that photoresist forms a semi-retained regions of the photoresist 19, the whole retention regions of the photoresist 18 and the full removal of the resist region 20, a semi-retained photoresist region 19 includes a source electrode region, the drain region and the pixel electrode region, the full retention of the photoresist region 18 includes a gate region, in addition to semiconservative regions of the photoresist, the whole retained outside the regions of the photoresist region is fully removed regions of the photoresist 20.

[0111] S502、刻蚀掉全去除光刻胶区域20对应的栅极薄膜、栅极绝缘薄膜和半导体金属氧化物薄膜。 [0111] S502, etch away the full removal of the gate film 20 corresponding to regions of the photoresist, the gate insulating film and a semiconductor metal oxide thin film.

[0112] 刻蚀掉全去除光刻胶区域20对应的栅极薄膜可以使用SF6和02的混合气或者C12和02的混合气进行干法刻蚀,刻蚀掉全去除光刻胶区域20对应的栅极绝缘薄膜可以使用CF4和02的混合气进行干法刻蚀,刻蚀掉全去除光刻胶区域20对应的半导体金属氧化物薄膜可以利用湿法刻蚀。 [0112] to etch away the full removal of the gate film 20 corresponding to regions of the photoresist may be used SF6 mixed gas 02 or a mixed gas of C12 and 02 by dry etching, to etch away the full removal of the resist region 20 corresponds to a gate insulating film may be used CF4 and mixed gas 02 by dry etching, to etch away the whole removing the photoresist corresponding to the area 20 of the semiconductor metal oxide film may be wet etching.

[0113] S503、通过第一次灰化工艺,去除半保留光刻胶区域19的光刻胶,且去除全保留光刻胶区域18的部分光刻胶。 [0113] S503, by the first ashing process to remove partially-retained photoresist resist region 19, and removing portions of the photoresist full retention of the photoresist region 18.

[0114] S504、刻蚀掉半保留光刻胶区域19对应的栅极薄膜和栅极绝缘薄膜,以便由所述栅极薄膜形成包含栅极的图形,由所述栅极绝缘薄膜形成包含栅极绝缘层的图形。 [0114] S504, etching away the gate electrode film and the gate insulating film half reserved regions of the photoresist 19 corresponding to form a pattern comprising a gate electrode by the gate electrode film is formed comprising a gate of said gate insulating film pattern gate insulating layer.

[0115] 刻蚀掉半保留光刻胶区域19对应的栅极薄膜也可以使用SF6和02的混合气或者C12和02的混合气进行干法刻蚀,刻蚀掉半保留光刻胶区域19对应的栅极绝缘薄膜也可以使用CF4和02的混合气进行干法刻蚀。 [0115] etching away the half-retained gate thin film regions of the photoresist 19 corresponding may also be used SF6 mixed gas 02 or a mixed gas of C12 and 02 by dry etching, etching away the half-retained regions of the photoresist 19 a gate insulating film corresponding may also be used CF4 and mixed gas 02 by dry etching.

[0116] S505、通过光刻胶剥离工艺,去除全保留光刻胶区域18的光刻胶。 [0116] S505, by photoresist stripping process, the photoresist is removed wholly retained photoresist region 18.

[0117] 该方法经过一次构图工艺,在所述基板上分别形成有源层以及位于像素电极区域、源电极区域、漏电极区域的图形,也形成了栅极绝缘层和栅极,操作简单,方便快捷,也降低了生产成本。 [0117] The method through one patterning process, is formed on the substrate respectively the active layer, and a pixel electrode, graphics source electrode region, the drain region is also formed a gate insulating layer and the gate, simple operation, convenient, but also reduce the production cost.

[0118] 进一步优选的是,所述半导体金属氧化物薄膜是IGZ0(Indium Gallium Zinc Oxide,铟镓锌氧化物)薄膜。 [0118] It is further preferred that the semiconductive metal oxide thin film is IGZ0 (Indium Gallium Zinc Oxide, Indium Gallium Zinc Oxide) film. 所述IGZO薄膜可以使用溅射方法成膜,所述溅射方法成膜时, 通入Ar和O 2,所述O2占总气体的体积百分比是15% -30%。 The IGZO film can be used a sputtering film formation method, when the sputtering film formation method, in an Ar and O 2, the O2 total gas volume percentage is 15% -30%.

[0119] 源电极、漏电极由IGZO薄膜层形成,代替了现有技术不透明的金属薄膜,该方法直接增大了阵列基板的透过率,进而提升了显示器的整体开口率。 [0119] a source electrode, a drain electrode formed from the IGZO thin film layer, instead of the prior art opaque metal thin film, which directly increases the permeability of the array substrate, and thus improve the overall aperture ratio of the display. IGZO是一种含有铟、镓和锌的非晶氧化物,载流子迀移率是非晶硅的20~30倍,由IGZO薄膜形成的有源层,可以大大提高TFT对像素电极的充放电速率,提高像素的响应速度,实现更快的刷新率,同时更快的响应也大大提高了像素的行扫描速率;因为载流子迀移率较高,降低了显示器的耗电量, 且相同电流流过的TFT面积就可以减小,布线也可以减细,不透光部分的面积减小,能够获得很大的开口率。 IGZO是一种含有铟、镓和锌的非晶氧化物,载流子迀移率是非晶硅的20~30倍,由IGZO薄膜形成的有源层,可以大大提高TFT对像素电极的充放电rate, to improve the response speed of the pixels, faster refresh rate, while a faster response also greatly improved the row scanning rate of pixels; because the carrier Gan shift high rate, reducing the power consumption of the display, and the same电流流过的TFT面积就可以减小,布线也可以减细,不透光部分的面积减小,能够获得很大的开口率。

[0120] 另外,IGZO薄膜进行导体化时,可以使用干刻设备,利用SF6和He的组合气体或者只使用He对IGZO薄膜进行离子化(Plasma)处理,离子化时长一般为20s-60s ;或者使用CF4和02的组合气体在干刻设备中对IGZO薄膜进行离子化处理,时长可以为20s-60s。 [0120] Further, when the IGZO film is a conductor, may be used dry etching device, using a combination gas of SF6 and He, or only He the IGZO film is ionized (the Plasma) process, length typically 20s-60s when ionized; or using CF4 and combined gas 02 of the IGZO film is plasma treatment in the dry etching apparatus, the duration may be 20s-60s. 导体化能够提高IGZO薄膜的载流子迀移率,进一步降低功耗。 Conductor of possible to improve the IGZO film carrier Gan drift rate, to further reduce power consumption.

[0121] 较佳地,所述层间介质薄膜的材料为硅的氮化物(SiNx)。 [0121] Preferably, the material of the interlayer dielectric film is a silicon nitride (SiNx). 硅的氮化物薄膜是由硅烷(SiH4)和氨气(NH3)生成,且硅的氮化物(SiNx)中含有氢⑶。 Nitride thin film silicon is generated from silane (SiH4) and ammonia (NH3), and silicon nitride (SiNx) containing hydrogen ⑶ in. 氢⑶经过扩散作用, 可以与像素电极图形、源电极图形和漏电极图形对应的IGZO薄膜层中的氧(0)结合,从而使像素电极区域、源电极区域和漏电极区域对应的IGZO薄膜层进行导体化。 Hydrogen ⑶ After diffusion, may be combined with the pixel electrode pattern, the source electrode pattern and the drain electrode pattern corresponding IGZO thin film layer of oxygen (0), so that the pixel electrode, the source electrode region and a drain region corresponding to the IGZO film layer be a conductor. 制作层间介质薄膜时,使用硅的氮化物(SiNx)使得暴露出的IGZO薄膜进行导体化,省去了单独对暴露出的IGZO薄膜进行导体化的步骤,从而提高了生产效率,降低了生产成本。 Forming an interlayer upon the dielectric film, a silicon nitride (SiNx) such that the exposed IGZO film is a conductor, eliminating separate the IGZO film exposed conductivity developing step, resulting in improved production efficiency, reduce production cost.

[0122] 本发明另一实施例中提供一种薄膜晶体管,包括:基板;在所述基板上同层设置的有源层、源电极、漏电极;位于所述有源层上的栅极绝缘层;位于所述栅极绝缘层上的栅极;所述有源层、源电极、漏电极、栅极绝缘层和栅极通过一次构图工艺形成,所述源电极通过所述有源层与所述漏电极连接。 Disposed in the same layer on the substrate, an active layer, a source electrode, a drain electrode;; substrate is positioned on the gate insulating on the active layer: embodiments provide a thin film transistor, including a further embodiment [0122] of the present invention layer; located gate electrode on the gate insulating layer; said active layer, a source electrode, a drain electrode, a gate insulating layer and a gate electrode formed through one patterning process, the source electrode through the active layer the drain electrode is connected.

[0123] 本发明实施例提供的薄膜晶体管中,其中的有源层、源电极、漏电极、像素电极设置在同一层,栅极绝缘层位于有源层上,栅极位于栅极绝缘层上,简化了现有技术的阵列基板的结构,方便了有源层、源电极、漏电极、像素电极、栅极绝缘层和栅极通过一次构图工艺形成,且有源层、源电极、漏电极、像素电极、栅极绝缘层和栅极通过一次构图工艺形成,减少了薄膜晶体管制作工艺中的掩膜次数,缩短了薄膜晶体管的制作时间,提高了薄膜晶体管的制作效率,降低了薄膜晶体管的生产成本。 [0123] the embodiment of the present invention, a thin film transistor provided in which the active layer, a source electrode, a drain electrode, a pixel electrode disposed in the same layer, a gate insulating layer on the active layer, a gate of the gate insulating layer , simplifies the structure of the array substrate of the prior art, facilitates active layer, a source electrode, a drain electrode, a pixel electrode, a gate insulating layer and a gate electrode formed through one patterning process, and the active layer, a source electrode, a drain electrode , a pixel electrode, a gate insulating layer and a gate electrode through one patterning process is formed, reducing the number of masks thin-film transistor fabrication process, to shorten the production time a thin film transistor, improves the production efficiency of the thin film transistor, reduces the thin film transistor Cost of production.

[0124] 本发明另一实施例中提供一种薄膜晶体管的制作方法,包括以下步骤: [0124] Examples provide a thin film transistor manufacturing method according to another embodiment of the present invention, comprising the steps of:

[0125] 在基板上依次层叠制作半导体金属氧化物薄膜、栅极绝缘薄膜、栅极薄膜; [0125] are sequentially laminated fabricating a semiconductor metal oxide thin film, a gate insulating film, a gate electrode film on the substrate;

[0126] 通过一次构图工艺,将所述半导体金属氧化物薄膜形成包含有源层以及位于源电极区域、漏电极区域的图形,将所述栅极绝缘薄膜形成包含栅极绝缘层的图形,将所述栅极薄膜形成包含栅极的图形;所述源电极通过所述有源层与所述漏电极连接; [0126] through one patterning process, the semiconductive metal oxide thin film formed pattern comprising an active layer, and a source electrode region, a drain region, the gate insulating film forming a pattern comprising the gate insulating layer, and the gate electrode film forming a pattern comprising a gate electrode; the source electrode through the active layer, a drain of said electrode connection;

[0127] 将所述位于源电极区域和漏电极区域的图形进行导体化,形成源电极和漏电极。 [0127] The pattern of the located on the source electrode region and the drain region is a conductor, a source electrode and a drain electrode.

[0128] 本发明实施例提供的薄膜晶体管的制作方法中,其通过层叠成膜和一次构图工艺及导体化步骤,制得的有源层、源电极、漏电极在同一层,栅极绝缘层位于有源层上,栅极位于栅极绝缘层上,该方法减少了薄膜晶体管制作工艺中的掩膜次数,缩短了薄膜晶体管的制作时间,提高了薄膜晶体管的制作效率,降低了薄膜晶体管的生产成本。 [0128] manufacturing method of a thin film transistor according to an embodiment of the present invention, by laminating the film formation and patterning process and a conductor step, the active layer is prepared, a source electrode, a drain electrode in the same layer, a gate insulating layer on the active layer, a gate electrode located on the gate insulating layer, which reduces the number of masks thin-film transistor fabrication process, to shorten the production time a thin film transistor, improves the production efficiency of the thin film transistor, reduces the thin film transistor Cost of production.

[0129] 本发明另一实施例中提供一种包含上述任一方案所述的阵列基板的显示装置。 Another embodiment [0129] of the present invention to provide a display device array substrate of any preceding embodiment said inclusion.

[0130] 本发明实施例提供的显示装置中,其中的有源层、源电极、漏电极、像素电极设置在同一层,栅极绝缘层位于有源层上,栅极位于栅极绝缘层上,简化了现有技术的显示装置的结构,方便了有源层、源电极、漏电极、像素电极、栅极绝缘层和栅极通过一次构图工艺形成,且有源层、源电极、漏电极、像素电极、栅极绝缘层和栅极通过一次构图工艺形成,减少了显示装置制作工艺中的掩膜次数,缩短了显示装置的制作时间,提高了显示装置的制作效率,降低了显示装置的生产成本。 [0130] The display device according to an embodiment of the present invention, wherein the active layer, a source electrode, a drain electrode, a pixel electrode disposed in the same layer, a gate insulating layer on the active layer, a gate electrode located on the gate insulating layer It simplifies the prior art display device structure to facilitate the active layer, a source electrode, a drain electrode, a pixel electrode, a gate insulating layer and the gate electrode by a patterning process to form, and the active layer, source and drain electrodes , a pixel electrode, a gate insulating layer and a gate electrode through one patterning process is formed, reduces the number of mask manufacturing process in the display device, shorten the production time of the display device, to improve the production efficiency of the display device reduces the display device Cost of production.

[0131] 以上所述,仅为本发明的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本发明的保护范围之内。 [0131] The above are only specific embodiments of the present invention, but the scope of the present invention is not limited thereto, any skilled in the art in the art within the scope of the invention disclosed can be easily thought variations or Alternatively, it shall fall within the protection scope of the present invention. 因此,本发明的保护范围应以权利要求所述的保护范围为准。 Accordingly, the scope of the present invention should be scope of the claims of the subject.

Claims (15)

  1. 1. 一种阵列基板,包括基板,其特征在于,还包括: 在所述基板上同层设置的有源层、源电极、漏电极、像素电极; 位于所述有源层上的栅极绝缘层; 位于所述栅极绝缘层上的栅极; 所述有源层、源电极、漏电极、像素电极、栅极绝缘层和栅极通过一次构图工艺形成,所述源电极通过所述有源层与所述漏电极连接。 An array substrate comprising a substrate, characterized by further comprising: an active layer with the layer provided on the substrate, a source electrode, a drain electrode, a pixel electrode; a gate insulating on the active layer layer; located on the gate insulation layer on the gate; the active layer, source and drain electrodes, the pixel electrode, a gate insulating layer and the gate electrode by a patterning process to form the source electrode through which there source layer and the drain electrode is connected.
  2. 2. 根据权利要求1所述的阵列基板,其特征在于,还包括: 位于所述像素电极、源电极、漏电极、栅极上的层间介质,所述层间介质包括对应所述源电极的过孔; 位于所述层间介质上的数据线,所述数据线通过所述过孔与所述源电极连接。 The array substrate according to claim 1, characterized in that, further comprising: a pixel electrode, a source electrode, a drain electrode, inter-layer on the gate dielectric, the interlayer dielectric comprises corresponding to the source electrode vias; a data line on the dielectric interlayer, the data line through the via hole to the source electrode.
  3. 3. 根据权利要求2所述的阵列基板,其特征在于,还包括: 位于所述数据线和所述层间介质上的纯化层; 位于所述纯化层上的公共电极。 3. The array substrate according to claim 2, characterized in that, further comprising: a passivation layer on the medium between said data lines and said layer; a common electrode on the passivation layer.
  4. 4. 根据权利要求3所述的阵列基板,其特征在于,还包括;位于所述纯化层上的有机树脂层,所述公共电极位于所述有机树脂层上。 4. The array substrate of claim 3, characterized by further comprising; located on said organic resin layer on the passivation layer, the common electrode located on the organic resin layer.
  5. 5. -种阵列基板的制作方法,其特征在于,包括W下步骤: 在基板上依次层叠制作半导体金属氧化物薄膜、栅极绝缘薄膜、栅极薄膜; 通过一次构图工艺,将所述半导体金属氧化物薄膜形成包含有源层W及位于像素电极区域、源电极区域、漏电极区域的图形,将所述栅极绝缘薄膜形成包含栅极绝缘层的图形, 将所述栅极薄膜形成包含栅极的图形;所述源电极通过所述有源层与所述漏电极连接; 将所述位于像素电极区域、源电极区域和漏电极区域的图形进行导体化,形成像素电极、源电极和漏电极。 5. - Production Method kinds array substrate, characterized by comprising W the steps of: sequentially laminating fabricating a semiconductor metal oxide thin film, a gate insulating film, a gate electrode film on the substrate; through one patterning process, the semiconductor metal oxide thin film is formed comprising an active layer W, and the pixel electrode region, graphics source electrode region, a drain region, the gate insulating film forming a pattern comprising the gate insulating layer, the gate electrode film is formed comprising a gate electrode pattern; the source electrode through the active layer, a drain of said pole connector; the located pixel electrode, a source electrode region and a pattern drain electrode region is a conductor, a pixel electrode, source and drain electrodes pole.
  6. 6. 根据权利要求5所述的阵列基板的制作方法,其特征在于,所述形成像素电极、源电极和漏电极之后还包括: 制作覆盖所述像素电极、源电极、漏电极、栅极的层间介质薄膜,通过一次构图工艺将所述层间介质薄膜形成包含过孔的层间介质,所述过孔对应所述源电极; 制作覆盖所述过孔的数据线薄膜,通过一次构图工艺将所述数据线薄膜形成包含数据线的图形,所述数据线通过所述过孔与所述源电极连接。 The production method of the array substrate as claimed in claim, wherein said pixel electrode, the source electrode and the drain electrode further comprises: making covering the pixel electrode, a source electrode, a drain electrode, a gate the interlayer dielectric film, through one patterning process to the interlayer dielectric film forming the interlayer dielectric comprises a through hole, the through hole corresponding to the source electrode; production cover the data line of the through hole of the film, through one patterning process the data line film-forming pattern, said data lines comprising a data line through said via hole connected to the source electrode.
  7. 7. 根据权利要求6所述的阵列基板的制作方法,其特征在于,所述通过一次构图工艺将所述数据线薄膜形成包含数据线的图形之后还包括: 制作覆盖所述数据线和所述层间介质的纯化层薄膜,通过一次构图工艺将所述纯化层薄膜形成纯化层; 在所述纯化层上制作公共电极薄膜,通过一次构图工艺将所述公共电极薄膜形成包含公共电极的图形。 The production method of claim 6 array substrate as claimed in claim, characterized in that, after the data line film-forming pattern comprising a data line of the through one patterning process further comprising: making covering the data line and the purification layer film interlayer dielectric by a patterning process to the formation of the passivation layer passivation layer film; making a common electrode film on said passivation layer, forming a pattern comprising a common electrode through one patterning process to the common electrode film.
  8. 8. 根据权利要求7所述的阵列基板的制作方法,其特征在于,所述通过一次构图工艺将所述纯化层薄膜形成纯化层包括: 制作覆盖所述纯化层薄膜的有机树脂薄膜; 将所述有机树脂薄膜在纯化层区域的有机树脂保留,其他区域的有机树脂去除,形成有机树脂层; 将暴露出的纯化层薄膜去除,形成纯化层; 所述在所述纯化层上制作公共电极薄膜具体为;在所述有机树脂层上制作公共电极薄膜。 8. A manufacturing method of an array substrate according to claim 7, wherein said through one patterning process of the passivation layer thin-film forming the passivation layer comprises: an organic resin film prepared covering the passivation layer film; The said organic resin film in an organic resin remains purified layer region, the organic resin other regions is removed, the organic resin layer is formed; the exposed passivation layer film is removed to form a passivation layer; the production of a common electrode film on said passivation layer specifically; making a common electrode film on said organic resin layer.
  9. 9. 根据权利要求7所述的阵列基板的制作方法,其特征在于,在所述通过一次构图工艺将所述公共电极薄膜形成包含公共电极的图形之后,对阵列基板进行退火处理,所述退火温度为200°C -250°C。 9. A manufacturing method of an array substrate according to claim 7, wherein, after a patterning process to the common electrode film is formed comprising a pattern of the common electrode of the pass, array substrate is annealed, said annealing temperature of 200 ° C -250 ° C.
  10. 10. 根据权利要求5所述的阵列基板的制作方法,其特征在于, 所述通过一次构图工艺,将所述半导体金属氧化物薄膜形成包含有源层W及位于像素电极区域、源电极区域、漏电极区域的图形,将所述栅极绝缘薄膜形成包含栅极绝缘层的图形,将所述栅极薄膜形成包含栅极的图形,包括W下步骤: 在所述栅极薄膜上涂覆光刻胶;通过半色调掩膜板对光刻胶进行一次曝光、显影,使得光刻胶形成半保留光刻胶区域、全保留光刻胶区域和全去除光刻胶区域,所述半保留光刻胶区域包括源电极区域、漏电极区域和像素电极区域,所述全保留光刻胶区域包括栅极区域,除半保留光刻胶区域、全保留光刻胶区域之外的区域为全去除光刻胶区域; 刻蚀掉全去除光刻胶区域对应的栅极薄膜、栅极绝缘薄膜和半导体金属氧化物薄膜; 通过第一次灰化工艺,去除半保留 10. A method for manufacturing an array substrate 5 according to claim, wherein said through one patterning process, the semiconductive metal oxide thin film is formed, a source electrode region comprising an active layer W, and the pixel electrode region, graphics drain region, the gate insulating film forming a pattern comprising the gate insulating layer, the gate electrode film forming a pattern comprising a gate electrode comprising W the steps of: coating light on the gate electrode film engraved gum; photoresist once exposed to light through a halftone mask, developed, so that photoresist forms a semi-retained regions of the photoresist, the whole retention photoresist regional and removing the photoresist regions, the half-retained optical engraved gum region including a source electrode region, the drain region and the pixel electrode region, the full retention photoresist region including a gate region, in addition to semi-retained regions of the photoresist, the whole area other than the resist area remains wholly removed regions of the photoresist; etch away the full removal of the gate film, a gate insulating film and a semiconductor metal oxide thin film of the photoresist corresponding to a region; by a first ashing process to remove the semi-conservative 刻胶区域的光刻胶,且去除全保留光刻胶区域的部分光刻胶; 刻蚀掉所述半保留光刻胶区域对应的栅极薄膜和栅极绝缘薄膜,W便由所述栅极薄膜形成包含栅极的图形,由所述栅极绝缘薄膜形成包含栅极绝缘层的图形; 通过光刻胶剥离工艺,去除所述全保留光刻胶区域的光刻胶。 The photoresist engraved rubber region, and removing portions of the photoresist full retention photoresist region; etching away the half-retained photoresist region corresponding to the gate electrode film and the gate insulating film, W then by the grid electrode film forming a pattern comprising a gate electrode, forming a pattern comprising the gate insulating layer by the gate insulating film; by photoresist stripping process, removing said full retention photoresist resist region.
  11. 11. 根据权利要求5所述的阵列基板的制作方法,其特征在于,所述半导体金属氧化物薄膜是IGZO薄膜。 According to claim 5, wherein the array substrate manufacturing method, wherein the semiconductor metal oxide film is IGZO film.
  12. 12. 根据权利要求6所述的阵列基板的制作方法,其特征在于,所述层间介质薄膜的材料包含Si化。 12. A manufacturing method of an array substrate according to claim 6, wherein the interlayer material is a dielectric film containing Si of.
  13. 13. -种薄膜晶体管,包括基板,其特征在于,还包括: 在所述基板上同层设置的有源层、源电极、漏电极; 位于所述有源层上的栅极绝缘层; 位于所述栅极绝缘层上的栅极; 所述有源层、源电极、漏电极、栅极绝缘层和栅极通过一次构图工艺形成,所述源电极通过所述有源层与所述漏电极连接。 13. - kind of thin film transistor comprising a substrate, characterized by further comprising: in the same layer on the substrate, an active layer, a source electrode, a drain electrode; a gate insulating layer on the active layer, said; a a gate on the gate insulating layer; said active layer, a source electrode, a drain electrode, a gate insulating layer and a gate electrode through one patterning process for forming the source electrode through the active layer and the drain connected.
  14. 14. 一种薄膜晶体管的制作方法,其特征在于,包括W下步骤: 在基板上依次层叠制作半导体金属氧化物薄膜、栅极绝缘薄膜、栅极薄膜; 通过一次构图工艺,将所述半导体金属氧化物薄膜形成包含有源层W及位于源电极区域、漏电极区域的图形,将所述栅极绝缘薄膜形成包含栅极绝缘层的图形,将所述栅极薄膜形成包含栅极的图形;所述源电极通过所述有源层与所述漏电极连接; 将所述位于源电极区域和漏电极区域的图形进行导体化,形成源电极和漏电极。 Production method 14. A thin film transistor, comprising the W steps of: sequentially laminating fabricating a semiconductor metal oxide thin film, a gate insulating film, a gate electrode film on the substrate; through one patterning process, the semiconductor metal oxide thin film is formed comprising an active layer W and the pattern on the source electrode region, a drain region, the gate insulating film forming a pattern comprising the gate insulating layer, the gate electrode film forming a pattern comprising a gate electrode; the source electrode through the active layer and the drain electrode is connected; the on the source electrode region and a drain region of the graphic conductor, thereby forming a source electrode and a drain electrode.
  15. 15. -种包含权利要求1-4任一项所述的阵列基板的显示装置。 15. - Species containing display device as claimed one of the array substrate of claims 1-4.
CN 201510105369 2015-03-10 2015-03-10 Array substrate, thin-film transistor and manufacturing methods thereof as well as display device CN104681627A (en)

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