CN104681627A - Array substrate, thin-film transistor and manufacturing methods thereof as well as display device - Google Patents
Array substrate, thin-film transistor and manufacturing methods thereof as well as display device Download PDFInfo
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- CN104681627A CN104681627A CN201510105369.3A CN201510105369A CN104681627A CN 104681627 A CN104681627 A CN 104681627A CN 201510105369 A CN201510105369 A CN 201510105369A CN 104681627 A CN104681627 A CN 104681627A
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- 239000010409 thin film Substances 0.000 title claims abstract description 63
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 60
- 239000000758 substrate Substances 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 claims abstract description 123
- 230000008569 process Effects 0.000 claims abstract description 74
- 238000000059 patterning Methods 0.000 claims abstract description 58
- 239000010408 film Substances 0.000 claims description 184
- 239000010410 layer Substances 0.000 claims description 157
- 229920002120 photoresistant polymer Polymers 0.000 claims description 78
- 239000012212 insulator Substances 0.000 claims description 58
- 238000002161 passivation Methods 0.000 claims description 52
- 229910044991 metal oxide Inorganic materials 0.000 claims description 40
- 150000004706 metal oxides Chemical class 0.000 claims description 39
- 239000011347 resin Substances 0.000 claims description 30
- 229920005989 resin Polymers 0.000 claims description 30
- 239000004020 conductor Substances 0.000 claims description 18
- 239000011229 interlayer Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 8
- 229910004205 SiNX Inorganic materials 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 230000000717 retained effect Effects 0.000 claims description 3
- 238000009413 insulation Methods 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 45
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 31
- 229910052710 silicon Inorganic materials 0.000 description 31
- 239000010703 silicon Substances 0.000 description 31
- 239000000377 silicon dioxide Substances 0.000 description 22
- 150000004767 nitrides Chemical class 0.000 description 18
- 235000012239 silicon dioxide Nutrition 0.000 description 16
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 12
- 238000005530 etching Methods 0.000 description 8
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 229910052733 gallium Inorganic materials 0.000 description 7
- 229910052738 indium Inorganic materials 0.000 description 7
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 7
- 239000008246 gaseous mixture Substances 0.000 description 6
- 239000012528 membrane Substances 0.000 description 6
- 229960001296 zinc oxide Drugs 0.000 description 6
- 235000014692 zinc oxide Nutrition 0.000 description 6
- 239000011787 zinc oxide Substances 0.000 description 6
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005056 compaction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000003116 impacting effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- -1 preferably Chemical compound 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The invention belongs to the technical field of display, and particularly relates to an array substrate, a thin-film transistor and manufacturing methods thereof as well as a display device. The array substrate comprises a substrate (1), and an active layer (2), a source electrode (3), a drain electrode (4) and a pixel electrode (5) which are arranged on the same layer of the substrate (1), as well as a grid insulation layer (6) positioned on the active layer (2) and a grid electrode (7) positioned on the grid insulation layer (6), wherein the active layer (2), the source electrode (3), the drain electrode (4), the pixel electrode (5), the grid insulation layer (6) and the grid electrode (7) are formed through a one-time patterning process; the source electrode (3) is connected with the drain electrode (4) through the active layer (2). The array substrate solves the technical problems that the existing array substrate is relatively complicated in structure, more in manufacturing process, low in production efficiency, relatively high in cost and the like, can substitute the existing array substrate, and is applicable to the technical field of display.
Description
Technical field
The invention belongs to Display Technique field, particularly relate to a kind of array base palte, thin-film transistor and manufacture method, display unit.
Background technology
Along with the develop rapidly of Display Technique, the characteristic requirements such as resolution, response time, power consumption of people to display is also more and more higher.In this case, the development of the Display Techniques such as the increasing and 3D of the size along with display, requires more and more higher to the mobility of the TFT be arranged on display array substrate (Thin Film Transistor, thin-film transistor).The mobility of TFT refers to charge carrier in the active layer of TFT (electronics and hole) the average drift velocity under unit electric field effect.In fact be manufactured with active layer with amorphous silicon and can not have met requirement to mobility, people have brought into use the metal oxide materials with higher migration rate.
Metal current oxide technique has become the mainstream technology of large scale, high image quality, low power consumption display product gradually, and each large display commercial city is at volume production or active development.Senior super dimension field switch technology (ADvanced Super Dimension Switch, be called for short ADS) Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Display can be improved, be called for short TFT-LCD) picture quality of product, have high-resolution, high permeability, low-power consumption, wide viewing angle, high aperture, low aberration, without advantages such as water of compaction ripples (push mura).
But the preparation process of the oxide TFT array substrate of ADS pattern, needs 7-9 road mask (mask) technique usually, the TFT especially in array base palte just needs 5 road masking process, therefore complex manufacturing technology, and production efficiency is lower, and cost is higher.
Summary of the invention
Embodiments of the invention provide a kind of array base palte, thin-film transistor and manufacture method, display unit, in order to solve, thin-film transistor in prior art, array base palte complex manufacturing technology, production efficiency are lower, cost comparatively high-technology problem, the structure of this array base palte is simple, manufacture craft is less, thus production efficiency is high, cost is lower.
For achieving the above object, embodiments of the invention adopt following technical scheme:
A kind of array base palte, comprising:
Substrate;
On the substrate with active layer, source electrode, drain electrode, pixel electrode that layer is arranged;
Be positioned at the gate insulator on described active layer;
Be positioned at the grid on described gate insulator;
Described active layer, source electrode, drain electrode, pixel electrode, gate insulator and grid are formed by a patterning processes, and described source electrode is connected with described drain electrode by described active layer.
Preferably, described array base palte also comprises such scheme:
Be positioned at the inter-level dielectric (Inter Level Dielectric is called for short ILD) on described pixel electrode, source electrode, drain electrode, grid, described inter-level dielectric comprises the via hole of corresponding described source electrode;
Be positioned at the data wire on described inter-level dielectric, described data wire is connected with described source electrode by described via hole.
Preferably, described array base palte also comprises above-mentioned either a program:
Be positioned at the passivation layer (passivation is called for short PVX) on described data wire and described inter-level dielectric;
Be positioned at the public electrode on described passivation layer.
Preferably, described array base palte also comprises above-mentioned either a program: be positioned at the organic resin layer on described passivation layer, described public electrode is positioned on described organic resin layer.
A manufacture method for array base palte, comprises the following steps:
Substrate stacks gradually and makes metal oxide thin films, grid insulating film, grid film;
By a patterning processes, described metal oxide thin films is formed and includes active layer and be positioned at the figure of pixel electrode area, source electrode region, drain regions, described grid insulating film is formed the figure comprising gate insulator, described grid film is formed the figure comprising grid; Described source electrode is connected with described drain electrode by described active layer;
By being describedly positioned at pixel electrode area, the figure of source electrode region and drain regions carries out conductor, forms pixel electrode, source electrode and drain electrode.
Such scheme preferably, also comprises after described formation pixel electrode, source electrode and drain electrode:
Make the interlayer medium film covering described pixel electrode, source electrode, drain electrode, grid, described interlayer medium film is formed by a patterning processes inter-level dielectric comprising via hole, the corresponding described source electrode of described via hole;
Make the data wire film covering described via hole, described data wire film is formed by a patterning processes figure comprising data wire, described data wire is connected with described source electrode by described via hole.
Above-mentioned either a program preferably, described by patterning processes described data wire film formed comprise the figure of data wire after also comprise:
Make the passivation layer film covering described data wire and described inter-level dielectric, by a patterning processes, described passivation layer film is formed passivation layer;
Described passivation layer makes public electrode film, described public electrode film is formed by a patterning processes figure comprising public electrode.
Described passivation layer film preferably, is describedly formed passivation layer by patterning processes and comprises by above-mentioned either a program:
Make the organic resin film covering described passivation layer film;
Retained by the organic resin of described organic resin film in passivation layer region, the organic resin in other regions is removed, and forms organic resin layer;
The passivation layer film exposed is removed, forms passivation layer;
The described public electrode film that makes on described passivation layer is specially: on described organic resin layer, make public electrode film.
Above-mentioned either a program preferably, described by patterning processes described public electrode film to be formed comprise the figure of public electrode after, array substrate carries out annealing in process, and described annealing temperature is 200 DEG C-250 DEG C.
Above-mentioned either a program preferably, describedly pass through a patterning processes, described metal oxide thin films is formed and includes active layer and be positioned at the figure of pixel electrode area, source electrode region, drain regions, described grid insulating film is formed the figure comprising gate insulator, described grid film is formed the figure comprising grid, comprises the following steps:
Described grid film applies photoresist; By intermediate tone mask plate, single exposure, development are carried out to photoresist, photoresist is formed, and half retains photoresist region, all risk insurance stays photoresist region and full removal photoresist region, described half retains photoresist region comprises source electrode region, drain regions and pixel electrode area, described all risk insurance stays photoresist region to comprise area of grid, except half reservation photoresist region, all risk insurance stay the region except photoresist region to remove photoresist region for complete;
Etch away grid film, grid insulating film and metal oxide thin films that full removal photoresist region is corresponding;
By first time cineration technics, remove the photoresist that half retains photoresist region, and remove the part photoresist that all risk insurance stays photoresist region;
Etch away described half and retain grid film corresponding to photoresist region and grid insulating film, to form by described grid film the figure comprising grid, formed the figure comprising gate insulator by described grid insulating film;
By photoresist stripping process, remove the photoresist that described all risk insurance stays photoresist region.
Preferably, described metal oxide thin films is IGZO (Indium Gallium Zinc Oxide, indium gallium zinc oxide) film to above-mentioned either a program.
Preferably, the material of described interlayer medium film comprises SiNx to above-mentioned either a program.
A kind of thin-film transistor, comprising:
Substrate;
On the substrate with active layer, source electrode, drain electrode that layer is arranged;
Be positioned at the gate insulator on described active layer;
Be positioned at the grid on described gate insulator;
Described active layer, source electrode, drain electrode, gate insulator and grid are formed by a patterning processes, and described source electrode is connected with described drain electrode by described active layer.
A manufacture method for thin-film transistor, comprises the following steps:
Substrate stacks gradually and makes metal oxide thin films, grid insulating film, grid film;
By a patterning processes, described metal oxide thin films is formed and includes active layer and be positioned at the figure of source electrode region, drain regions, described grid insulating film is formed the figure comprising gate insulator, described grid film is formed the figure comprising grid; Described source electrode is connected with described drain electrode by described active layer;
The described figure being positioned at source electrode region and drain regions is carried out conductor, forms source electrode and drain electrode.
A kind of display unit comprising array base palte described in above-mentioned either a program.
The array base palte that the embodiment of the present invention provides, active layer, source electrode, drain electrode, pixel electrode is arranged on same layer, gate insulator is positioned on active layer, grid is positioned on gate insulator, simplify the structure of the array base palte of prior art, facilitate active layer, source electrode, drain electrode, pixel electrode, gate insulator and grid are formed by a patterning processes, and active layer, source electrode, drain electrode, pixel electrode, gate insulator and grid are formed by a patterning processes, decrease the masking process of array base palte, shorten the manufacturing time of array base palte, improve the manufacture efficiency of array base palte, reduce the production cost of array base palte.
Accompanying drawing explanation
Fig. 1 is the schematic cross-section of the array base palte in one embodiment of the invention.
Fig. 2 is the schematic cross-section of the array base palte in another embodiment of the present invention.
Fig. 3 is the schematic cross-section of the array base palte in another embodiment of the present invention.
Fig. 4 is the schematic cross-section of the array base palte in another embodiment of the present invention.
Fig. 5 is that stacking gradually on substrate in one embodiment of the invention makes metal oxide thin films, grid insulating film, schematic cross-section after grid film.
Fig. 6 be in one embodiment of the invention by a patterning processes, form in the graphic procedure of pixel electrode area, source electrode region, drain regions, gate insulator and grid the schematic cross-section after applying mask lithography glue.
Fig. 7 be in one embodiment of the invention by a patterning processes, formed in the graphic procedure of pixel electrode area, source electrode region, drain regions, gate insulator and grid, etch away and entirely remove the schematic cross-section after photoresist region corresponding grid film, grid insulating film and metal oxide thin films.
Fig. 8 be in one embodiment of the invention by a patterning processes, formed in the graphic procedure of pixel electrode area, source electrode region, drain regions, gate insulator and grid, by first time cineration technics, remove the photoresist that half retains photoresist region, and remove all risk insurance stay the part photoresist in photoresist region after schematic cross-section.
Fig. 9-1 be in one embodiment of the invention by a patterning processes, formed in the graphic procedure of pixel electrode area, source electrode region, drain regions, gate insulator and grid, etch away the schematic cross-section after grid film corresponding to half reservation photoresist region and grid insulating film.
Fig. 9-2 be in one embodiment of the invention by a patterning processes, formed in the graphic procedure of pixel electrode area, source electrode region, drain regions, gate insulator and grid, after etching away grid film corresponding to half reservation photoresist region and grid insulating film, carry out the schematic cross-section of conductor.
Figure 10 is the manufacture method schematic flow sheet of the array base palte in one embodiment of the invention.
Figure 11 is the manufacture method part run schematic diagram of the array base palte in one embodiment of the invention.
Figure 12 is the manufacture method part run schematic diagram of the array base palte in one embodiment of the invention.
Figure 13 is in the manufacture method of array base palte in one embodiment of the invention, passivation layer film is formed the schematic flow sheet of passivation layer.
Figure 14 is the manufacture method part run schematic diagram of the array base palte in one embodiment of the invention.
Reference numeral: 1-substrate, 2-active layer, 3-source electrode, 4-drain electrode, 5-pixel electrode, 6-gate insulator, 7-grid, 8-inter-level dielectric, 9-via hole, 10-data wire, 11-passivation layer, 12-organic resin layer, 13-public electrode, 14-metal oxide thin films, 15-grid insulating film, 16-grid film, 17-photoresist, 18-all risk insurance stays photoresist region, and 19-half retains photoresist region, and 20-removes photoresist region entirely.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
As everyone knows, thin-film transistor (TFT) comprising: grid, source electrode and drain electrode.Generally, the source electrode of TFT and drain electrode can be considered as being equal to; Namely except in the two poles of the earth in TFT except grid, can by wherein any one is called source electrode, another pole is called drain electrode.Concrete, what cause in order to avoid appellation in embodiments of the present invention obscures, and TFT and data wire is electrically connected a pole and is called source electrode, the pole that TFT and pixel electrode are electrically connected is called drain electrode.Certainly, if TFT and data wire are electrically connected a pole be called drain electrode, the pole that TFT and pixel electrode are electrically connected are called source electrode, are also fine.
A kind of array base palte is provided in one embodiment of the invention, as shown in Figure 1, comprises: substrate 1; On substrate 1 with active layer 2, source electrode 3, drain electrode 4, pixel electrode 5 that layer is arranged; Be positioned at the gate insulator 6 on described active layer; Be positioned at the grid 7 on described gate insulator; Described active layer 2, source electrode 3, drain electrode 4, pixel electrode 5, gate insulator 6 and grid 7 is formed by a patterning processes, and described source electrode 3 is connected with described drain electrode 4 by described active layer 2.
In the embodiment of the present invention, as shown in Figure 1, source electrode 3 is connected with drain electrode 4 by active layer 2, and drain electrode 4 is connected with pixel electrode 5.These are the changes slightly carried out based on the spirit of the embodiment of the present invention, all should fall into protection scope of the present invention.
In the array base palte that the embodiment of the present invention provides, active layer, source electrode, drain electrode, pixel electrode is arranged on same layer, gate insulator is positioned on active layer, grid is positioned on gate insulator, simplify the structure of the array base palte of prior art, facilitate active layer, source electrode, drain electrode, pixel electrode, gate insulator and grid are formed by a patterning processes, and active layer, source electrode, drain electrode, pixel electrode, gate insulator and grid are formed by a patterning processes, decrease the masking process number of times of array base palte, shorten the Production Time of array base palte, improve the make efficiency of array base palte, reduce the production cost of array base palte.
It should be noted that, for array base palte, generally also need setting data line.For the present embodiment preferably, array base palte as shown in Figure 2 also comprises: be positioned at inter-level dielectric (the Inter Level Dielectric on pixel electrode 5, source electrode 3, drain electrode 4, grid 7, be called for short ILD) 8, inter-level dielectric 8 comprises the via hole 9 of corresponding described source electrode 3; Be positioned at the data wire 10 on inter-level dielectric 8, data wire 10 is connected with source electrode 3 by via hole 9.Source electrode, drain electrode, pixel electrode that data wire takes the method to arrange can to facilitate make early stage are further processed (as conductor process).In practice process, also data wire and source electrode can be carried out same layer and arrange.The material of data wire can be aluminium, copper or the good metal material of other electric conductivities.
Inter-level dielectric 8 is a kind of insulation systems, and pixel electrode 5, source electrode 3, drain electrode 4, grid 7 can be made to insulate with other parts.The thickness of inter-level dielectric 8 can be
the concrete material of inter-level dielectric 8 can be SiNx, SiON or SiO
2single thin film, or the laminated film of the nitride of silicon (SiNx) and silicon dioxide (SiO2) (being namely the nitride film of silicon and the laminated film of silica membrane formation), or the laminated film of silicon dioxide and silicon oxynitride (SiON) (being namely the laminated film that silica membrane and silicon oxynitride film are formed), or the laminated film of the nitride of silicon dioxide, silicon oxynitride and silicon (being namely the laminated film that the nitride film of silica membrane, silicon oxynitride film and silicon is formed).
The cross section of via hole 9 can be V-type, T-shaped or U-shaped structure or other there is the structure of phase same-action.Shown in Fig. 2 is V-structure.
In order to protect source electrode, drain electrode, pixel electrode, grid, data wire etc., avoid them to be subject to oxide etch effect, array base palte as shown in Figure 3,4 also comprises: be positioned at the passivation layer 11 on data wire 10 and inter-level dielectric 8; Be positioned at the public electrode 13 on passivation layer 11.
Passivation layer 11 can be silicon dioxide layer film, or the laminated film of silicon dioxide and silicon oxynitride, and the thickness of passivation layer can be
the thickness of public electrode 13 can be
In another preferred embodiment, described array base palte also comprises: be positioned at the organic resin layer 12 on passivation layer 11, and public electrode 13 is positioned on organic resin layer 12, as shown in Figure 4.The setting of organic resin layer, can reduce the parasitic capacitance between public electrode and data wire, thus reduces the power consumption of array base palte, also can make the surface plate of array base palte.
In another embodiment of the present invention, the manufacture method of array base palte as shown in Figure 10, comprises the following steps:
S101, stack gradually on substrate make metal oxide thin films 14, grid insulating film 15, grid film 16.
Stacking gradually on substrate as shown in Figure 5 makes metal oxide thin films, grid insulating film, schematic cross-section after grid film.Substrate makes metal oxide thin films, sputtering method can be used to deposit film forming, the material of metal-oxide film can be IGZO (Indium Gallium ZincOxide, indium gallium zinc oxide) or ITZO (indium tin zinc oxide), the thickness of metal oxide thin films is generally
When making grid insulating film, be make on the substrate being formed with metal-oxide film.Manufacture method can be PECVD (plasma enhanced chemical vapor deposition method), and the gross thickness of grid insulating film layer can be
grid insulating film can be the silica membrane of individual layer, also can be the nitride of silicon and the laminated film (being namely the nitride film of silicon and the laminated film of silica membrane formation) of silicon dioxide, or the laminated film of the nitride of silicon, silicon oxynitride and silicon dioxide.If grid insulating film layer is the nitride of silicon and the laminated film of silicon dioxide, or the nitride of silicon, the laminated film of silicon oxynitride and silicon dioxide, preferably, silica membrane is contacted with metal oxide thin films, the nitride film of silicon or silicon oxynitride film should be avoided directly to contact with metal oxide thin films, this is because when the nitride film of silicon or silicon oxynitride film contact with metal oxide thin films, especially time with IGZO film contacts, hydrogen (H) in the nitride film of silicon or silicon oxynitride film can carry out conductor to metal oxide thin films, thus have impact on the characteristic of metal oxide thin films.
When making grid film, be make on the substrate being formed with grid insulating film.Manufacture method can be sputtering sedimentation, and the material of grid film can be the metal such as molybdenum (Mo), aluminium (Al), and thickness is
S102, by a patterning processes, metal oxide thin films 14 is formed and includes active layer and be positioned at the figure of pixel electrode area, source electrode region, drain regions, described grid insulating film is formed the figure comprising gate insulator, described grid film is formed the figure comprising grid; Described source electrode is connected with described drain electrode by described active layer.
Describedly pass through a patterning processes, specifically comprise the techniques such as coating photoresist, exposure, development, etching.Wherein, exposure technology needs to use mask plate to control the exposure of photoresist in zones of different.In the whole manufacturing process of array base palte, usually the number of times of number as patterning processes of mask plate will be used; That is, carry out a patterning processes to be use mask plate and to complete composition.As Fig. 9-1, the method, by a patterning processes, defines active layer, pixel electrode area, source electrode region, drain regions, gate insulator and gate patterns.
S103, by being describedly positioned at pixel electrode area, the figure of source electrode region and drain regions carries out conductor, forms pixel electrode, source electrode and drain electrode.
As Fig. 9-2, by conductor, the metal-oxide film of pixel electrode area, source electrode region, drain regions be form respectively pixel electrode, source electrode, drain electrode.Arrow in Fig. 9-2 represents conductor, conductorization can reduce the contact resistance between data wire and source electrode, also metal oxide semiconductor can be made to serve as pixel electrode, simultaneously, because only corresponding to pixel electrode area, source electrode region, drain regions metal oxide thin films carries out conductor, so do not affect the characteristic of metal oxide thin films corresponding to active layer.
In the manufacture method of the array base palte that the embodiment of the present invention provides, by stacked film forming and a patterning processes and conductor step, obtained active layer, source electrode, drain electrode, pixel electrode are at same layer, gate insulator is positioned on active layer, grid is positioned on gate insulator, the method reduces the masking process number of times of array base palte, shortens the Production Time of array base palte, improve the make efficiency of array base palte, reduce the production cost of array base palte.
Preferably in embodiment, in the manufacture method of array base palte as shown in figure 11, also comprise after described formation pixel electrode, source electrode and drain electrode:
The interlayer medium film of S201, the described pixel electrode of making covering, source electrode, drain electrode, grid, forms by a patterning processes inter-level dielectric comprising via hole by described interlayer medium film, the corresponding described source electrode of described via hole.
Inter-level dielectric is a kind of insulation system, and pixel electrode, source electrode, drain electrode, grid and other parts can be made to insulate.The thickness of inter-level dielectric can be
film build method can be PECVD, concrete material can be the nitride of silicon and the laminated film of silicon dioxide (SiO2), or the laminated film of silicon dioxide and silicon oxynitride (SiON), or the laminated film of the nitride of silicon dioxide, silicon oxynitride and silicon.
The cross section of via hole can be V-type, T-shaped or U-shaped structure or other there is the structure of phase same-action.
The data wire film of S202, the described via hole of making covering, described data wire film is formed by a patterning processes figure comprising data wire, described data wire is connected with described source electrode by described via hole.
Preferably, the manufacture method of array base palte as shown in figure 12, described by patterning processes described data wire film formed comprise the figure of data wire after also comprise:
The passivation layer film of S301, the making described data wire of covering and described inter-level dielectric, forms passivation layer by a patterning processes by described passivation layer film.
Passivation layer can be silicon dioxide layer film, or the laminated film of silicon dioxide and silicon oxynitride, and the thickness of passivation layer can be
film build method can be PECVD.Passivation layer can protect source electrode, drain electrode, pixel electrode, grid, data wire etc., avoids them to be subject to oxide etch effect.
S302, on described passivation layer, make public electrode film, described public electrode film is formed by a patterning processes figure comprising public electrode.The thickness of public electrode can be
film build method can be magnetron sputtering method.
As shown in figure 13, describedly by patterning processes, described passivation layer film is formed passivation layer and comprises:
The organic resin film of S401, the described passivation layer film of making covering.
S402, retained by the organic resin of described organic resin film in passivation layer region, the organic resin in other regions is removed, and forms organic resin layer.The setting of organic resin layer, can reduce the parasitic capacitance between public electrode and data wire, thus reduces the power consumption of array base palte, also can make the surface plate of array base palte.
S403, the passivation layer film removal that will expose, form passivation layer.
S404, the described public electrode film that makes on described passivation layer are specially: on described organic resin layer, make public electrode film.
This step, define passivation layer and organic resin layer by a patterning processes, manufacture craft is easy, and production cost is lower.
In preferred embodiment, described by patterning processes described public electrode film to be formed comprise the figure of public electrode after, array substrate carries out annealing in process, and described annealing temperature is 200 DEG C-250 DEG C.Annealing in process is the stability in order to improve oxide array substrate, reduces the resistivity of pixel electrode simultaneously; The temperature of annealing in process should, higher than the rear baking temperature of organic resin layer, not avoided impacting organic resin layer.
In another embodiment of the present invention, as Fig. 1,6,7,8, shown in 9-1,9-2,14, describedly pass through a patterning processes, described metal oxide thin films is formed and includes active layer and be positioned at the figure of pixel electrode area, source electrode region, drain regions, described grid insulating film is formed the figure comprising gate insulator, described grid film is formed the figure comprising grid, comprises the following steps:
S501, on described grid film, apply photoresist 17; By intermediate tone mask plate, single exposure, development are carried out to photoresist 17, photoresist is formed, and half retains photoresist region 19, all risk insurance stays photoresist region 18 and full removal photoresist region 20, half retains photoresist region 19 comprises source electrode region, drain regions and pixel electrode area, all risk insurance stays photoresist region 18 to comprise area of grid, except half reservation photoresist region, all risk insurance stay the region except photoresist region to remove photoresist region 20 for complete.
S502, the grid film etching away full removal photoresist region 20 correspondence, grid insulating film and metal oxide thin films.
Etching away the full grid film removing photoresist region 20 correspondence can use the gaseous mixture of SF6 and O2 or the gaseous mixture of Cl2 and O2 to carry out dry etching, etching away the full grid insulating film removing photoresist region 20 correspondence can use the gaseous mixture of CF4 and O2 to carry out dry etching, etches away the full metal oxide thin films removing photoresist region 20 correspondence and can utilize wet etching.
S503, by first time cineration technics, remove the photoresist that half retains photoresist region 19, and remove the part photoresist that all risk insurance stays photoresist region 18.
S504, the grid film etching away half reservation photoresist region 19 correspondence and grid insulating film, to form by described grid film the figure comprising grid, formed the figure comprising gate insulator by described grid insulating film.
The grid film etching away half reservation photoresist region 19 correspondence also can use the gaseous mixture of SF6 and O2 or the gaseous mixture of Cl2 and O2 to carry out dry etching, and the grid insulating film etching away half reservation photoresist region 19 correspondence also can use the gaseous mixture of CF4 and O2 to carry out dry etching.
S505, by photoresist stripping process, remove all risk insurance and stay the photoresist in photoresist region 18.
The method is through a patterning processes, be formed with active layer on the substrate respectively and be positioned at the figure of pixel electrode area, source electrode region, drain regions, also form gate insulator and grid, simple to operate, convenient and swift, also reduce production cost.
Further preferably, described metal oxide thin films is IGZO (Indium Gallium Zinc Oxide, indium gallium zinc oxide) film.Described IGZO film can use sputtering method film forming, during described sputtering method film forming, passes into Ar and O
2, described O
2the percent by volume accounting for total gas is 15%-30%.
Source electrode, drain electrode are formed by IGZO thin layer, and instead of the opaque metallic film of prior art, the method directly increases the transmitance of array base palte, and then improve the integral finish rate of display.IGZO is a kind of amorphous oxides containing indium, gallium and zinc, carrier mobility is 20 ~ 30 times of amorphous silicon, the active layer formed by IGZO film, greatly can improve the charge-discharge velocity of TFT to pixel electrode, improve the response speed of pixel, realize refresh rate faster, respond the line scanning rate also substantially increasing pixel faster simultaneously; Because carrier mobility is higher, reduce the power consumption of display, and the TFT area that same current flows through just can reduce, wiring also can subtract thin, and the area of lightproof part reduces, and can obtain very large aperture opening ratio.
In addition, when IGZO film carries out conductor, can use equipment at dry quarter, utilize the composition gas of SF6 and He or only use He to carry out ionization (Plasma) process to IGZO film, ionization duration is generally 20s-60s; Or use the composition gas of CF4 and O2 to carry out ionize process to IGZO film at dry quarter in equipment, duration can be 20s-60s.Conductorization can improve the carrier mobility of IGZO film, reduces power consumption further.
Preferably, the material of described interlayer medium film is the nitride (SiNx) of silicon.The nitride film of silicon is generated by silane (SiH4) and ammonia (NH3), and containing hydrogen (H) in the nitride of silicon (SiNx).Hydrogen (H) is through diffusion, can combine by oxygen (O) in the IGZO thin layer corresponding with pixel electrode figure, source electrode figure and drain electrode patterns, thus make IGZO thin layer corresponding to pixel electrode area, source electrode region and drain regions carry out conductor.When making interlayer medium film, use the nitride (SiNx) of silicon to make the IGZO film exposed carry out conductor, eliminate the step of separately the IGZO film exposed being carried out to conductor, thus improve production efficiency, reduce production cost.
A kind of thin-film transistor is provided in another embodiment of the present invention, comprises: substrate; On the substrate with active layer, source electrode, drain electrode that layer is arranged; Be positioned at the gate insulator on described active layer; Be positioned at the grid on described gate insulator; Described active layer, source electrode, drain electrode, gate insulator and grid are formed by a patterning processes, and described source electrode is connected with described drain electrode by described active layer.
In the thin-film transistor that the embodiment of the present invention provides, active layer wherein, source electrode, drain electrode, pixel electrode is arranged on same layer, gate insulator is positioned on active layer, grid is positioned on gate insulator, simplify the structure of the array base palte of prior art, facilitate active layer, source electrode, drain electrode, pixel electrode, gate insulator and grid are formed by a patterning processes, and active layer, source electrode, drain electrode, pixel electrode, gate insulator and grid are formed by a patterning processes, decrease the number of mask in thin-film transistor manufacture craft, shorten the Production Time of thin-film transistor, improve the make efficiency of thin-film transistor, reduce the production cost of thin-film transistor.
A kind of manufacture method of thin-film transistor is provided in another embodiment of the present invention, comprises the following steps:
Substrate stacks gradually and makes metal oxide thin films, grid insulating film, grid film;
By a patterning processes, described metal oxide thin films is formed and includes active layer and be positioned at the figure of source electrode region, drain regions, described grid insulating film is formed the figure comprising gate insulator, described grid film is formed the figure comprising grid; Described source electrode is connected with described drain electrode by described active layer;
The described figure being positioned at source electrode region and drain regions is carried out conductor, forms source electrode and drain electrode.
In the manufacture method of the thin-film transistor that the embodiment of the present invention provides, it is by stacked film forming and a patterning processes and conductor step, obtained active layer, source electrode, drain electrode are at same layer, gate insulator is positioned on active layer, grid is positioned on gate insulator, the method reduces the number of mask in thin-film transistor manufacture craft, shortens the Production Time of thin-film transistor, improve the make efficiency of thin-film transistor, reduce the production cost of thin-film transistor.
A kind of display unit comprising array base palte described in above-mentioned either a program is provided in another embodiment of the present invention.
In the display unit that the embodiment of the present invention provides, active layer wherein, source electrode, drain electrode, pixel electrode is arranged on same layer, gate insulator is positioned on active layer, grid is positioned on gate insulator, simplify the structure of the display unit of prior art, facilitate active layer, source electrode, drain electrode, pixel electrode, gate insulator and grid are formed by a patterning processes, and active layer, source electrode, drain electrode, pixel electrode, gate insulator and grid are formed by a patterning processes, decrease the number of mask in display unit manufacture craft, shorten the Production Time of display unit, improve the make efficiency of display unit, reduce the production cost of display unit.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range described in claim.
Claims (15)
1. an array base palte, comprises substrate, it is characterized in that, also comprises:
On the substrate with active layer, source electrode, drain electrode, pixel electrode that layer is arranged;
Be positioned at the gate insulator on described active layer;
Be positioned at the grid on described gate insulator;
Described active layer, source electrode, drain electrode, pixel electrode, gate insulator and grid are formed by a patterning processes, and described source electrode is connected with described drain electrode by described active layer.
2. array base palte according to claim 1, is characterized in that, also comprises:
Be positioned at the inter-level dielectric on described pixel electrode, source electrode, drain electrode, grid, described inter-level dielectric comprises the via hole of corresponding described source electrode;
Be positioned at the data wire on described inter-level dielectric, described data wire is connected with described source electrode by described via hole.
3. array base palte according to claim 2, is characterized in that, also comprises:
Be positioned at the passivation layer on described data wire and described inter-level dielectric;
Be positioned at the public electrode on described passivation layer.
4. array base palte according to claim 3, is characterized in that, also comprises: be positioned at the organic resin layer on described passivation layer, and described public electrode is positioned on described organic resin layer.
5. a manufacture method for array base palte, is characterized in that, comprises the following steps:
Substrate stacks gradually and makes metal oxide thin films, grid insulating film, grid film;
By a patterning processes, described metal oxide thin films is formed and includes active layer and be positioned at the figure of pixel electrode area, source electrode region, drain regions, described grid insulating film is formed the figure comprising gate insulator, described grid film is formed the figure comprising grid; Described source electrode is connected with described drain electrode by described active layer;
By being describedly positioned at pixel electrode area, the figure of source electrode region and drain regions carries out conductor, forms pixel electrode, source electrode and drain electrode.
6. the manufacture method of array base palte according to claim 5, is characterized in that, also comprises after described formation pixel electrode, source electrode and drain electrode:
Make the interlayer medium film covering described pixel electrode, source electrode, drain electrode, grid, described interlayer medium film is formed by a patterning processes inter-level dielectric comprising via hole, the corresponding described source electrode of described via hole;
Make the data wire film covering described via hole, described data wire film is formed by a patterning processes figure comprising data wire, described data wire is connected with described source electrode by described via hole.
7. the manufacture method of array base palte according to claim 6, is characterized in that, described by patterning processes described data wire film formed comprise the figure of data wire after also comprise:
Make the passivation layer film covering described data wire and described inter-level dielectric, by a patterning processes, described passivation layer film is formed passivation layer;
Described passivation layer makes public electrode film, described public electrode film is formed by a patterning processes figure comprising public electrode.
8. the manufacture method of array base palte according to claim 7, is characterized in that, describedly by patterning processes, described passivation layer film is formed passivation layer and comprises:
Make the organic resin film covering described passivation layer film;
Retained by the organic resin of described organic resin film in passivation layer region, the organic resin in other regions is removed, and forms organic resin layer;
The passivation layer film exposed is removed, forms passivation layer;
The described public electrode film that makes on described passivation layer is specially: on described organic resin layer, make public electrode film.
9. the manufacture method of array base palte according to claim 7, it is characterized in that, described by patterning processes described public electrode film to be formed comprise the figure of public electrode after, array substrate carries out annealing in process, and described annealing temperature is 200 DEG C-250 DEG C.
10. the manufacture method of array base palte according to claim 5, is characterized in that,
Describedly pass through a patterning processes, described metal oxide thin films is formed and includes active layer and be positioned at the figure of pixel electrode area, source electrode region, drain regions, described grid insulating film is formed the figure comprising gate insulator, described grid film is formed the figure comprising grid, comprises the following steps:
Described grid film applies photoresist; By intermediate tone mask plate, single exposure, development are carried out to photoresist, photoresist is formed, and half retains photoresist region, all risk insurance stays photoresist region and full removal photoresist region, described half retains photoresist region comprises source electrode region, drain regions and pixel electrode area, described all risk insurance stays photoresist region to comprise area of grid, except half reservation photoresist region, all risk insurance stay the region except photoresist region to remove photoresist region for complete;
Etch away grid film, grid insulating film and metal oxide thin films that full removal photoresist region is corresponding;
By first time cineration technics, remove the photoresist that half retains photoresist region, and remove the part photoresist that all risk insurance stays photoresist region;
Etch away described half and retain grid film corresponding to photoresist region and grid insulating film, to form by described grid film the figure comprising grid, formed the figure comprising gate insulator by described grid insulating film;
By photoresist stripping process, remove the photoresist that described all risk insurance stays photoresist region.
The manufacture method of 11. array base paltes according to claim 5, is characterized in that, described metal oxide thin films is IGZO film.
The manufacture method of 12. array base paltes according to claim 6, is characterized in that, the material of described interlayer medium film comprises SiNx.
13. 1 kinds of thin-film transistors, comprise substrate, it is characterized in that, also comprise:
On the substrate with active layer, source electrode, drain electrode that layer is arranged;
Be positioned at the gate insulator on described active layer;
Be positioned at the grid on described gate insulator;
Described active layer, source electrode, drain electrode, gate insulator and grid are formed by a patterning processes, and described source electrode is connected with described drain electrode by described active layer.
The manufacture method of 14. 1 kinds of thin-film transistors, is characterized in that, comprises the following steps:
Substrate stacks gradually and makes metal oxide thin films, grid insulating film, grid film;
By a patterning processes, described metal oxide thin films is formed and includes active layer and be positioned at the figure of source electrode region, drain regions, described grid insulating film is formed the figure comprising gate insulator, described grid film is formed the figure comprising grid; Described source electrode is connected with described drain electrode by described active layer;
The described figure being positioned at source electrode region and drain regions is carried out conductor, forms source electrode and drain electrode.
15. 1 kinds of display unit comprising the array base palte described in any one of claim 1-4.
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