WO2019095562A1

WO2019095562A1 - Method for manufacturing tft substrate

Info

Publication number: WO2019095562A1
Application number: PCT/CN2018/074991
Authority: WO
Inventors: 韦显旺
Original assignee: 深圳市华星光电技术有限公司
Priority date: 2017-11-14
Filing date: 2018-02-01
Publication date: 2019-05-23
Also published as: CN107910351A; CN107910351B

Abstract

The present invention relates to the field of display manufacturing. Provided is a method for manufacturing a TFT substrate (100). By means of a zone exposure process, on an oxide semi-conductor layer (20) are a semi-conductor area (011) formed corresponding to a gate electrode (051) and conductor areas (021) formed corresponding to areas of a source electrode (0210), a drain electrode (0211) and a pixel electrode (0212) successively, and the remaining parts correspond to the position of an insulating area after same are removed. In comparison to a manufacturing method in the prior art, the TFT substrate (100) needing to be formed by means of four photoetching processes is formed instead in three photoetching processes, thus omitting one photoetching process flow, simplifying the process and improving the production efficiency.

Description

TFT substrate manufacturing method

Technical field

The present invention relates to the field of display technologies, and in particular, to the fabrication of a TFT substrate.

Background technique

Organic Light Emitting Display (OLED) has self-luminous, no backlight, high contrast, thin thickness, wide viewing angle, fast response, flexible panel, wide temperature range, Excellent features such as simple construction and process are considered to be the emerging application technologies for next-generation flat panel displays. In the production of large-size OLED panels, oxide semiconductors have higher electron mobility, and compared to low-temperature polysilicon (LTPS), oxide semiconductors have simple process, high compatibility with amorphous silicon processes, and high generations. The production line is compatible and has been widely used.

At present, a common structure of an oxide semiconductor thin film transistor (TFT) substrate is an etch barrier layer (ESL) structure, but the structure itself has certain problems, mainly in the required mask and lithography process. More, increased process time and process complexity.

Summary of the invention

An object of the present invention is to provide a method for fabricating a TFT substrate that reduces the number of masks and shortens the process flow, and provides the following technical solutions:

Providing a substrate;

Depositing an oxide semiconductor layer on one side of the substrate;

Forming a photoresist layer covering the oxide semiconductor layer;

Partition exposure patterning the photoresist layer to expose opposite portions of the oxide semiconductor layer;

Conducting two opposite portions of the oxide semiconductor layer, one of which forms a source, and the other portion forms a drain and a pixel electrode electrically connected to the drain;

The photoresist layer remaining after the patterning is removed, and the oxide semiconductor layer covered by the photoresist layer remaining after being patterned forms a channel region.

Wherein the oxide semiconductor layer is deposited on the substrate, and after forming the channel region, the method further comprises the steps of:

Depositing an insulating layer;

Patterning the insulating layer to form two connection holes on the insulating layer to penetrate the insulating layer to expose the source and the drain;

Depositing a metal layer;

Patterning the metal layer to form a gate, a gate line, a source line, and a drain line, the gate and the gate line being electrically connected, the gate being disposed corresponding to the channel region, The source line is connected to the source through the connection hole, the drain line is connected to the drain through another connection hole, and the source line is spaced apart from the gate and the gate line The drain line is spaced apart from the gate and the gate line.

Wherein, before depositing the oxide semiconductor layer on the substrate, the method further comprises the following steps:

A buffer layer is deposited on the substrate.

Wherein, before depositing the oxide semiconductor layer, the following steps are further included:

Providing a substrate;

Depositing a metal layer on the substrate;

Patterning the metal layer to form a gate, a gate line, a source line, and a drain line;

Depositing an insulating layer;

Patterning the insulating layer, defining two connection holes, the connection holes penetrating through the insulating layer, respectively connecting the source line and the drain line;

When the opposite portions of the oxide semiconductor layer are conductorized, the source is connected to the source line, the drain and the drain line are connected, and the channel region corresponds to the gate Extreme setting.

Wherein, in depositing the oxide semiconductor layer, the connection hole is filled with the oxide semiconductor layer.

Among them, the action of depositing the oxide semiconductor layer is achieved by a physical vapor deposition method.

Wherein, the material of the oxide semiconductor layer is IGZO.

Among them, the action of partitioning the exposed oxide semiconductor layer is realized by a halftone process.

Wherein, the plasma of the conductord half-exposed area is helium or argon.

Wherein, a protective layer is deposited after the steps of the above method are completed.

In the method for fabricating a TFT substrate of the present invention, after depositing the oxide semiconductor layer, a semiconductor is formed on the oxide semiconductor layer by a portionwise exposure method, and a region corresponding to the source, the drain, and the pixel electrode is formed on the oxide semiconductor layer. The conductor is formed, and the remaining area is removed by wet etching, corresponding to the position of the insulating region. Compared with the prior art manufacturing method, the TFT substrate which is required to be formed by four photolithography processes is compressed into three photolithography processes, thereby eliminating a photolithography process flow, simplifying the process, and improving the production efficiency.

DRAWINGS

1 is a schematic flow chart of a first embodiment of a method for fabricating a TFT substrate of the present invention;

2 is a schematic view showing a step of depositing an oxide semiconductor in a method of fabricating a TFT substrate of the present invention;

3 is a schematic view showing a coating photoresist of a method for fabricating a TFT substrate of the present invention;

4 is a schematic view showing a partial exposure of a method for fabricating a TFT substrate of the present invention;

5 is a schematic view showing the removal of photoresist by the method for fabricating the TFT substrate of the present invention;

6 is a schematic view showing a conductor forming process of a method for fabricating a TFT substrate of the present invention;

7 is a schematic view showing a method of fabricating a TFT substrate of the present invention;

8 is a schematic plan view showing the method of fabricating the TFT substrate of the present invention;

9 is a schematic flow chart of a second embodiment of a method for fabricating a TFT substrate of the present invention;

10 is a schematic view showing an insulating layer of a second embodiment of a method for fabricating a TFT substrate of the present invention;

11 is a schematic view showing a second embodiment of a method for fabricating a TFT substrate of the present invention;

12 is a schematic plan view showing a second embodiment of a method for fabricating a TFT substrate of the present invention after defining a connection hole;

13 is a schematic view showing a metal layer of a second embodiment of a method for fabricating a TFT substrate of the present invention;

FIG. 14 is a schematic view showing the second embodiment of the method for fabricating the TFT substrate of the present invention; FIG.

Figure 15 is a plan view showing the second embodiment of the method for fabricating the TFT substrate of the present invention;

16 is a schematic view showing a second embodiment of a method for fabricating a TFT substrate of the present invention;

17 is a schematic flow chart of a third embodiment of a method for fabricating a TFT substrate of the present invention;

18 is a schematic view showing a third embodiment of a method for fabricating a TFT substrate of the present invention with all photoresist layers removed;

Fig. 19 is a schematic view showing the third embodiment of the method for fabricating the TFT substrate of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

Referring to the flowchart of the method for fabricating the TFT substrate 100 of FIG. 1 , the manufacturing method of the first embodiment of the present invention specifically includes the following steps:

S11. Providing a substrate 10;

Specifically, the substrate 10 may be a transparent substrate, such as glass, plastic or the like.

S12. Depositing an oxide semiconductor layer 20 on one side of the substrate 10;

Specifically, as shown in FIG. 2, the material of the oxide semiconductor layer 20 may be IGZO, which may be deposited by physical vapor deposition, and the oxide semiconductor layer 20 may be deposited on the substrate 10 or deposited on the substrate. On the structural layer other than the substrate 10, such as a buffer layer or an insulating layer.

S13. forming a photoresist layer 21 covering the oxide semiconductor layer 20;

Specifically, as shown in FIG. 3, a coating is formed on the surface of the oxide semiconductor layer 20 to form the photoresist layer 21.

S14. The oxide semiconductor layer 20 is subjected to partial exposure, and the photoresist layer 21 is patterned to expose opposite portions of the oxide semiconductor layer 20;

Specifically, the halftone process is employed, that is, the photoresist layer 21 is subjected to partial exposure using a halftone. Referring to FIG. 4, the half palette includes, in addition to the unexposed portion and the half exposed portion, and of course, a portion of the full exposure may be included. Such an arrangement can form three kinds of exposure results of the photoresist layer 21 full exposure region 03, half exposure region 02, and non-exposure region 01 in one exposure process.

Specifically, the position of the unexposed area 01 corresponds to a portion of the gate electrode 051 to be formed on the TFT substrate, and the position of the half-exposure area 02 corresponds to the source 0210, the drain electrode 0211, and the pixel electrode 0212 of the TFT substrate to be formed. In the region, the position of the fully exposed region 03 corresponds to the region of the insulating layer 031 where the TFT substrate is to be formed. The correspondence of the positions in the present description is the correspondence relationship between the upper and lower layers of each structural layer, that is, the corresponding relationship of the projected areas of the respective structural layers on the substrate 10.

Removing the photoresist layer 21 on the fully exposed region 03 by a wet etching process, and graying out the remaining photoresist layer 21, at which time the non-exposed region 01 and the half-exposed region 02 are further The photoresist layer 21 is left, see FIG. 5. It can be understood that the thickness of the photoresist layer 21 at the non-exposed area 01 is greater than the thickness of the photoresist layer 21 at the half-exposed area 02. Thicker, so in the process of ashing the photoresist layer 21, by setting and controlling the depth of ashing, when the oxide semiconductor layer 20 at the half-exposed region 02 is exposed, the non-exposure The photoresist layer 21 at the region 01 also has a portion remaining. At this time, the half-exposure region 02 is divided into a portion to form the source electrode 0210, and the portion of the drain electrode 0211 and the pixel electrode region 0212 is to be formed, and the two portions are relatively independent.

S 15. The opposite portions of the oxide semiconductor layer 20 are conductorized, a part of which forms a source 0210, and another part forms a drain electrode 0211 and a pixel electrode 0212 electrically connected to the drain electrode 0211;

Specifically, for the two opposite portions of the exposed oxide semiconductor layer 20 to be electrically conductive, a helium gas or an argon plasma is generally used, and the process conditions are a cavity pressure of 10 to 150 mT, an RF energy of 800 to 10000 W, and a gas flow rate. 200 to 4000 sccm. Referring to FIG. 6, the conductive oxide semiconductor layer 20 is changed from a first all-semiconductor state to a "conductor-semiconductor-conductor" state, at which time the source electrode 0210 and the drain electrode 0211 are formed. And the pixel electrode 0212, see FIG.

S16. The patterned photoresist layer 21 is removed, and the oxide semiconductor layer 20 covered by the patterned photoresist layer 21 serves as a channel region 011.

Specifically, the remaining photoresist layer 21 at the oxide semiconductor layer 20 is removed by ashing, and the oxide semiconductor layer 20 includes a conductor 021 and a semiconductor channel region 011, as shown in FIG. The semiconductor exists as the channel region 011 structure of the TFT substrate. The position of the channel region 011 corresponds to the position of the gate electrode 051, and the function of the TFT substrate is ensured.

In the method of fabricating a TFT substrate of the present invention, the area exposure is performed on the oxide semiconductor layer 20, and the conductor 021 including the source electrode 0210, the drain electrode 0211, and the pixel electrode 0212 is formed at a time, and The semiconductor having the channel region 011 structure corresponding to the position of the gate electrode 051 also forms a space of the insulating layer 031 so that each sub-pixel region exists independently and can perform a normal function. The method can be combined with the fabrication of the gate layer 051 and the source lines 040, the drain lines 041 and the like to reduce a photolithography process and simplify the fabrication process of the conventional planar oxide semiconductor TFT substrate.

Figure 9 is a second embodiment of a method of fabricating a planar oxide semiconductor TFT substrate of the present invention, the specific steps are as follows:

S201. Providing a substrate 10;

S202. depositing a buffer layer on the substrate 10;

Specifically, the buffer layer may be a silicon oxide buffer layer, which is not shown in the drawing. The buffer layer is mainly used for the effects of contaminants, bending stress and the like encountered in the subsequent process of the barrier-type oxide semiconductor TFT substrate. In some embodiments, under the premise that the process conditions are better controlled, the buffer layer may not be disposed to save manufacturing time.

S203. depositing the oxide semiconductor layer 20 on the buffer layer;

Specifically, as shown in FIG. 2, the material of the oxide semiconductor layer 20 may be IGZO, and the deposition manner thereof may be physical vapor deposition specific, as shown in FIG. 2, the material of the oxide semiconductor layer 20 may be IGZO, and deposition thereof. The mode can be physical vapor deposition.

S204. Forming a photoresist layer 21 covering the oxide semiconductor layer 20;

Specifically, as shown in FIG. 3, the photoresist layer 21 is coated on the surface of the oxide semiconductor layer 20.

S205. Performing a partial exposure on the oxide semiconductor layer 20, and patterning the photoresist layer 21 to expose opposite portions of the oxide semiconductor layer 20;

Removing the photoresist layer 21 on the fully exposed region 03 by a wet etching process, and graying out the remaining photoresist layer 21, at which time the non-exposed region 01 and the half-exposed region 02 are further The photoresist layer 21 is left, see FIG. 5. It can be understood that the thickness of the photoresist layer 21 at the non-exposed area 01 is greater than the thickness of the photoresist layer 21 at the half-exposed area 02. Thicker, so in the process of ashing the photoresist layer 21, by setting and controlling the depth of ashing, when the oxide semiconductor layer 20 at the half-exposed region 02 is exposed, the non-exposure The photoresist layer 21 at the region 01 also has a portion remaining. At this time, the half-exposure region 02 is divided into a portion where the source electrode 0210 is to be formed, and another portion of the drain electrode 0211 and the pixel electrode region 0212 is to be formed, and the two portions are relatively independent.

S206. Conducting the opposite portions of the oxide semiconductor layer 20, a portion of which forms a source 0210, and another portion forms a drain electrode 0211 and a pixel electrode 0212 electrically connected to the drain electrode 0211;

Specifically, for the exposed two portions of the oxide semiconductor layer 20 to be electrically conductive, a helium gas or an argon plasma is generally used, and the process conditions are a cavity pressure of 10 to 150 mT, an RF energy of 800 to 10000 W, and a gas flow rate of 200. ~4000sccm. Referring to FIG. 6, the conductive oxide semiconductor layer 20 is changed from a first all-semiconductor state to a "conductor-semiconductor-conductor" state, at which time the source electrode 0210 and the drain electrode 0211 are formed. And the pixel electrode 0212, see FIG.

S207. The patterned photoresist layer 21 is removed, and the oxide semiconductor layer 20 covered by the patterned photoresist layer 21 becomes the channel region 011.

S208 depositing an insulating layer 031;

Specifically, as shown in FIG. 10, the insulating layer 031 needs to completely cover the entire range of the sub-pixel region.

S209. The insulating layer 031 is patterned to form two connection holes 04 on the insulating layer 031, through the insulating layer 031 to expose the source 0210 and the drain 0211;

Specifically, the pattern of the connection holes 04 is defined by photolithography, and here, the photomask is used for the second time in the method of manufacturing the TFT substrate of the present invention. Referring to FIGS. 11 and 12, the shape of the connection hole 04 is etched on the insulating layer 031 by a dry etching process, that is, the material of the insulating layer 031 in the pattern of the connection hole 04 is removed, so that The conductor 021 in the lower portion of the insulating layer 031, that is, the source electrode 0210 and the drain electrode 0211 are exposed, one of the connection holes 04 communicates with the source 0210, and the other of the connection holes 04 communicates with the drain Pole 021.

S210. Depositing a metal layer 05;

Specifically, a metal layer 05 is further deposited on the insulating layer 031, and the connection hole 04 needs to be filled with the metal layer 05 to turn on the path of the conductor 021 to the metal layer 05. See Figure 13. It can be understood that the metal layer 05 is connected to the source 0210 and the drain 0211 portion of the conductor 021.

S211. Patterning the metal layer 05 to form a gate electrode 051, a gate line 052, a source line 040, and a drain line 041, the gate 051 and the gate line 052 being electrically connected, the gate 051 is corresponding to the channel region 011, the source line 040 is connected to the source 0210 through the connection hole 04, and the drain line 041 is connected to the drain 0211 through another connection hole 04. The source line 040 is spaced apart from the gate 051 and the gate line 052, and the drain line 041 is spaced apart from the gate 051 and the gate line 052;

Specifically, a pattern of the gate electrode 051, the gate line 052, the source line 040, and the drain line 041 is defined on the metal layer 05 by photolithography. Specifically, as shown in FIGS. 14 and 15, the gate electrode 051, the gate line 052, the source line 040, and the drain line 041 are formed by a wet etching process using a defined pattern. Here, the photomask is used for the third time in the method of manufacturing the TFT substrate of the present invention.

The gate electrode 051 is disposed corresponding to the channel region 011, the source line 040 is connected to the source electrode 0210 through the connection hole 04, and the drain line 041 is connected to the other through the connection hole 04. The drain line 0211 is spaced apart from the gate electrode 051 and the gate line 052, and the drain line 041 is spaced apart from the gate electrode 051 and the gate line 052.

S212. Depositing a protective layer 06.

Specifically, as shown in FIG. 16, after all the structural layers are completely prepared, a protective layer 06 is deposited on top to protect the TFT substrate of the present invention. It can be understood that in some embodiments, the function of the TFT substrate can also be realized without depositing the protective layer 06.

A third embodiment of a method for fabricating a planar oxide semiconductor TFT substrate of the present invention is shown in FIG. 17, and includes the following steps:

S301. Providing a substrate 10;

S302. depositing a metal layer 05 on the substrate 10;

Specifically, the metal layer 05 is directly deposited on the substrate 10.

S303. The metal layer 05 is patterned, and a gate electrode 051, a gate line 052 and a source line 040, and the drain line 041 are defined;

Specifically, the shape of the gate electrode 051, the gate line 052, the source line 040, and the drain line 041 is formed by photolithography and/or wet etching. It can be understood that the photomask is used for the first time in this embodiment.

S304. Depositing an insulating layer 031;

Specifically, the insulating layer 031 is deposited over the gate electrode 051, the gate line 052, the source line 040, and the drain line 041.

S305. Patterning the insulating layer 031 to define two connection holes 04 penetrating through the insulating layer 031 to respectively connect the source line 040 and the drain line 041.

The insulating layer 031 is patterned to define and form a pattern of the connection holes 04. It can be understood that the position of the connection hole 04 is at the position of the source line 040 and the drain line 041. It can be understood that the photomask is used for the second time in this embodiment. Specifically, the shape of the connection hole 04 is etched on the insulating layer 031 by a dry etching process, that is, the material of the insulating layer 031 in the pattern of the connection hole 04 is removed, so that the insulating layer The source line 040 and the drain line 041 in the lower portion of 031 are exposed.

S306. Depositing an oxide semiconductor layer 20 on the insulating layer 031;

Specifically, the material of the oxide semiconductor layer 20 may be IGZO, and the deposition manner may be physical vapor deposition. It can be understood that the oxide semiconductor layer 20 fills the connection hole 40 during deposition, and turns on the source line 040 and the drain line 041.

S307. Forming a photoresist layer 21 covering the oxide semiconductor layer 20;

Specifically, the photoresist layer 21 is coated on the surface of the oxide semiconductor layer 20.

S308. The oxide semiconductor layer 20 is subjected to partial exposure, and no exposure is performed in a region corresponding to the gate electrode 051, and is performed in a region of the source line 040 and the drain line 0211 and the pixel electrode 0212. Half exposure, fully exposed in the rest of the area;

Specifically, the halftone process is employed, that is, the photoresist layer 21 is subjected to partial exposure using a halftone. The half palette includes a part of the half exposure portion in addition to the fully exposed portion and the non-exposed portion, and the photoresist layer 21 can be formed in the entire exposure process by the full exposure region 03, the half exposure region 02, and the non-exposure. Three exposure results for area 01.

Specifically, the position of the unexposed area 01 corresponds to the portion of the gate 051 of the embodiment, and the position of the half-exposure area 02 corresponds to the source 0210, the drain 0211, and the The area of the pixel electrode 0212, the position of the fully exposed area 03 corresponds to the area of the insulating layer 031 of the present embodiment. It can be understood that the correspondence of the positions in the present description is the upper and lower correspondence relationship between the structural layers, that is, the corresponding relationship of the projected areas of the respective structural layers on the substrate 10.

It can be understood that the photomask is used for the third time in this embodiment.

Specifically, the photoresist layer 21 on the fully exposed region 03 is removed by a wet etching process.

Specifically, the photoresist layer 21 is ashed, and the photoresist layer 21 is left on the non-exposed area 01 and the half-exposed area 02. It can be understood that the non-exposed area 01 The thickness of the photoresist layer 21 is thicker than the thickness of the photoresist layer 21 at the half-exposed region 02, so by setting and controlling the gray during the ashing of the photoresist layer 21 The depth of the photoresist layer 21 at the unexposed area 01 is still partially left when the oxide semiconductor layer 20 at the half-exposed area 02 is exposed.

S309. The semi-exposed area 02 is processed into a conductor 021 by a conductor process using a plasma to form the source electrode 0210, the drain electrode 0211, and the pixel electrode 0212;

Specifically, for the exposed oxide semiconductor layer 20 to be conductorized, helium gas or argon plasma is usually used, and the conditions of the process are a cavity pressure of 10 to 150 mT, an RF energy of 800 to 10000 W, and a gas flow rate of 200 to 4000 sccm. The conductive oxide semiconductor layer 20 is changed from a first all-semiconductor state to a "conductor-semiconductor-conductor" state, at which time the source electrode 0210, the drain electrode 0211, and the pixel electrode 0212 are formed. . When the opposite portions of the oxide semiconductor layer are conductorized, the source electrode 0210 is connected to the source line 040, the drain electrode 0211 and the drain line 041 are connected to the channel. The region, that is, the semiconductor 011, is disposed corresponding to the gate 051.

S310. Removing the remaining photoresist layer 21 of the portion of the non-exposed area 01;

Specifically, the remaining photoresist layer 21 at the oxide semiconductor layer 20 is removed by ashing, and the oxide semiconductor layer 20 includes a conductor 021 and a semiconductor. The semiconductor exists as a channel region 011 structure of the TFT substrate, see FIG. The position of the channel region 011 corresponds to the position of the gate electrode 051, and the function of the TFT substrate is ensured.

S311. Depositing a protective layer 60.

Specifically, as shown in FIG. 19, after all the structural layers are completely prepared, a protective layer 06 is deposited on the upper layer to protect the planar oxide semiconductor TFT substrate. It can be understood that in some embodiments, the function of the TFT substrate can also be realized without depositing the protective layer 06.

In the method for fabricating a TFT substrate of the present invention, a semiconductor is formed on the oxide semiconductor layer corresponding to the gate electrode by a process of the partition exposure process, a conductor is formed in a region corresponding to the source, the drain, and the pixel electrode, and the remaining portion is wet-etched. After removal, the position of the corresponding insulation zone. Compared with the prior art manufacturing method, the TFT substrate which is required to be formed by four photolithography processes is compressed into three photolithography processes, thereby eliminating a photolithography process flow, simplifying the process, and improving the production efficiency.

The embodiments described above do not constitute a limitation on the scope of protection of the technical solutions. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the above-described embodiments are intended to be included within the scope of the technical solutions.

Claims

A method for fabricating a TFT substrate, wherein the method for fabricating the TFT substrate comprises:

Providing a substrate;

Depositing an oxide semiconductor layer on one side of the substrate;

Forming a photoresist layer covering the oxide semiconductor layer;

Partition exposure patterning the photoresist layer to expose opposite portions of the oxide semiconductor layer;

Conducting two opposite portions of the oxide semiconductor layer, one of which forms a source, and the other portion forms a drain and a pixel electrode electrically connected to the drain;

The photoresist layer remaining after the patterning is removed, and the oxide semiconductor layer covered by the photoresist layer remaining after being patterned forms a channel region.
The method of fabricating a TFT substrate according to claim 1, wherein the oxide semiconductor layer is deposited on the substrate, and after forming the channel region, the method further comprises the steps of:

Depositing an insulating layer;

Patterning the insulating layer to form two connection holes on the insulating layer to penetrate the insulating layer to expose the source and the drain;

Depositing a metal layer;

Patterning the metal layer to form a gate, a gate line, a source line, and a drain line, the gate and the gate line being electrically connected, the gate being disposed corresponding to the channel region, The source line is connected to the source through the connection hole, the drain line is connected to the drain through another connection hole, and the source line is spaced apart from the gate and the gate line The drain line is spaced apart from the gate and the gate line.
The method of fabricating a TFT substrate according to claim 2, further comprising the steps of: depositing said oxide semiconductor layer on said substrate:

A buffer layer is deposited on the substrate.
A method of fabricating a TFT substrate according to claim 1, further comprising the steps of: before depositing said oxide semiconductor layer:

Providing a substrate;

Depositing a metal layer on the substrate;

Patterning the metal layer to form a gate, a gate line, a source line, and a drain line;

Depositing an insulating layer;

Patterning the insulating layer, defining two connection holes, the connection holes penetrating through the insulating layer, respectively connecting the source line and the drain line;

When the opposite portions of the oxide semiconductor layer are conductorized, the source is connected to the source line, the drain and the drain line are connected, and the channel region corresponds to the gate Extreme setting.
The method of fabricating a TFT substrate according to claim 4, wherein, in depositing the oxide semiconductor layer, the connection hole is filled with the oxide semiconductor layer.
The method of fabricating a TFT substrate according to claim 1, wherein the action of depositing the oxide semiconductor layer is performed by a physical vapor deposition method.
The method of fabricating a TFT substrate according to claim 1, wherein the material of the oxide semiconductor layer is IGZO.
The method of fabricating a TFT substrate according to claim 1, wherein the operation of partitioning the exposed oxide semiconductor layer is performed by a halftone process.
The method of fabricating a TFT substrate according to claim 1, wherein the plasma in the conductive half-exposure region is helium or argon.
A method of fabricating a TFT substrate according to claim 1, wherein a protective layer is deposited after all the method steps are completed.