WO2019095562A1 - Procédé de fabrication de substrat tft - Google Patents

Procédé de fabrication de substrat tft Download PDF

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Publication number
WO2019095562A1
WO2019095562A1 PCT/CN2018/074991 CN2018074991W WO2019095562A1 WO 2019095562 A1 WO2019095562 A1 WO 2019095562A1 CN 2018074991 W CN2018074991 W CN 2018074991W WO 2019095562 A1 WO2019095562 A1 WO 2019095562A1
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Prior art keywords
oxide semiconductor
layer
semiconductor layer
tft substrate
fabricating
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PCT/CN2018/074991
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English (en)
Chinese (zh)
Inventor
韦显旺
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深圳市华星光电技术有限公司
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Publication of WO2019095562A1 publication Critical patent/WO2019095562A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/125—Active-matrix OLED [AMOLED] displays including organic TFTs [OTFT]

Definitions

  • the present invention relates to the field of display technologies, and in particular, to the fabrication of a TFT substrate.
  • OLED Organic Light Emitting Display
  • OLED has self-luminous, no backlight, high contrast, thin thickness, wide viewing angle, fast response, flexible panel, wide temperature range, Excellent features such as simple construction and process are considered to be the emerging application technologies for next-generation flat panel displays.
  • oxide semiconductors have higher electron mobility, and compared to low-temperature polysilicon (LTPS), oxide semiconductors have simple process, high compatibility with amorphous silicon processes, and high generations. The production line is compatible and has been widely used.
  • LTPS low-temperature polysilicon
  • a common structure of an oxide semiconductor thin film transistor (TFT) substrate is an etch barrier layer (ESL) structure, but the structure itself has certain problems, mainly in the required mask and lithography process. More, increased process time and process complexity.
  • ESL etch barrier layer
  • An object of the present invention is to provide a method for fabricating a TFT substrate that reduces the number of masks and shortens the process flow, and provides the following technical solutions:
  • the photoresist layer remaining after the patterning is removed, and the oxide semiconductor layer covered by the photoresist layer remaining after being patterned forms a channel region.
  • the oxide semiconductor layer is deposited on the substrate, and after forming the channel region, the method further comprises the steps of:
  • the metal layer to form a gate, a gate line, a source line, and a drain line, the gate and the gate line being electrically connected, the gate being disposed corresponding to the channel region,
  • the source line is connected to the source through the connection hole
  • the drain line is connected to the drain through another connection hole
  • the source line is spaced apart from the gate and the gate line
  • the drain line is spaced apart from the gate and the gate line.
  • the method further comprises the following steps:
  • a buffer layer is deposited on the substrate.
  • connection holes Patterning the insulating layer, defining two connection holes, the connection holes penetrating through the insulating layer, respectively connecting the source line and the drain line;
  • the source is connected to the source line, the drain and the drain line are connected, and the channel region corresponds to the gate Extreme setting.
  • connection hole is filled with the oxide semiconductor layer.
  • the action of depositing the oxide semiconductor layer is achieved by a physical vapor deposition method.
  • the material of the oxide semiconductor layer is IGZO.
  • the action of partitioning the exposed oxide semiconductor layer is realized by a halftone process.
  • the plasma of the conductord half-exposed area is helium or argon.
  • a protective layer is deposited after the steps of the above method are completed.
  • a semiconductor is formed on the oxide semiconductor layer by a portionwise exposure method, and a region corresponding to the source, the drain, and the pixel electrode is formed on the oxide semiconductor layer.
  • the conductor is formed, and the remaining area is removed by wet etching, corresponding to the position of the insulating region.
  • FIG. 1 is a schematic flow chart of a first embodiment of a method for fabricating a TFT substrate of the present invention
  • FIG. 2 is a schematic view showing a step of depositing an oxide semiconductor in a method of fabricating a TFT substrate of the present invention
  • FIG. 3 is a schematic view showing a coating photoresist of a method for fabricating a TFT substrate of the present invention
  • FIG. 4 is a schematic view showing a partial exposure of a method for fabricating a TFT substrate of the present invention
  • FIG. 5 is a schematic view showing the removal of photoresist by the method for fabricating the TFT substrate of the present invention
  • FIG. 6 is a schematic view showing a conductor forming process of a method for fabricating a TFT substrate of the present invention
  • FIG. 7 is a schematic view showing a method of fabricating a TFT substrate of the present invention.
  • FIG. 8 is a schematic plan view showing the method of fabricating the TFT substrate of the present invention.
  • FIG. 9 is a schematic flow chart of a second embodiment of a method for fabricating a TFT substrate of the present invention.
  • FIG. 10 is a schematic view showing an insulating layer of a second embodiment of a method for fabricating a TFT substrate of the present invention.
  • FIG. 11 is a schematic view showing a second embodiment of a method for fabricating a TFT substrate of the present invention.
  • FIG. 12 is a schematic plan view showing a second embodiment of a method for fabricating a TFT substrate of the present invention after defining a connection hole;
  • FIG. 13 is a schematic view showing a metal layer of a second embodiment of a method for fabricating a TFT substrate of the present invention.
  • FIG. 14 is a schematic view showing the second embodiment of the method for fabricating the TFT substrate of the present invention.
  • Figure 15 is a plan view showing the second embodiment of the method for fabricating the TFT substrate of the present invention.
  • 16 is a schematic view showing a second embodiment of a method for fabricating a TFT substrate of the present invention.
  • FIG. 17 is a schematic flow chart of a third embodiment of a method for fabricating a TFT substrate of the present invention.
  • FIG. 18 is a schematic view showing a third embodiment of a method for fabricating a TFT substrate of the present invention with all photoresist layers removed;
  • Fig. 19 is a schematic view showing the third embodiment of the method for fabricating the TFT substrate of the present invention.
  • the manufacturing method of the first embodiment of the present invention specifically includes the following steps:
  • the substrate 10 may be a transparent substrate, such as glass, plastic or the like.
  • the material of the oxide semiconductor layer 20 may be IGZO, which may be deposited by physical vapor deposition, and the oxide semiconductor layer 20 may be deposited on the substrate 10 or deposited on the substrate.
  • the structural layer other than the substrate 10 such as a buffer layer or an insulating layer.
  • a coating is formed on the surface of the oxide semiconductor layer 20 to form the photoresist layer 21.
  • the oxide semiconductor layer 20 is subjected to partial exposure, and the photoresist layer 21 is patterned to expose opposite portions of the oxide semiconductor layer 20;
  • the halftone process is employed, that is, the photoresist layer 21 is subjected to partial exposure using a halftone.
  • the half palette includes, in addition to the unexposed portion and the half exposed portion, and of course, a portion of the full exposure may be included.
  • Such an arrangement can form three kinds of exposure results of the photoresist layer 21 full exposure region 03, half exposure region 02, and non-exposure region 01 in one exposure process.
  • the position of the unexposed area 01 corresponds to a portion of the gate electrode 051 to be formed on the TFT substrate
  • the position of the half-exposure area 02 corresponds to the source 0210, the drain electrode 0211, and the pixel electrode 0212 of the TFT substrate to be formed.
  • the position of the fully exposed region 03 corresponds to the region of the insulating layer 031 where the TFT substrate is to be formed.
  • the correspondence of the positions in the present description is the correspondence relationship between the upper and lower layers of each structural layer, that is, the corresponding relationship of the projected areas of the respective structural layers on the substrate 10.
  • the photoresist layer 21 Removing the photoresist layer 21 on the fully exposed region 03 by a wet etching process, and graying out the remaining photoresist layer 21, at which time the non-exposed region 01 and the half-exposed region 02 are further
  • the photoresist layer 21 is left, see FIG. 5. It can be understood that the thickness of the photoresist layer 21 at the non-exposed area 01 is greater than the thickness of the photoresist layer 21 at the half-exposed area 02. Thicker, so in the process of ashing the photoresist layer 21, by setting and controlling the depth of ashing, when the oxide semiconductor layer 20 at the half-exposed region 02 is exposed, the non-exposure
  • the photoresist layer 21 at the region 01 also has a portion remaining. At this time, the half-exposure region 02 is divided into a portion to form the source electrode 0210, and the portion of the drain electrode 0211 and the pixel electrode region 0212 is to be formed, and the two portions are relatively independent.
  • the opposite portions of the oxide semiconductor layer 20 are conductorized, a part of which forms a source 0210, and another part forms a drain electrode 0211 and a pixel electrode 0212 electrically connected to the drain electrode 0211;
  • a helium gas or an argon plasma is generally used, and the process conditions are a cavity pressure of 10 to 150 mT, an RF energy of 800 to 10000 W, and a gas flow rate. 200 to 4000 sccm.
  • the conductive oxide semiconductor layer 20 is changed from a first all-semiconductor state to a "conductor-semiconductor-conductor" state, at which time the source electrode 0210 and the drain electrode 0211 are formed.
  • the pixel electrode 0212 see FIG.
  • the patterned photoresist layer 21 is removed, and the oxide semiconductor layer 20 covered by the patterned photoresist layer 21 serves as a channel region 011.
  • the remaining photoresist layer 21 at the oxide semiconductor layer 20 is removed by ashing, and the oxide semiconductor layer 20 includes a conductor 021 and a semiconductor channel region 011, as shown in FIG.
  • the semiconductor exists as the channel region 011 structure of the TFT substrate.
  • the position of the channel region 011 corresponds to the position of the gate electrode 051, and the function of the TFT substrate is ensured.
  • the area exposure is performed on the oxide semiconductor layer 20, and the conductor 021 including the source electrode 0210, the drain electrode 0211, and the pixel electrode 0212 is formed at a time, and
  • the semiconductor having the channel region 011 structure corresponding to the position of the gate electrode 051 also forms a space of the insulating layer 031 so that each sub-pixel region exists independently and can perform a normal function.
  • the method can be combined with the fabrication of the gate layer 051 and the source lines 040, the drain lines 041 and the like to reduce a photolithography process and simplify the fabrication process of the conventional planar oxide semiconductor TFT substrate.
  • Figure 9 is a second embodiment of a method of fabricating a planar oxide semiconductor TFT substrate of the present invention, the specific steps are as follows:
  • the substrate 10 may be a transparent substrate, such as glass, plastic or the like.
  • the buffer layer may be a silicon oxide buffer layer, which is not shown in the drawing.
  • the buffer layer is mainly used for the effects of contaminants, bending stress and the like encountered in the subsequent process of the barrier-type oxide semiconductor TFT substrate.
  • the buffer layer may not be disposed to save manufacturing time.
  • the material of the oxide semiconductor layer 20 may be IGZO, and the deposition manner thereof may be physical vapor deposition specific, as shown in FIG. 2, the material of the oxide semiconductor layer 20 may be IGZO, and deposition thereof.
  • the mode can be physical vapor deposition.
  • the photoresist layer 21 is coated on the surface of the oxide semiconductor layer 20.
  • the halftone process is employed, that is, the photoresist layer 21 is subjected to partial exposure using a halftone.
  • the half palette includes, in addition to the unexposed portion and the half exposed portion, and of course, a portion of the full exposure may be included.
  • Such an arrangement can form three kinds of exposure results of the photoresist layer 21 full exposure region 03, half exposure region 02, and non-exposure region 01 in one exposure process.
  • the photoresist layer 21 Removing the photoresist layer 21 on the fully exposed region 03 by a wet etching process, and graying out the remaining photoresist layer 21, at which time the non-exposed region 01 and the half-exposed region 02 are further
  • the photoresist layer 21 is left, see FIG. 5. It can be understood that the thickness of the photoresist layer 21 at the non-exposed area 01 is greater than the thickness of the photoresist layer 21 at the half-exposed area 02. Thicker, so in the process of ashing the photoresist layer 21, by setting and controlling the depth of ashing, when the oxide semiconductor layer 20 at the half-exposed region 02 is exposed, the non-exposure
  • the photoresist layer 21 at the region 01 also has a portion remaining. At this time, the half-exposure region 02 is divided into a portion where the source electrode 0210 is to be formed, and another portion of the drain electrode 0211 and the pixel electrode region 0212 is to be formed, and the two portions are relatively independent
  • the exposed two portions of the oxide semiconductor layer 20 to be electrically conductive, a helium gas or an argon plasma is generally used, and the process conditions are a cavity pressure of 10 to 150 mT, an RF energy of 800 to 10000 W, and a gas flow rate of 200. ⁇ 4000sccm.
  • the conductive oxide semiconductor layer 20 is changed from a first all-semiconductor state to a "conductor-semiconductor-conductor" state, at which time the source electrode 0210 and the drain electrode 0211 are formed.
  • the pixel electrode 0212 see FIG.
  • the patterned photoresist layer 21 is removed, and the oxide semiconductor layer 20 covered by the patterned photoresist layer 21 becomes the channel region 011.
  • the remaining photoresist layer 21 at the oxide semiconductor layer 20 is removed by ashing, and the oxide semiconductor layer 20 includes a conductor 021 and a semiconductor channel region 011, as shown in FIG.
  • the semiconductor exists as the channel region 011 structure of the TFT substrate.
  • the position of the channel region 011 corresponds to the position of the gate electrode 051, and the function of the TFT substrate is ensured.
  • the insulating layer 031 needs to completely cover the entire range of the sub-pixel region.
  • the insulating layer 031 is patterned to form two connection holes 04 on the insulating layer 031, through the insulating layer 031 to expose the source 0210 and the drain 0211;
  • the pattern of the connection holes 04 is defined by photolithography, and here, the photomask is used for the second time in the method of manufacturing the TFT substrate of the present invention.
  • the shape of the connection hole 04 is etched on the insulating layer 031 by a dry etching process, that is, the material of the insulating layer 031 in the pattern of the connection hole 04 is removed, so that The conductor 021 in the lower portion of the insulating layer 031, that is, the source electrode 0210 and the drain electrode 0211 are exposed, one of the connection holes 04 communicates with the source 0210, and the other of the connection holes 04 communicates with the drain Pole 021.
  • a metal layer 05 is further deposited on the insulating layer 031, and the connection hole 04 needs to be filled with the metal layer 05 to turn on the path of the conductor 021 to the metal layer 05. See Figure 13. It can be understood that the metal layer 05 is connected to the source 0210 and the drain 0211 portion of the conductor 021.
  • the metal layer 05 to form a gate electrode 051, a gate line 052, a source line 040, and a drain line 041, the gate 051 and the gate line 052 being electrically connected, the gate 051 is corresponding to the channel region 011, the source line 040 is connected to the source 0210 through the connection hole 04, and the drain line 041 is connected to the drain 0211 through another connection hole 04.
  • the source line 040 is spaced apart from the gate 051 and the gate line 052, and the drain line 041 is spaced apart from the gate 051 and the gate line 052;
  • a pattern of the gate electrode 051, the gate line 052, the source line 040, and the drain line 041 is defined on the metal layer 05 by photolithography.
  • the gate electrode 051, the gate line 052, the source line 040, and the drain line 041 are formed by a wet etching process using a defined pattern.
  • the photomask is used for the third time in the method of manufacturing the TFT substrate of the present invention.
  • the gate electrode 051 is disposed corresponding to the channel region 011, the source line 040 is connected to the source electrode 0210 through the connection hole 04, and the drain line 041 is connected to the other through the connection hole 04.
  • the drain line 0211 is spaced apart from the gate electrode 051 and the gate line 052, and the drain line 041 is spaced apart from the gate electrode 051 and the gate line 052.
  • a protective layer 06 is deposited on top to protect the TFT substrate of the present invention. It can be understood that in some embodiments, the function of the TFT substrate can also be realized without depositing the protective layer 06.
  • FIG. 17 A third embodiment of a method for fabricating a planar oxide semiconductor TFT substrate of the present invention is shown in FIG. 17, and includes the following steps:
  • the substrate 10 may be a transparent substrate, such as glass, plastic or the like.
  • the metal layer 05 is directly deposited on the substrate 10.
  • the metal layer 05 is patterned, and a gate electrode 051, a gate line 052 and a source line 040, and the drain line 041 are defined;
  • the shape of the gate electrode 051, the gate line 052, the source line 040, and the drain line 041 is formed by photolithography and/or wet etching. It can be understood that the photomask is used for the first time in this embodiment.
  • the insulating layer 031 is deposited over the gate electrode 051, the gate line 052, the source line 040, and the drain line 041.
  • the insulating layer 031 is patterned to define and form a pattern of the connection holes 04. It can be understood that the position of the connection hole 04 is at the position of the source line 040 and the drain line 041. It can be understood that the photomask is used for the second time in this embodiment. Specifically, the shape of the connection hole 04 is etched on the insulating layer 031 by a dry etching process, that is, the material of the insulating layer 031 in the pattern of the connection hole 04 is removed, so that the insulating layer The source line 040 and the drain line 041 in the lower portion of 031 are exposed.
  • the material of the oxide semiconductor layer 20 may be IGZO, and the deposition manner may be physical vapor deposition. It can be understood that the oxide semiconductor layer 20 fills the connection hole 40 during deposition, and turns on the source line 040 and the drain line 041.
  • the photoresist layer 21 is coated on the surface of the oxide semiconductor layer 20.
  • the oxide semiconductor layer 20 is subjected to partial exposure, and no exposure is performed in a region corresponding to the gate electrode 051, and is performed in a region of the source line 040 and the drain line 0211 and the pixel electrode 0212. Half exposure, fully exposed in the rest of the area;
  • the halftone process is employed, that is, the photoresist layer 21 is subjected to partial exposure using a halftone.
  • the half palette includes a part of the half exposure portion in addition to the fully exposed portion and the non-exposed portion, and the photoresist layer 21 can be formed in the entire exposure process by the full exposure region 03, the half exposure region 02, and the non-exposure. Three exposure results for area 01.
  • the position of the unexposed area 01 corresponds to the portion of the gate 051 of the embodiment
  • the position of the half-exposure area 02 corresponds to the source 0210, the drain 0211, and the The area of the pixel electrode 0212
  • the position of the fully exposed area 03 corresponds to the area of the insulating layer 031 of the present embodiment. It can be understood that the correspondence of the positions in the present description is the upper and lower correspondence relationship between the structural layers, that is, the corresponding relationship of the projected areas of the respective structural layers on the substrate 10.
  • photomask is used for the third time in this embodiment.
  • the photoresist layer 21 on the fully exposed region 03 is removed by a wet etching process.
  • the photoresist layer 21 is ashed, and the photoresist layer 21 is left on the non-exposed area 01 and the half-exposed area 02. It can be understood that the non-exposed area 01
  • the thickness of the photoresist layer 21 is thicker than the thickness of the photoresist layer 21 at the half-exposed region 02, so by setting and controlling the gray during the ashing of the photoresist layer 21
  • the depth of the photoresist layer 21 at the unexposed area 01 is still partially left when the oxide semiconductor layer 20 at the half-exposed area 02 is exposed.
  • the semi-exposed area 02 is processed into a conductor 021 by a conductor process using a plasma to form the source electrode 0210, the drain electrode 0211, and the pixel electrode 0212;
  • the exposed oxide semiconductor layer 20 to be conductorized, helium gas or argon plasma is usually used, and the conditions of the process are a cavity pressure of 10 to 150 mT, an RF energy of 800 to 10000 W, and a gas flow rate of 200 to 4000 sccm.
  • the conductive oxide semiconductor layer 20 is changed from a first all-semiconductor state to a "conductor-semiconductor-conductor" state, at which time the source electrode 0210, the drain electrode 0211, and the pixel electrode 0212 are formed. .
  • the source electrode 0210 is connected to the source line 040
  • the drain electrode 0211 and the drain line 041 are connected to the channel.
  • the region, that is, the semiconductor 011 is disposed corresponding to the gate 051.
  • the remaining photoresist layer 21 at the oxide semiconductor layer 20 is removed by ashing, and the oxide semiconductor layer 20 includes a conductor 021 and a semiconductor.
  • the semiconductor exists as a channel region 011 structure of the TFT substrate, see FIG.
  • the position of the channel region 011 corresponds to the position of the gate electrode 051, and the function of the TFT substrate is ensured.
  • a protective layer 06 is deposited on the upper layer to protect the planar oxide semiconductor TFT substrate. It can be understood that in some embodiments, the function of the TFT substrate can also be realized without depositing the protective layer 06.
  • a semiconductor is formed on the oxide semiconductor layer corresponding to the gate electrode by a process of the partition exposure process, a conductor is formed in a region corresponding to the source, the drain, and the pixel electrode, and the remaining portion is wet-etched. After removal, the position of the corresponding insulation zone.
  • the TFT substrate which is required to be formed by four photolithography processes is compressed into three photolithography processes, thereby eliminating a photolithography process flow, simplifying the process, and improving the production efficiency.

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  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)

Abstract

La présente invention se rapporte au domaine de la fabrication d'affichage. L'invention concerne un procédé de fabrication d'un substrat TFT (100). Au moyen d'un procédé d'exposition de zone, une zone semi-conductrice (011) formée correspondant à une électrode de grille (051) et des zones conductrices (021) formées correspondant à des zones d'une électrode de source (0210), d'une électrode de drain (0211) et d'une électrode de pixel (0212) sont successivement formées sur une couche semi-conductrice d'oxyde (20), et les parties restantes correspondent à la position d'une zone isolante après que ces dernières ont été retirées. Par rapport à un procédé de fabrication de l'état de la technique, le substrat TFT (100) devant être formé au moyen de quatre processus de photogravure est formé à la place par trois processus de photogravure, ce qui permet d'omettre un flux de production de photogravure, de simplifier le processus et d'améliorer l'efficacité de production.
PCT/CN2018/074991 2017-11-14 2018-02-01 Procédé de fabrication de substrat tft WO2019095562A1 (fr)

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CN201711124844.7A CN107910351B (zh) 2017-11-14 2017-11-14 Tft基板的制作方法

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CN109994530B (zh) 2019-03-28 2021-01-26 云谷（固安）科技有限公司 显示装置、显示面板及其制作方法
CN110718467B (zh) * 2019-09-24 2021-12-03 Tcl华星光电技术有限公司 一种tft阵列基板的制作方法
CN111180471A (zh) * 2020-03-02 2020-05-19 南京中电熊猫平板显示科技有限公司 阵列基板及其制造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102023424A (zh) * 2009-09-09 2011-04-20 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
US20130320335A1 (en) * 2012-06-01 2013-12-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
CN103715094A (zh) * 2013-12-27 2014-04-09 京东方科技集团股份有限公司 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置
CN104393051A (zh) * 2014-10-31 2015-03-04 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板
CN104681627A (zh) * 2015-03-10 2015-06-03 京东方科技集团股份有限公司 阵列基板、薄膜晶体管及制作方法、显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007103418A (ja) * 2005-09-30 2007-04-19 Seiko Epson Corp 半導体装置、半導体装置の製造方法、並びに電気光学装置
KR100964227B1 (ko) * 2008-05-06 2010-06-17 삼성모바일디스플레이주식회사 평판 표시 장치용 박막 트랜지스터 어레이 기판, 이를포함하는 유기 발광 표시 장치, 및 이들의 제조 방법
CN101825815B (zh) * 2009-03-06 2013-02-13 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
CN102890378B (zh) * 2012-09-17 2015-01-21 京东方科技集团股份有限公司 一种阵列基板及其制造方法
CN105118777A (zh) * 2015-07-01 2015-12-02 深圳市华星光电技术有限公司 Tft背板的制作方法及其结构
CN106384714B (zh) * 2016-10-13 2018-07-10 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102023424A (zh) * 2009-09-09 2011-04-20 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
US20130320335A1 (en) * 2012-06-01 2013-12-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
CN103715094A (zh) * 2013-12-27 2014-04-09 京东方科技集团股份有限公司 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置
CN104393051A (zh) * 2014-10-31 2015-03-04 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板
CN104681627A (zh) * 2015-03-10 2015-06-03 京东方科技集团股份有限公司 阵列基板、薄膜晶体管及制作方法、显示装置

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