CN102890378B - 一种阵列基板及其制造方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 80
- 239000000758 substrate Substances 0.000 title claims abstract description 67
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 238000009413 insulation Methods 0.000 claims abstract description 32
- 238000002161 passivation Methods 0.000 claims abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims description 106
- 239000010408 film Substances 0.000 claims description 58
- 238000000059 patterning Methods 0.000 claims description 48
- 239000010409 thin film Substances 0.000 claims description 41
- 239000000463 material Substances 0.000 claims description 28
- 239000004065 semiconductor Substances 0.000 claims description 20
- 238000011161 development Methods 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 18
- HTCXJNNIWILFQQ-UHFFFAOYSA-M emmi Chemical compound ClC1=C(Cl)C2(Cl)C3C(=O)N([Hg]CC)C(=O)C3C1(Cl)C2(Cl)Cl HTCXJNNIWILFQQ-UHFFFAOYSA-M 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 238000005229 chemical vapour deposition Methods 0.000 claims description 11
- 238000005516 engineering process Methods 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 8
- 150000002739 metals Chemical class 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 6
- 229910045601 alloy Inorganic materials 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 230000008020 evaporation Effects 0.000 claims description 6
- 238000001704 evaporation Methods 0.000 claims description 6
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
- 239000011733 molybdenum Substances 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- JAONJTDQXUSBGG-UHFFFAOYSA-N dialuminum;dizinc;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Al+3].[Al+3].[Zn+2].[Zn+2] JAONJTDQXUSBGG-UHFFFAOYSA-N 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims description 3
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical group O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 claims description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 2
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 3
- 239000007789 gas Substances 0.000 description 15
- 239000011248 coating agent Substances 0.000 description 11
- 238000000576 coating method Methods 0.000 description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- -1 molybdenum Mo Chemical class 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 241000931705 Cicada Species 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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Abstract
本发明实施例涉及液晶显示器的制造领域,特别涉及一种阵列基板及其制造方法。本发明实施例的方法包括:采用灰色调或半色调掩膜板,通过第一次构图工艺,在衬底基板上依次形成栅线和栅电极、第一绝缘层、有源层及欧姆接触层;采用灰色调或半色调掩膜板,通过第二次构图工艺,在完成上述步骤的衬底基板上,依次形成第二绝缘层和像素电极;采用灰色调或半色调掩膜板,通过第三次构图工艺,在完成上述步骤的衬底基板上,依次形成漏电极和源电极、数据线以及钝化层。本发明实施例通过三次构图工艺即可完成阵列基板的制备,缩短了生产周期,降低了生产成本,提高了生产效率。
Description
技术领域
本发明涉及液晶显示器的制造领域,特别涉及一种阵列基板及其制造方法。
背景技术
薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display,TFT-LCD)具有体积小、功耗低、无辐射等优点,在当前的平板显示器市场中占据了主导地位,广泛应用于台式电脑、笔记本电脑、个人数字助理(PersonalDigital Assistant,PDA)、手机、电视、监视器等领域。对于TFT-LCD来说,阵列基板的结构及其制造工艺决定了TFT-LCD的产品性能、成品率和价格。
目前,TFT-LCD阵列基板的制造都是通过多次构图工艺形成薄膜图形来完成的,以形成一层薄膜图形。为了有效地降低TFT-LCD的价格、提高TFT-LCD的成品率,TFT-LCD阵列基板的制造工艺逐步得到简化,由开始的需要经过七次构图工艺形成已经发展到基于灰色调掩模板光刻(Gray Tone Mask)技术的四次构图工艺形成。现有的四次构图工艺利用灰色调或半灰色调掩膜板技术,通过一次构图工艺完成有源层、数据线、源电极、漏电极和薄膜晶体管沟道区域图形的制作。
由于每一次构图工艺中一般都包括掩膜、曝光、显影、刻蚀和剥离等工艺,所以构图工艺的次数可以衡量制造TFT-LCD阵列基板的繁简程度,在TFT-LCD阵列基板制造过程中,采用的构图工艺的次数越少,则生产时间就越短、生产效率就越高、制造成本也就越低。
发明内容
本发明实施例提供了一种阵列基板及其制造方法,采用三次构图工艺实现阵列基板的制造,缩短生产周期,降低生产成本,提高生产效率。
本发明实施例提供了一种阵列基板,包括:
位于衬底基板上的栅电极和栅线;
所述栅电极和栅线上依次覆盖有第一绝缘层、有源层及欧姆接触层,其中,所述有源层与所述欧姆接触层形成薄膜晶体管TFT沟道;
所述TFT沟道上覆盖有第二绝缘层,在所述衬底基板上除所述第二绝缘层覆盖的区域外的其他区域上覆盖有像素电极,其中,所述第二绝缘层上的欧姆接触层对应位置上分别形成有接触孔,部分所述像素电极通过所述接触孔与所述欧姆接触层接触;
所述第二绝缘层上覆盖有漏电极、源电极及数据线,其中,所述漏电极与所述像素电极接触;
所述漏电极、源电极及数据线上覆盖有钝化层。
本发明实施例提供了一种阵列基板的制造方法,包括:
步骤1:采用灰色调或半色调掩膜板,通过一次构图工艺,在衬底基板上依次形成栅线和栅电极、第一绝缘层、有源层及欧姆接触层,其中,所述有源层及所述欧姆接触层构成薄膜晶体管TFT沟道区域;
步骤2:采用灰色调或半色调掩膜板,通过一次构图工艺,在完成步骤1的衬底基板上,依次形成第二绝缘层和像素电极;
步骤3:采用灰色调或半色调掩膜板,通过一次构图工艺,在完成步骤2的衬底基板上,依次形成漏电极和源电极、数据线以及钝化层。
本发明实施例通过三次构图工艺即可完成阵列基板的制备,缩短了生产周期,降低了生产成本,提高了生产效率;本发明实施例阵列基板的制造方法工艺过程简单、可靠,易于实现,具有广泛的应用前景。
附图说明
图1为本发明实施例灰色调或半色调掩膜板的原理示意图;
图2为本发明实施例阵列基板的剖面结构示意图;
图3本发明实施例阵列基板制造方法的流程示意图;
图4为本发明实施例阵列基板制造方法中的第一次构图工艺流程示意图;
图5A为本发明实施例第一次构图工艺中,在衬底基板上沉积各薄膜层后的剖面结构示意图;
图5B为本发明实施例第一次构图工艺中,阵列基板的TFT区域涂覆光刻胶后的剖面结构示意图;
图5C为本发明实施例第一次构图工艺中,阵列基板的TFT区域的光刻胶进行曝光、显影处理后的剖面结构示意图;
图5D为本发明实施例第一次构图工艺后,阵列基板的TFT区域的剖面结构示意图;
图5E为本发明实施例第一次构图工艺后,阵列基板的栅线所在区域的剖面结构示意图;
图6为本发明实施例阵列基板制造方法中的第二次构图工艺流程示意图;
图7A为本发明实施例第二次构图工艺中,在沉积了第二绝缘层薄膜的阵列基板的TFT区域涂覆光刻胶后的剖面结构图;
图7B为本发明实施例第二次构图工艺中,在沉积了第二绝缘层薄膜的阵列基板的栅线所在区域涂覆光刻胶后的剖面结构图;
图7C为本发明实施例第二次构图工艺中,阵列基板的TFT区域的光刻胶进行曝光、显影处理后的剖面结构示意图;
图7D为本发明实施例第二次构图工艺中,阵列基板的栅线所在区域的光刻胶进行曝光、显影处理后的剖面结构示意图;
图7E为本发明实施例第二次构图工艺中,对第二光刻胶完全去除区域进行刻蚀处理后,栅线所在区域的剖面结构示意图;
图7F为本发明实施例第二次构图工艺中,对第二光刻胶半保留区域进行刻蚀处理后,TFT区域的剖面结构示意图;
图7G为本发明实施例第二次构图工艺后,阵列基板的TFT区域的剖面结构示意图;
图7H为本发明实施例第二次构图工艺后,阵列基板的栅线所在区域的剖面结构示意图;
图8为本发明实施例阵列基板制造方法中的第三次构图工艺流程示意图;
图9A为本发明实施例第三次构图工艺中,在完成第二次构图工艺后的衬底基板上沉积各薄膜层后的剖面结构示意图;
图9B为本发明实施例第三次构图工艺中,在阵列基板的TFT区域涂覆光刻胶后的剖面结构示意图;
图9C为本发明实施例第三次构图工艺中,在阵列基板的数据线所在区域涂覆光刻胶后的剖面结构图;
图9D为本发明实施例第三次构图工艺中,TFT区域的光刻胶进行曝光、显影处理后的剖面结构图;
图9E为本发明实施例第三次构图工艺中,数据线所在区域的光刻胶进行曝光、显影处理后的剖面结构图;
图9F为本发明实施例第三次构图工艺后,阵列基板的TFT区域的剖面结构示意图。
具体实施方式
本发明通过三次构图工艺即可完成阵列基板的制备,从而缩短了生产周期,降低了生产成本,提高了生产效率。
参见图1,本发明实施例的灰色调或半色调掩膜板的原理为:灰色调或半色调掩模板包括透明的石英玻璃基板g,不透明膜f及半透明膜h,其中,不透明膜f由不透明的挡光材料制作,半透明膜h可允许光线部分透过或者半透过。该灰色调或半色调掩膜板形成有完全不透光区域A、半透光区域B及完全透光区域C。
以正性光刻胶为例,使用时,先在需要形成图形的薄膜材料上涂覆一层光刻胶10,用光源照射该灰色调或半色调掩膜板后,光线无法透过完全不透光区域A,使该区域成为未曝光区域,显影后未曝光区域的光刻胶完全保留,成为光刻胶完全保留区域;约有一半的光线能够透过半透光区域B,使该区域成为半曝光区域,显影后半曝光区域的光刻胶被部分去除,成为光刻胶半保留区域;光线透过完全透光区域C,使该区域成为完全曝光区域,显影后完全曝光区域的光刻胶被完全去除,成为光刻胶完全去除区域。
下面结合说明书附图对本发明实施例作进一步详细描述。
参见图2,本发明实施例提供的阵列基板,包括:
位于衬底基板1上的栅电极2a和栅线(图中未示);
栅电极2a和栅线上依次覆盖有第一绝缘层3、有源层4及欧姆接触层5,其中,有源层4与欧姆接触层5形成TFT沟道;
TFT沟道上覆盖有第二绝缘层6,该第二绝缘层6包裹于TFT沟道外围;在衬底基板1上除第二绝缘层6覆盖的区域外的其他区域上覆盖有像素电极7,其中,第二绝缘层6上的欧姆接触层5对应位置上分别形成有接触孔,部分像素电极7通过该接触孔与欧姆接触层5接触;
第二绝缘层6上覆盖有源电极8a、漏电极8b及数据线(图中未示),其中,漏电极8b与像素电极7接触;
源电极8a、漏电极8b及数据线上覆盖有钝化层9。
进一步,栅电极和栅线的材质为钼Mo、铝Al、铜Cu及钨W等金属中的一种或由至少两种金属形成的合金;
第一绝缘层的材质为氮化硅SiNx及氧化硅SiOx中的一种或组合;
有源层的材质为半导体材质,如非晶型硅(a-Si、a-Si:H)、多晶硅、铟镓锌氧化物(IGZO)或其他用以形成晶体管中电流通道的半导体材料;
欧姆接触层的材质为掺杂半导体材质,如N掺杂硅、P掺杂硅等;
优选的,该掺杂半导体材质为N掺杂硅;
第二绝缘层的材质为氮化硅SiNx及氧化硅SiOx中的一种或组合;
漏电极、源电极及数据线的材质为钼Mo、铝Al、铜Cu及钨W等金属中的一种或由至少两种金属形成的合金;
像素电极的材质为氧化铟锡ITO、氧化铟锌IZO或氧化铝锌等氧化物;
钝化层的材质为氮化硅SiNx及氧化硅SiOx中的一种或组合。
优选的,栅电极、栅线、漏电极、源电极及数据线的材质相同;
第一绝缘层、第二绝缘层及钝化层的材质相同。
参见图3,本发明实施例提供了阵列基板的制造方法,包括以下步骤:
步骤1:采用灰色调或半色调掩膜板,通过一次构图工艺,在衬底基板上依次形成栅线和栅电极、第一绝缘层、有源层及欧姆接触层,其中,有源层及欧姆接触层构成TFT沟道区域;
步骤2:采用灰色调或半色调掩膜板,通过一次构图工艺,在完成步骤1的衬底基板上,依次形成第二绝缘层和像素电极;
步骤3:采用灰色调或半色调掩膜板,通过一次构图工艺,在完成步骤2的衬底基板上,依次形成漏电极和源电极、数据线以及钝化层。
进一步,参见图4,步骤1具体包括:
步骤11:在衬底基板1上依次沉积栅金属薄膜2、第一绝缘层薄膜3、半导体薄膜4及掺杂半导体薄膜5,参见图5A所示;
其中,栅金属薄膜用以形成栅电极和栅线,其厚度为1500埃米~2500埃米,其材质为钼、铝、铜及钨中的一种或由至少两种金属形成的合金;
第一绝缘层薄膜用以形成第一绝缘层,其厚度为2500埃米~4000埃米,其材质为氮化硅及氧化硅中的一种或组合;
半导体薄膜用以形成有源层,其厚度为800埃米~1500埃米;
掺杂半导体薄膜用以形成欧姆接触层,其厚度为500埃米~1000埃米。
步骤12:在完成步骤11的衬底基板1上涂覆光刻胶10,参见图5B所示;采用灰色调或半色调掩膜板进行曝光、显影处理,形成第一光刻胶完全保留区域A、第一光刻胶半保留区域B及第一光刻胶完全去除区域C,参见图5C所示;
其中,第一光刻胶完全保留区域A对应栅线和栅电极所在区域,第一光刻胶半保留区域B对应TFT沟道区域中除栅电极之外的区域,第一光刻胶完全去除区域C对应衬底基板上除上述区域之外的区域;
步骤13:在完成步骤23的衬底基板1上,依次形成栅电极2a和栅线2b、第一绝缘层3以及由有源层4及欧姆接触层5形成的TFT沟道区域,参见图5D和图5E所示,其中,图5D为第一次构图工艺后,TFT区域的剖面结构示意图;图5E为第一次构图工艺后,栅线2b所在区域的剖面结构示意图。
进一步,步骤11具体包括:
采用磁控溅射或热蒸镀的方式,在衬底基板上沉积栅金属薄膜;以及
采用化学气相沉积方式,在完成上述步骤的衬底基板上,依次沉积第一绝缘层薄膜、半导体薄膜及掺杂半导体薄膜;
其中,在采用化学气相沉积方式沉积第一绝缘层薄膜时,对应的反应气体可以是甲烷SiH4、氨气NH3及氮气N2的混合气体,或二氯硅烷SiH2Cl2、NH3及N2的混合气体;
在采用化学气相沉积方式沉积半导体薄膜时,对应的反应气体可以是SiH4和氢气H2的混合气体,或者SiH2Cl2和H2的混合气体;
在采用化学气相沉积方式沉积掺杂半导体时,对应的反应气体可以是SiH4、磷化氢PH3及氮气H2的混合气体,或者SiH2Cl2、PH3和H2的混合气体。
进一步,步骤13具体包括:
通过一次刻蚀工艺,刻蚀掉第一光刻胶完全去除区域对应的栅金属薄膜、第一绝缘层薄膜、半导体薄膜及掺杂半导体薄膜;
通过一次灰化工艺,去除掉第一光刻胶半保留区域的光刻胶;
通过一次刻蚀工艺,刻蚀掉第一光刻胶半保留区域对应的掺杂半导体薄膜,并暴露出半导体薄膜,以形成TFT沟道区域,其中,本步骤中的刻蚀工艺可以为干法刻蚀工艺;以及
通过剥离工艺,剥离掉第一光刻胶完全保留区域的光刻胶。
进一步,参见图6,步骤2具体包括:
步骤21:采用化学气相沉积方式,在完成步骤1的衬底基板1上沉积第二绝缘层薄膜6;
其中,第二绝缘层薄膜用以形成第二绝缘层,其厚度为2500埃米~4000埃米,其材质为氮化硅及氧化硅中的一种或组合;
在采用化学气相沉积方式沉积第二绝缘层薄膜时,对应的反应气体可以是SiH4、NH3和N2的混合气体,或者SiH2Cl2、NH3和N2的混合气体。
步骤22:在完成步骤21的衬底基板1上涂覆光刻胶10,参见图7A和图7B所示,其中,图7A为TFT区域涂覆光刻胶之后的剖面结构图,图7B为栅线2b所在区域涂覆光刻胶之后的剖面结构图;采用灰色调或半色调掩膜板进行曝光、显影处理,以形成第二光刻胶完全保留区域A、第二光刻胶半保留区域B及第二光刻胶完全去除区域C,参见图7C和图7D所示,其中,图7C为TFT区域的光刻胶进行曝光、显影处理后的剖面结构示意图,图7D为栅线2b所在区域的光刻胶进行曝光、显影处理后的剖面结构示意图;
其中,第二光刻胶完全去除区域C对应栅线的引线区域,第二光刻胶半保留区域B对应欧姆接触层及像素电极所在区域,第二光刻胶完全保留区域A对应衬底基板上除上述区域之外的区域;
步骤23:在完成步骤22的衬底基板1上,形成像素电极7。
进一步,步骤23具体包括:
通过一次刻蚀工艺,刻蚀掉第二光刻胶完全去除区域对应的栅线的引线区域上的第二绝缘层薄膜、掺杂半导体薄膜、半导体薄膜及第一绝缘层薄膜,并暴露出栅金属层,参见图7E所示,其中,本步骤中刻蚀工艺可以为干法刻蚀工艺;
通过一次灰化工艺,去除掉第二光刻胶半保留区域的光刻胶;
通过一次刻蚀工艺,刻蚀掉第二光刻胶半保留区域对应的第二绝缘层薄膜,并暴露出掺杂半导体薄膜,参见图7F所示;
采用磁控溅射或热蒸镀的方式,在完成上述步骤的衬底基板上,沉积透明导电薄膜7;其中,透明导电薄膜用以形成像素电极,其厚度为500埃米~1500埃米,其的材质为ITO、IZO或氧化铝锌等氧化物;以及
通过剥离工艺,剥离掉第二光刻胶完全保留区域的光刻胶10,以形成像素电极7,参见图7G和图7H所示,其中,图7G为第二次构图工艺后,阵列基板的TFT区域的剖面结构示意图;图7H为第二次构图工艺后,阵列基板的栅线2b所在区域的剖面结构示意图。
进一步,参见图8,步骤3具体包括:
步骤31:在完成步骤2的衬底基板1上,依次沉积漏源金属膜8及钝化层薄膜9,参见图9A所示;
其中,漏源金属薄膜用以形成漏电极、源电极和数据线,其材质为钼、铝、铜及钨中的一种或由至少两种金属形成的合金,其厚度为1500埃米~2500埃米;
钝化层薄膜用以形成钝化层,其材质为氮化硅及氧化硅中的一种或组合,其厚度为2500埃米~4000埃米。
步骤32:在完成步骤31的衬底基板1上涂覆光刻胶10,参见图9B和图9C所示,其中,图9B为阵列基板的TFT区域涂覆光刻胶后的剖面结构示意图,图9C为阵列基板的数据线所在区域涂覆光刻胶后的剖面结构图;采用灰色调或半色调掩膜板进行曝光、显影处理,形成第三光刻胶完全保留区域A、第三光刻胶半保留区域B及第三光刻胶完全去除区域C,参见图9D和图9E所示,其中,图9D为阵列基板的TFT区域的光刻胶进行曝光、显影处理后的剖面结构图;图9E为阵列基板的数据线所在区域的光刻胶进行曝光、显影处理后的剖面结构图;
其中,第一光刻胶完全保留区域A对应源电极、漏电极及数据线所在区域,第一光刻胶半保留区域B对应数据线的引线区域,第一光刻胶完全去除区域C对应衬底基板上除上述区域之外的区域;
步骤33:在完成步骤32的衬底基板1,依次形成源电极8a和漏电极8b、数据线(图中未示)及钝化层9,参见图9F所示。
进一步,步骤31具体包括:
采用磁控溅射或热蒸镀的方式,在衬底基板上沉积漏源金属薄膜;以及
采用化学气相沉积方式,在完成上述步骤的衬底基板上,沉积钝化层薄膜;
其中,在采用化学气相沉积方式沉积钝化层薄膜时,对应的反应气体可以是SiH4、NH3及氮气N2的混合气体,或SiH2Cl2、NH3及N2的混合气体。
进一步,步骤33具体包括:
通过一次刻蚀工艺,刻蚀掉第三光刻胶完全去除区域对应的钝化层薄膜及漏源金属薄膜;
通过一次灰化工艺,去除掉第三光刻胶半保留区域的光刻胶;
通过一次刻蚀工艺,刻蚀掉第三光刻胶半保留区域对应的钝化层薄膜,暴露出漏源金属薄膜,其中,本步骤中的刻蚀工艺可以为干法刻蚀工艺;以及
通过剥离工艺,剥离掉第三光刻胶完全保留区域的光刻胶,以形成源电极8a和漏电极8b、数据线(图中未示)及钝化层9,参见图9F所示,此时,栅线的引线区也暴露出来。
尽管已描述了本发明的优选实施例,但本领域内的技术人员一旦得知了基本创造性概念,则可对这些实施例作出另外的变更和修改。所以,所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
本发明实施例通过三次构图工艺即可完成阵列基板的制备,缩短了生产周期,降低了生产成本,提高了生产效率;本发明实施例阵列基板的制造方法工艺过程简单、可靠,易于实现,具有广泛的应用前景。
显然,本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。
Claims (13)
1.一种阵列基板,其特征在于,该阵列基板包括:
位于衬底基板上的栅电极和栅线;
所述栅电极和栅线上依次覆盖有第一绝缘层、有源层及欧姆接触层,其中,所述有源层与所述欧姆接触层形成薄膜晶体管TFT沟道;
所述TFT沟道上覆盖有第二绝缘层,在所述衬底基板上除所述第二绝缘层覆盖的区域外的其他区域上覆盖有像素电极,其中,所述第二绝缘层上的欧姆接触层对应位置上分别形成有接触孔,部分所述像素电极通过所述接触孔与所述欧姆接触层接触;
所述第二绝缘层上覆盖有漏电极、源电极及数据线,其中,所述漏电极与所述像素电极接触;
所述漏电极、源电极及数据线上覆盖有钝化层。
2.一种阵列基板的制造方法,其特征在于,该方法包括:
步骤1:采用灰色调或半色调掩膜板,通过第一次构图工艺,在衬底基板上依次形成栅线和栅电极、第一绝缘层、有源层及欧姆接触层,其中,所述有源层及所述欧姆接触层构成薄膜晶体管TFT沟道区域;
步骤2:采用灰色调或半色调掩膜板,通过第二次构图工艺,在完成步骤1的衬底基板上,依次形成第二绝缘层和像素电极;
步骤3:采用灰色调或半色调掩膜板,通过第三次构图工艺,在完成步骤2的衬底基板上,依次形成漏电极和源电极、数据线以及钝化层。
3.如权利要求2所述的方法,其特征在于,所述步骤1具体包括:
步骤11:在所述衬底基板上依次沉积栅金属薄膜、第一绝缘层薄膜、半导体薄膜及掺杂半导体薄膜;
步骤12:在完成步骤11的衬底基板上涂覆光刻胶,并采用灰色调或半色调掩膜板进行曝光、显影处理,形成第一光刻胶完全保留区域、第一光刻胶半保留区域及第一光刻胶完全去除区域;
其中,所述第一光刻胶完全保留区域对应所述栅线和栅电极所在区域,所述第一光刻胶半保留区域对应TFT沟道区域中除所述栅电极之外的区域,所述第一光刻胶完全去除区域对应所述衬底基板上除上述区域之外的区域;
步骤13:在完成步骤12的衬底基板上,依次形成栅线和栅电极、第一绝缘层以及TFT沟道区域,具体包括:
通过一次刻蚀工艺,刻蚀掉所述第一光刻胶完全去除区域对应的栅金属薄膜、第一绝缘层薄膜、半导体薄膜及掺杂半导体薄膜;
通过一次灰化工艺,去除掉所述第一光刻胶半保留区域的光刻胶;
通过一次刻蚀工艺,刻蚀掉所述第一光刻胶半保留区域对应的掺杂半导体薄膜,并暴露出半导体薄膜,以形成所述TFT沟道区域;以及
通过剥离工艺,剥离掉所述第一光刻胶完全保留区域的光刻胶。
4.如权利要求3所述的方法,其特征在于,所述步骤11具体包括:
采用磁控溅射或热蒸镀的方式,在所述衬底基板上沉积栅金属薄膜;以及
采用化学气相沉积方式,在完成上述步骤的衬底基板上,依次沉积第一绝缘层薄膜、半导体薄膜及掺杂半导体薄膜。
5.如权利要求3或4所述的方法,其特征在于,所述栅金属薄膜的厚度为1500埃米~2500埃米;
所述第一绝缘层薄膜的厚度为2500埃米~4000埃米;
所述半导体薄膜的厚度为800埃米~1500埃米;
所述掺杂半导体薄膜的厚度为500埃米~1000埃米。
6.如权利要求3或4所述的方法,其特征在于,所述栅金属薄膜的材质为钼、铝、铜及钨中的一种金属或由至少两种金属形成的合金;
所述第一绝缘层薄膜的材质为氮化硅及氧化硅中的一种或组合。
7.如权利要求2所述的方法,其特征在于,所述步骤2具体包括:
步骤21:采用化学气相沉积方式,在完成步骤1的衬底基板上沉积第二绝缘层薄膜;
步骤22:在完成步骤21的衬底基板上涂覆光刻胶,并采用灰色调或半色调掩膜板进行曝光、显影处理,以形成第二光刻胶完全保留区域、第二光刻胶半保留区域及第二光刻胶完全去除区域;
其中,所述第二光刻胶完全去除区域对应栅线的引线区域,所述第二光刻胶半保留区域对应欧姆接触层及像素电极所在区域,所述第二光刻胶完全保留区域对应所述衬底基板上除上述区域之外的区域;
步骤23:在完成步骤22的衬底基板上,形成像素电极,具体包括:
通过一次刻蚀工艺,刻蚀掉所述第二光刻胶完全去除区域对应的栅线的引线区域上的第二绝缘层薄膜、掺杂半导体薄膜、半导体薄膜及第一绝缘层薄膜,并暴露出栅金属层;
通过一次灰化工艺,去除掉所述第二光刻胶半保留区域的光刻胶;
通过一次刻蚀工艺,刻蚀掉所述第二光刻胶半保留区域对应的第二绝缘层薄膜,并暴露出掺杂半导体薄膜;
采用磁控溅射或热蒸镀的方式,在完成上述步骤的衬底基板上,沉积透明导电薄膜;以及
通过剥离工艺,剥离掉所述第二光刻胶完全保留区域的光刻胶,以形成像素电极。
8.如权利要求7所述的方法,其特征在于,所述第二绝缘层薄膜的厚度为2500埃米~4000埃米;
所述透明导电薄膜的厚度为500埃米~1500埃米。
9.如权利要求7或8所述的方法,其特征在于,所述第二绝缘层薄膜的材质为氮化硅及氧化硅中的一种或组合;
所述透明导电薄膜的材质为氧化铟锡ITO、氧化铟锌IZO或氧化铝锌。
10.如权利要求2所述的方法,其特征在于,所述步骤3具体包括:
步骤31:在完成步骤2的衬底基板上,依次沉积漏源金属膜及钝化层薄膜;
步骤32:在完成步骤31的衬底基板上涂覆光刻胶,并采用灰色调或半色调掩膜板进行曝光、显影处理,形成第三光刻胶完全保留区域、第三光刻胶半保留区域及第三光刻胶完全去除区域;
其中,所述第三光刻胶完全保留区域对应源电极、漏电极及数据线所在区域,所述第三光刻胶半保留区域对应所述数据线的引线区域,所述第三光刻胶完全去除区域对应所述衬底基板上除上述区域之外的区域;
步骤33:在完成步骤32的衬底基板上,依次形成源电极和漏电极、数据线及钝化层,具体包括:
通过一次刻蚀工艺,刻蚀掉所述第三光刻胶完全去除区域对应的钝化层薄膜及漏源金属薄膜;
通过一次灰化工艺,去除掉所述第三光刻胶半保留区域的光刻胶;
通过一次刻蚀工艺,刻蚀掉所述第三光刻胶半保留区域对应的钝化层薄膜,暴露出漏源金属薄膜;以及
通过剥离工艺,剥离掉所述第三光刻胶完全保留区域的光刻胶。
11.如权利要求10所述的方法,其特征在于,所述步骤31具体包括:
采用磁控溅射或热蒸镀的方式,在完成步骤2的衬底基板上沉积漏源金属薄膜;以及
采用化学气相沉积方式,在完成上述步骤的衬底基板上,沉积钝化层薄膜。
12.如权利要求10或11所述的方法,其特征在于,所述漏源金属薄膜的厚度为1500埃米~2500埃米;
所述钝化层薄膜的厚度为2500埃米~4000埃米。
13.如权利要求10或11所述的方法,其特征在于,所述漏源金属薄膜的材质为钼、铝、铜及钨中的一种金属或由至少两种金属形成的合金;
所述钝化层薄膜的材质为氮化硅及氧化硅中的一种或组合。
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