WO2021077673A1 - 阵列基板的制作方法及阵列基板 - Google Patents

阵列基板的制作方法及阵列基板 Download PDF

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WO2021077673A1
WO2021077673A1 PCT/CN2020/080721 CN2020080721W WO2021077673A1 WO 2021077673 A1 WO2021077673 A1 WO 2021077673A1 CN 2020080721 W CN2020080721 W CN 2020080721W WO 2021077673 A1 WO2021077673 A1 WO 2021077673A1
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semiconductor layer
layer
source
drain
manufacturing
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PCT/CN2020/080721
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English (en)
French (fr)
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刘翔
孙学军
李广圣
马群
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成都中电熊猫显示科技有限公司
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Priority to US16/758,435 priority Critical patent/US20220069108A1/en
Publication of WO2021077673A1 publication Critical patent/WO2021077673A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
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    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
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    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/103—Materials and properties semiconductor a-Si

Definitions

  • the present disclosure relates to the field of liquid crystal display technology, and in particular to a manufacturing method of an array substrate and an array substrate.
  • the liquid crystal display panel is generally composed of an array substrate, a color filter substrate, and a liquid crystal molecule layer sandwiched between the array substrate and the color filter substrate.
  • An array substrate manufacturing method known to the applicant includes six photolithography processes, including: the first step: depositing a metal layer on a glass substrate, performing the first photolithography to form a gate; and the second step, sequentially Deposit the gate insulating layer and the indium gallium zinc oxide IGZO semiconductor layer, perform the second photolithography to form the active island pattern; the third step, deposit the etching barrier layer, and perform the third photolithography; the fourth step , Deposit the source and drain metal layers, and perform the fourth photolithography to form the source and drain electrodes; the fifth step, deposit the passivation layer and the planarization layer, and perform the fifth photolithography to form conductive vias ; The sixth step, deposit a transparent conductive film, and perform a sixth photolithography to form a pixel electrode and a connection pattern of the conductive via and the pixel electrode.
  • the above-mentioned manufacturing method for the array substrate includes six photolithography processes, the process is complicated, and the manufacturing cost is high.
  • the present disclosure provides a manufacturing method of an array substrate and an array substrate.
  • the manufacturing of the array substrate can be realized by only four photoetching processes, the process is simple, and the manufacturing cost is low.
  • the embodiment of the present disclosure provides a manufacturing method of an array substrate, including:
  • the gate insulating layer, the first semiconductor layer, the second semiconductor layer, and the source and drain metal layers are sequentially deposited, and the first semiconductor layer and the second semiconductor layer are formed into active islands through the second photolithography process, and at the same time
  • the source-drain metal layer forms a source electrode and a drain electrode, a channel region is formed between the source electrode and the drain electrode, and then the channel region is oxidized to make all the channels located in the channel region
  • the second semiconductor layer is converted into a protective layer;
  • a transparent conductive layer is deposited, and through the fourth photolithography process, the transparent conductive layer is formed into a pixel electrode and the pixel electrode and the drain are connected through the conductive via.
  • the second photolithography process includes a gray tone mask process or a halftone mask process.
  • the second photolithography process specifically includes:
  • the mask is exposed and developed to form a completely transparent region, a partially transparent region, and an opaque region.
  • the opaque region corresponds to the source and the drain, and the partially transparent region corresponds to the The channel area;
  • the source and drain metal layers corresponding to the opaque area are reserved to form the source electrode and the drain electrode.
  • the first semiconductor layer is a metal oxide semiconductor layer, including amorphous indium gallium zinc oxide a-IGZO.
  • the oxygen content in the metal oxide semiconductor layer is reduced to reduce the conductivity of the first semiconductor layer.
  • the second semiconductor layer is a heavily doped amorphous silicon semiconductor layer.
  • the protective layer is silicon oxide.
  • the first semiconductor layer is deposited by a sputtering method
  • the second semiconductor layer is deposited by a plasma-enhanced chemical vapor deposition method.
  • the thickness of the first semiconductor layer is The thickness of the second semiconductor layer is
  • the manufacturing method of the array substrate provided by the embodiments of the present disclosure adopts a metal oxide thin film transistor structure, and uses a halftone or gray tone mask in the second photolithography process to simultaneously form the metal oxide semiconductor layer pattern, source and drain metal Electrodes, data scan lines, and the channel region between the source and drain, and the heavily doped amorphous silicon semiconductor layer in the channel region is oxidized to convert it into silicon oxide, saving 2 times of photolithography The process improves the production efficiency.
  • the double-layer semiconductor layer structure is cleverly designed.
  • the upper layer is a heavily doped amorphous silicon semiconductor layer.
  • the amorphous silicon semiconductor layer is in direct contact with the source and drain metal electrodes, which can reduce the source and drain metal electrodes and semiconductors.
  • the contact resistance of the layer can also protect the underlying metal oxide semiconductor layer from corrosion when forming the source and drain metal electrodes. This design reduces the process difficulty and improves the performance and stability of the thin film transistor.
  • the embodiments of the present disclosure also provide an array substrate, the array substrate is manufactured by the above-mentioned manufacturing method, and the array substrate includes a base substrate and a gate and a gate which are sequentially arranged on the base substrate.
  • the first semiconductor layer is a metal oxide semiconductor layer
  • the second semiconductor layer is a heavily doped amorphous silicon semiconductor layer
  • the channel region has a protective layer
  • the protective layer is the second semiconductor layer Oxide of silicon formed by oxidation treatment
  • the passivation layer has a conductive via hole, and the pixel electrode communicates with the drain electrode through the conductive via hole.
  • the array substrate provided by the embodiments of the present disclosure adopts a double-layer semiconductor layer structure, the upper layer is a heavily doped amorphous semiconductor layer, the lower layer is a metal oxide semiconductor layer with low oxygen content, and the upper amorphous semiconductor layer is directly connected to the source and drain metal electrodes Contact, reducing the contact resistance between the source and drain metal electrodes and the semiconductor layer, while protecting the underlying metal oxide semiconductor layer from being corroded, and at the same time using the oxidation process of heavily doped amorphous silicon to make the amorphous silicon in the channel region Converted into silicon oxide.
  • the oxygen content of the underlying metal oxide semiconductor layer is low, thereby making it conductive Low, which improves the performance and stability of thin film transistors.
  • This design enables the metal oxide semiconductor layer, source and drain metal electrodes, data lines and channel regions to be formed in the same photolithography process, which saves two photolithography processes, and at the same time avoids the etching barrier layer, and reduces the preparation process Difficulty.
  • FIG. 1 is a plan view of an array substrate provided by an embodiment of the disclosure
  • FIG. 2 is a flowchart of a manufacturing method of an array substrate provided by an embodiment of the disclosure
  • FIG. 3 is a schematic diagram of the array substrate along the AB direction after the first photolithography process is completed according to an embodiment of the disclosure
  • FIG. 4 is a schematic structural diagram of the array substrate provided by an embodiment of the disclosure along the AB direction after the exposure and development in the second photolithography process are completed;
  • FIG. 5 is a schematic structural view of the array substrate along the AB direction after the first etching in the second photolithography process according to an embodiment of the disclosure
  • FIG. 6 is a schematic structural diagram along the AB direction of the array substrate provided by an embodiment of the disclosure after the ashing in the second photolithography process is completed;
  • FIG. 7 is a schematic structural diagram along the AB direction of the array substrate provided by an embodiment of the disclosure after the second photolithography process is completed;
  • FIG. 8 is a schematic structural view of the array substrate along the AB direction after the third photolithography process is completed according to an embodiment of the disclosure.
  • FIG. 9 is a schematic structural view of the array substrate provided by an embodiment of the disclosure along the AB direction after the fourth photolithography process is completed.
  • the traditional liquid crystal display panel is composed of a thin film transistor array substrate (TFT Array Substrate, referred to as TFT Array Substrate) and a color film substrate (Color Filter Substrate, referred to as CF Substrate) bonded together.
  • Pixel electrodes and common electrodes are formed on the array substrate and the color filter substrate, and liquid crystal is filled between the array substrate and the color filter substrate.
  • the working principle is to apply a driving voltage between the pixel electrode and the common electrode, and use the pixel electrode and the common electrode.
  • the electric field formed between the clicks controls the rotation of the liquid crystal molecules in the liquid crystal layer, and refracts the light from the backlight module to produce a picture.
  • Mask also known as Photo Mask
  • Photo Mask is a pattern master used in photolithography. It is a mask pattern formed on a transparent substrate by an opaque light-shielding film (metal chromium). The pattern is transferred to the thin film of the glass substrate through a photolithography process.
  • the exposure process is a process in which ultraviolet (Ultraviolet) irradiates the photoresist through the mask to transfer the pattern on the mask to the photoresist.
  • the photoresist acts as a mask, and the photoresist pattern formed by exposure, during the etching process, the thin film layer on the substrate corresponding to the photoresist pattern is retained, and other areas are etched Finally, the photoresist is removed, and the pattern on the mask is transferred to the substrate.
  • This process is called photolithography.
  • Each photolithography process goes through thin film deposition, photoresist coating, exposure, development, The process steps of etching and photoresist stripping.
  • FIG. 1 is a plan view of an array substrate provided by an embodiment of the present disclosure.
  • the array substrate provided by an embodiment of the present disclosure may include a source electrode 161, a drain electrode 162, a passivation layer 22, a conductive via 23, and pixels.
  • FIG. 1 is a plan view of the array substrate. Due to the angle of view, part of the structure of the array substrate is not shown in FIG. 1 and therefore is not described here.
  • FIG. 2 is a flowchart of a manufacturing method of an array substrate provided by an embodiment of the present disclosure. As shown in FIG. 2, the manufacturing method of an array substrate provided by an embodiment of the present disclosure may include:
  • a gate metal layer is deposited on the base substrate 11, and the gate metal layer is formed into the gate electrode 12 through the first photolithography process.
  • FIG. 3 is a schematic structural diagram of the array substrate provided by an embodiment of the disclosure along the AB direction after the first photolithography process is completed. As shown in FIG. 3, the gate metal layer is formed to form the gate electrode 12 through the first photolithography process.
  • S102 Deposit the gate insulating layer 13, the first semiconductor layer 14, the second semiconductor layer 15, and the source/drain metal layer 16 in sequence, and form the first semiconductor layer 14 and the second semiconductor layer 15 through the second photolithography process.
  • the source island, the source and drain metal layer 16 is formed into the source 161 and the drain 162 at the same time, the channel region 21 is formed between the source 161 and the drain 162, and then the channel region 21 is oxidized to make the channel region 21
  • the second semiconductor layer 15 is converted into a protective layer.
  • the continuous deposition thickness of the plasma enhanced chemical vapor deposition (PECVD) method on the base substrate 11 after S101 is
  • the material of the gate insulating layer 13 can be oxides, nitrides or oxynitride compounds, and the corresponding reaction gas can be SiH 4 , NH 3 or N 2 or SiH 2 C l2 , NH 3 or N 2 .
  • the first semiconductor layer 14 is a metal oxide semiconductor layer, which can be an amorphous oxide semiconductor or a polycrystalline oxide semiconductor.
  • the material can be selected from amorphous indium gallium zinc oxide a- IGZO, HIZO, IZO, a-InZnO, ZnO: F, In 2 O 3 : Sn, In 2 O 3 : Mo, Cd 2 SnO 4 , ZnO: Al, TiO 2 : Nb, Cd-Sn-O or other metals
  • the oxide may be a single layer or multiple layers.
  • the conductivity of the metal oxide semiconductor can be effectively controlled by controlling the oxygen content in the metal oxide semiconductor.
  • the oxide semiconductor layer 14 has low oxygen content and therefore low conductivity.
  • the metal oxide semiconductor layer 14 directly contacts the gate insulating layer 13, and the metal oxide semiconductor layer 14 between the source electrode 161 and the drain electrode 162 is formed.
  • the performance of the semiconductor thin film transistor formed by the channel region 21 and the metal oxide semiconductor layer 14 with low oxygen content is more stable.
  • the continuous deposition thickness by PECVD method is
  • the second semiconductor layer 15 is a heavily doped amorphous silicon semiconductor layer.
  • doping refers to the addition of conductive elements in a tetravalent semiconductor, for example, adding trivalent boron or pentavalent phosphorus to silicon or germanium to improve the conductivity of the semiconductor.
  • the more conductive elements are added The conductivity of the semiconductor is stronger, and it is generally added in the proportion of one part per million (ppm).
  • ppm part per million
  • it can be divided into light doping, medium doping and heavy doping, for example, 5ppm Less than lightly doped, 5-20ppm (including 5, excluding 20) is moderately doped, and 20ppm and above is heavily doped.
  • the heavily doped amorphous silicon semiconductor layer is a high-conductivity semiconductor layer that directly contacts the source and drain metal electrodes, so that the contact resistance between the semiconductor layer and the source and drain metal electrodes can be reduced, and the on-state current of the thin film transistor can be increased.
  • the source and drain metal layer 16 can be selected from Cr, W, Ti, Ta or Mo and other metals and alloys thereof, and can be a single layer or multiple layers.
  • the second photolithography is performed by a halftone mask process or a gray tone mask process.
  • a half-tone mask HTM is a process that uses a semi-transparent film on the mask to incompletely expose the photoresist.
  • the gray-tone mask is a process that uses the light-blocking strips in the gray-scale area on the mask to expose the photoresist incompletely.
  • the second photolithography process may specifically include the following processes:
  • FIG. 4- is a schematic diagram of the structure along the AB direction of the array substrate provided by the embodiment of the disclosure after exposure and development in the second photolithography process-forming a completely light-transmitting area 18.
  • the opaque region 19 and the partially transparent region 20 corresponds to the source and drain and the data line 26, and the partially transparent region 20 corresponds to the channel region 21 between the source and drain, which is completely transparent
  • the area 18 corresponds to an area other than the light-impermeable area 19 and the partially light-transmissive area 20.
  • the partially transparent region 20 is located in the middle of the two opaque regions 19, and the two completely transparent regions 18 are located on both sides of the two opaque regions 19 respectively.
  • FIG. 5- is a schematic diagram of the structure of the array substrate provided by the embodiment of the disclosure in the AB direction after the first etching in the second photolithography process-by
  • the etching process removes the source and drain metal layers 16, the second semiconductor layer 15, and the first semiconductor layer 14 in the completely light-transmitting region 18, so that only the gate insulating layer 13 and the parts below it remain in the completely light-transmitting region 18.
  • the first semiconductor layer 14 and the second semiconductor layer 15 form an active island, the source and drain metal layer 16 above the active island remains, and the first semiconductor layer 14 and the second semiconductor layer 15 outside the active island Both the source and drain metal layers 16 are etched away.
  • FIG. 6 is a schematic diagram of the structure of the array substrate in the second photolithography process along the AB direction after the array substrate provided by the embodiment of the present disclosure is ashed.
  • FIG. 7- is a schematic diagram of the structure of the array substrate provided by the embodiment of the disclosure along the AB direction after the second photolithography process-the part is etched away by the etching process
  • the source-drain metal layer 16 in the light-transmitting area 20 forms a channel region 21 between the source and drain
  • the source-drain metal layer 16 that is not etched on the left forms a source 161
  • the right is not etched away
  • the source and drain metal layer 16 forms the drain 162.
  • the second semiconductor layer 15 in the channel region 21 is subjected to oxidation treatment.
  • the oxidation treatment can be carried out in an oxygen plasma environment in a dry etching equipment.
  • the radio frequency power is 5KW-10KW, and the pressure is 200mT-600mT.
  • the gas flow rate is 1000-4000 sccm.
  • FIG. 8 is a schematic structural diagram of the array substrate in the AB direction after the third photolithography process is completed according to the embodiment provided by the present disclosure.
  • plasma-enhanced chemistry is performed on the base substrate 11 after S102 is completed.
  • the continuous deposition thickness of the vapor deposition method is The passivation layer 22, the material of the passivation layer 22 can be selected from oxides, nitrides or oxynitride compounds, and can be a single layer or multiple layers.
  • the corresponding reaction gas can be SiH 4 , NH 3 or N 2 or SiH 2 C l2 , NH 3 or N 2 .
  • a passivation layer pattern having a conductive via 23 is formed, and the conductive via 23 is located above the drain 162.
  • S104 Deposit a transparent conductive layer, and through the fourth photolithography process, the transparent conductive layer is formed into the pixel electrode 24 and the pixel electrode 24 and the drain electrode 162 are connected through the conductive via 23.
  • FIG. 9 is a schematic structural diagram of the array substrate provided by an embodiment of the disclosure along the AB direction after the fourth photolithography process is completed.
  • the base substrate 11 after S103 is sputtered or heated.
  • the evaporation method continuously deposits the thickness of about
  • the transparent conductive layer the material of the transparent conductive layer can be indium tin oxide ITO or indium zinc oxide IZO, or other transparent metal oxides.
  • the pixel electrode 24 is formed on the transparent conductive layer, and the pixel electrode 24 and the drain electrode 162 are connected through the conductive via 23.
  • the manufacturing method of the array substrate provided by the embodiments of the present disclosure adopts a metal oxide thin film transistor structure, and uses a halftone or gray tone mask in the second photolithography process to simultaneously form the metal oxide semiconductor layer pattern, source and drain metal Electrodes, data scan lines, and the channel region between the source and drain, and the heavily doped amorphous silicon semiconductor layer in the channel region is oxidized to convert it into silicon oxide, saving 2 times of photolithography The process improves the production efficiency.
  • the double-layer semiconductor layer structure is cleverly designed.
  • the upper layer is a heavily doped amorphous silicon semiconductor layer.
  • the amorphous silicon semiconductor layer is in direct contact with the source and drain metal electrodes, which can reduce the source and drain metal electrodes and semiconductors.
  • the contact resistance of the layer can also protect the underlying metal oxide semiconductor layer from corrosion when forming the source and drain metal electrodes. This design reduces the process difficulty and improves the performance and stability of the thin film transistor.
  • the embodiments of the present disclosure also provide an array substrate, which is manufactured by the above method, as shown in FIG. 1 and FIG. 9, the array substrate may include: a base substrate 11 and a base substrate 11 sequentially arranged on the base substrate 11
  • the gate electrode 12, the gate insulating layer 13, the first semiconductor layer 14, the second semiconductor layer 15, the source and drain layer, the passivation layer 22 and the pixel electrode 24, the source and drain layer may include: a source electrode 161 and a drain electrode 162.
  • the first semiconductor layer 14 is a metal oxide semiconductor layer
  • the second semiconductor layer 15 is a heavily doped amorphous silicon semiconductor layer
  • the channel region 21 has a protective layer 151
  • the protective layer 151 is a silicon oxide formed by oxidation of the second semiconductor layer 15
  • a conductive via 23 is provided on the passivation layer 22, and the pixel electrode 24 passes through the conductive via 23 and the drain 162 Connected.
  • the array substrate may also include a scan line 25 and a data line 26.
  • the scan line 25 may be connected to the gate electrode 12 and the two are formed in the same photolithography process.
  • the data line 26 may be connected to the source electrode 161 and the two may be in the same photolithography process. In the engraving process.
  • the thickness of the gate electrode 12 can be about
  • the material of the gate can be selected from metals such as Cr, W, Ti, Ta, Mo, Al, Cu, or alloys thereof, and a gate metal layer composed of multiple layers of metals can also meet the requirements.
  • the thickness of the gate insulating layer 13 may be
  • the material of the gate insulating layer can be oxide, nitride, or oxynitride, and the corresponding reaction gas can be SiH 4 , NH 3 or N 2 or SiH 2 Cl 2 , NH 3 or N 2 .
  • the thickness of the first semiconductor layer 14 may be The thickness of the second semiconductor layer 15 may be
  • the first semiconductor layer 14 may be a metal oxide semiconductor, an amorphous oxide semiconductor, or a polycrystalline oxide semiconductor.
  • its material may be selected from amorphous indium gallium zinc oxide a-IGZO, HIZO, IZO, a -InZnO, ZnO: F, In 2 O 3 : Sn, In 2 O 3 : Mo, Cd 2 SnO 4 , ZnO: Al, TiO 2 : Nb, Cd-Sn-O or other metal oxides, metal semiconductor layer 14 Since the oxygen content is low, the conductivity is also low, and the metal semiconductor layer 14 is in direct contact with the gate insulating layer 13.
  • the metal oxide semiconductor layer 14 located between the source electrode 161 and the drain electrode 162 of the thin film transistor forms the channel region 21, and the performance of the semiconductor thin film transistor formed by the metal oxide semiconductor layer with low oxygen content is more stable.
  • the second semiconductor layer 15 may be a heavily doped amorphous silicon semiconductor, and the heavily doped amorphous silicon semiconductor layer may be a semiconductor layer with high conductivity, which directly contacts the source and drain metal electrodes, so that the semiconductor layer and source and drain metals can be reduced.
  • the contact resistance of the electrode increases the on-state current of the thin film transistor.
  • the thickness of the source-drain metal layer 16 can be Metals such as Cr, W, Ti, Ta or Mo and their alloys can be selected, and it can be a single layer or multiple layers.
  • the thickness of the passivation layer 22 can be
  • the material of the passivation layer can be selected from oxides, nitrides, or oxygen-nitrogen compounds, and can be a single layer or multiple layers.
  • the corresponding reaction gas can be SiH 4 , NH 3 or N 2 or SiH 2 C l2 , NH 3 or N 2 .
  • the array substrate provided by the embodiments of the present disclosure adopts a double-layer semiconductor layer structure, the upper layer is a heavily doped amorphous semiconductor layer, the lower layer is a metal oxide semiconductor layer with low oxygen content, and the upper amorphous semiconductor layer is directly connected to the source and drain metal electrodes Contact, reducing the contact resistance between the source and drain metal electrodes and the semiconductor layer, while protecting the underlying metal oxide semiconductor layer from being corroded, and at the same time using the oxidation process of heavily doped amorphous silicon to make the amorphous silicon in the channel region Converted into silicon oxide.
  • the oxygen content of the underlying metal oxide semiconductor layer is low, thereby making it conductive Low, which improves the performance and stability of thin film transistors.
  • This design enables the metal oxide semiconductor layer, source and drain metal electrodes, data lines and channel regions to be formed in the same photolithography process, which saves two photolithography processes, and at the same time avoids the etching barrier layer, and reduces the preparation process Difficulty.
  • first or second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined with “first” or “second” may explicitly or implicitly include one or more of these features.
  • “plurality” means at least two, such as two or three, unless otherwise specifically defined.
  • the terms “installed”, “connected”, “connected” or “fixed” shall be interpreted broadly, for example, it may be a fixed connection or a detachable connection, or Become a whole; it can be mechanically connected, or it can be electrically connected or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal communication of two components or the interaction relationship between two components.
  • installed shall be interpreted broadly, for example, it may be a fixed connection or a detachable connection, or Become a whole; it can be mechanically connected, or it can be electrically connected or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal communication of two components or the interaction relationship between two components.
  • the "above” or “below” of the first feature of the second feature may include direct contact between the first and second features, or may include the first and second features Not in direct contact but through other features between them.
  • “above”, “above” and “above” the second feature of the first feature include the first feature being directly above and obliquely above the second feature, or only that the level of the first feature is higher than the second feature.
  • the “below”, “below” and “below” the first feature of the second feature include the first feature directly below and obliquely below the second feature, or it simply means that the level of the first feature is smaller than the second feature.
  • the manufacturing method of the array substrate provided by the embodiments of the present disclosure and the manufactured array substrate adopt a metal oxide thin film transistor structure, and use a halftone or gray tone mask in the second photolithography process to simultaneously form a metal oxide semiconductor
  • the layer pattern, the source and drain metal electrodes, the data scan line and the channel region between the source and drain, that is, the metal oxide semiconductor layer, the source and drain metal electrodes, the data line and the channel region are formed in the same photolithography process It saves two photolithography processes, avoids the etching barrier layer, and reduces the difficulty of the preparation process; in addition, the heavily doped amorphous silicon semiconductor layer in the channel region is oxidized to convert it into silicon Oxide; At the same time, the double-layer semiconductor layer structure is cleverly designed.
  • the upper layer is a heavily doped amorphous silicon semiconductor layer.
  • the amorphous silicon semiconductor layer is in direct contact with the source and drain metal electrodes, which can reduce the contact resistance between the source and drain metal electrodes and the semiconductor layer.
  • the underlying metal oxide semiconductor layer can also be protected from corrosion. This design reduces the process difficulty.
  • the deposition process is controlled The oxygen content in the lower metal oxide semiconductor layer makes the oxygen content of the underlying metal oxide semiconductor layer low, so that its conductivity is low, and the performance and stability of the thin film transistor are improved.

Abstract

本公开提供一种阵列基板的制作方法及阵列基板，阵列基板的制作方法包括：在衬底基板上沉积栅金属层，通过第一次光刻工艺，形成栅极；依次沉积栅极绝缘层、第一半导体层、第二半导体层、源漏金属层，通过第二次光刻工艺，形成有源岛，源极、漏极，源极和漏极之间形成沟道区，沟道区内的第二半导体层转化成硅的氧化物；沉积钝化层，通过第三次光刻工艺，在漏极上方的钝化层上形成导电过孔；沉积透明导电层，通过第四次光刻工艺，使透明导电层形成像素电极并使像素电极与漏极通过导电过孔连通。本公开提供的阵列基板的制作方法和阵列基板，仅需四次光刻工艺即可实现阵列基板的制作，工艺简单，制作成本低。

Description

阵列基板的制作方法及阵列基板
相关申请的交叉引用
本公开要求于2019年10月23日提交中国专利局的申请号为CN201911013988.4、名称为“阵列基板的制作方法及阵列基板”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及液晶显示技术领域，尤其涉及一种阵列基板的制作方法及阵列基板。
背景技术
随着显示技术的发展，液晶显示器(Liquid Crystal Display，简称LCD)等平面显示装置因具有高画质、省电、机身薄并且无辐射等优点，而被广泛地应用于手机、电视、个人数字助理和笔记本电脑等各种消费性电子产品中，成为显示装置中的主流。液晶显示面板一般由相对设置的阵列基板、彩膜基板以及夹持在阵列基板和彩膜基板之间的液晶分子层组成。通过在阵列基板和彩膜基板之间施加驱动电压，可控制液晶分子旋转，从而使背光模组的光线折射出来产生画面。
申请人知晓的一种阵列基板的制造方法包括六次光刻工艺，包括：第一步：在玻璃衬底基板上沉积金属层，进行第一次光刻，形成栅极；第二步，依次沉积栅极绝缘层和铟镓锌氧化物IGZO半导体层，进行第二次光刻，以形成有源岛图形；第三步，沉积刻蚀阻挡层，并进行第三次光刻；第四步，沉积源漏极金属层，并进行第四次光刻，以形成源极和漏极；第五步，沉积钝化层和平坦化层，并进行第五次光刻，以形成导电过孔；第六步，沉积透明导电薄膜，并进行第六次光刻，以形成像素电极以及导电过孔和像素电极的连通图形。
上述用于阵列基板的制造方法包括六次光刻工艺，工艺复杂，制作成本高。
发明内容
本公开提供一种阵列基板的制作方法及阵列基板，仅需四次光刻工艺即可实现阵列基板的制作，工艺简单，制作成本低。
本公开实施例提供了一种阵列基板的制作方法，包括：
在衬底基板上沉积栅金属层，通过第一次光刻工艺，使所述栅金属层形成栅极；
依次沉积栅极绝缘层、第一半导体层、第二半导体层、源漏金属层，通过第二次光刻工艺，使所述第一半导体层和所述第二半导体层形成有源岛，同时所述源漏金属层形成源极和漏极，所述源极和所述漏极之间形成沟道区，再对所述沟道区进行氧化处理，使位于所述沟道区内的所述第二半导体层转化成保护层；
沉积钝化层，通过第三次光刻工艺，在所述漏极上方的所述钝化层上形成导电过孔；
沉积透明导电层，通过第四次光刻工艺，使所述透明导电层形成像素电极并使所述像素电极与所述漏极通过所述导电过孔连通。
可选地，所述第二次光刻工艺包括一次灰色调掩膜版工艺或半色调掩膜版工艺。
可选地，所述第二次光刻工艺具体包括：
通过掩膜版曝光显影，形成完全透光区域、部分透光区域和不透光区域，所述不透光区域对应于所述源极和所述漏极，所述部分透光区域对应于所述沟道区；
进行第一次刻蚀，刻蚀掉所述完全透光区域对应的所述源漏金属层、所述第二半导体层、所述第一半导体层；
进行一次光刻灰化工艺，去除掉部分透光区域的光刻胶；进行第二次刻蚀，刻蚀掉所述部分透光区域内的所述源漏金属层，以形成所述沟道区；
保留不透光区域对应的所述源漏金属层，以形成所述源极和所述漏极。
可选地，所述第一半导体层为金属氧化物半导体层，包括非晶铟镓锌氧化物a-IGZO。
可选地，在沉积所述第一半导体层时，降低所述金属氧化物半导体层中氧的含量，以降低所述第一半导体层的导电率。
可选地，所述第二半导体层为重掺杂非晶硅半导体层。
可选地，所述保护层为硅的氧化物。
可选地，所述第一半导体层通过溅射方法沉积形成，所述第二半导体层通过等离子体增强化学气相沉积方法沉积形成。
可选地，所述第一半导体层的厚度为
Figure PCTCN2020080721-appb-000001
所述第二半导体层的厚度为
Figure PCTCN2020080721-appb-000002
本公开实施例提供的阵列基板的制作方法，采用金属氧化物薄膜晶体管结构，在第二次光刻工艺中使用一次半色调或灰色调掩膜版同时形成金属氧化物半导体层图案、源漏金 属电极、数据扫描线以及源漏极之间的沟道区，并对沟道区内的重掺杂非晶硅半导体层进行氧化处理，使其转化为硅的氧化物，节省了2次光刻工艺，提升了生产效率；同时巧妙地设计了双层半导体层结构，上层为重掺杂非晶硅半导体层，非晶硅半导体层与源漏金属电极直接接触，可以减少源漏金属电极与半导体层的接触电阻，同时在形成源漏金属电极时也可以保护下层的金属氧化物半导体层不被腐蚀，这样的设计减少了工艺难度，提升薄膜晶体管的性能和稳定性。
本公开实施例还提供了一种阵列基板，所述阵列基板通过如上所述的制作方法制作而成，所述阵列基板包括衬底基板以及依次设置在所述衬底基板上的栅极、栅极绝缘层、第一半导体层、第二半导体层、源漏极层、钝化层和像素电极，所述源漏极层包括源极和漏极，所述源极和所述漏极之间具有沟道区；
所述第一半导体层为金属氧化物半导体层，所述第二半导体层为重掺杂非晶硅半导体层；所述沟道区内具有保护层，所述保护层为所述第二半导体层经过氧化处理形成的硅的氧化物；
所述钝化层上具有导电过孔，所述像素电极通过所述导电过孔与所述漏极连通。
本公开实施例提供的阵列基板采用双层半导体层结构，上层为重掺杂非晶半导体层，下层为含氧量低的金属氧化物半导体层，上层的非晶半导体层直接与源漏金属电极接触，减少了源漏金属电极与半导体层的接触电阻，同时能够保护下层的金属氧化物半导体层不被腐蚀，同时利用重掺杂非晶硅的氧化工艺，使得沟道区内的非晶硅转化为硅的氧化物，另一方面，在沉积下层的金属氧化物半导体层时，通过控制沉积过程中氧的含量，使得下层的金属氧化物半导体层的含氧量低，从而使其导电率低，提升了薄膜晶体管的性能和稳定性。这样的设计使得金属氧化物半导体层、源漏金属电极、数据线和沟道区在同一次光刻工艺中形成，节省了2次光刻工艺，同时避免了刻蚀阻挡层，降低了制备工艺难度。
附图说明
为了更清楚地说明本公开或现有技术的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的阵列基板的平面图；
图2为本公开实施例提供的阵列基板的制作方法的流程图；
图3为本公开实施例提供的阵列基板完成第一次光刻工艺后的沿AB方向的结构示意图；
图4为本公开实施例提供的阵列基板完成第二次光刻工艺中的曝光显影后的沿AB方向的结构示意图；
图5为本公开实施例提供的阵列基板完成第二次光刻工艺中的第一次刻蚀后的沿AB方向的结构示意图；
图6为本公开实施例提供的阵列基板完成第二次光刻工艺中的灰化后的沿AB方向的结构示意图；
图7为本公开实施例提供的阵列基板完成第二次光刻工艺后的沿AB方向的结构示意图；
图8为本公开实施例提供的阵列基板完成第三次光刻工艺后的沿AB方向的结构示意图；
图9为本公开实施例提供的阵列基板完成第四次光刻工艺后的沿AB方向的结构示意图。
附图标记：
11-衬底基板；
12-栅极；
13-栅极绝缘层；
14-第一半导体层；
15-第二半导体层；
151-保护层；
16-源漏金属层；
161-源极；
162-漏极；
17-光刻胶；
18-完全透光区域；
19-不透光区域；
20-部分透光区域；
21-沟道区；
22-钝化层；
23-导电过孔；
24-像素电极；
25-扫描线；
26-数据线。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合本公开中的附图，对本公开中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
需要理解的是，传统的液晶显示面板是由一片薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，简称TFT Array Substrate)和一片彩膜基板(Color Filter Substrate，简称CF Substrate)贴合而成，分别在阵列基板和彩膜基板上形成像素电极和公共电极，并在阵列基板和彩膜基板之间灌入液晶，其工作原理是通过在像素电极与公共电极之间施加驱动电压，利用像素电极与公共点击之间形成的电场来控制液晶层内的液晶分子的旋转，将背光模组的光线折射出来产生画面。
掩模版(Mask)，也称为光罩(Photo Mask)，是光刻工艺所使用的图形母版，是由不透光的遮光薄膜(金属铬)在透明衬底基板上形成掩模图形，通过光刻工艺(Photolithography)将图形转印到玻璃衬底基板的薄膜上。曝光(Exposure)过程，就是紫外线(Ultraviolet)通过掩模版照射光刻胶(Photo Resist)，使掩模版上的图形转印到光刻胶上的过程。在阵列工程中，光刻胶起到掩膜的作用，通过曝光形成的光刻胶图形，在 刻蚀工艺中，光刻胶图形对应的基板上的薄膜层被保留下来，其他区域被刻蚀掉，最后去除光刻胶，掩模版上的图形就转移到了基板上，这个过程称为光刻(Photolithography)，每一个光刻工艺过程都经过薄膜沉积、光刻胶涂布、曝光、显影、刻蚀和光刻胶剥离这几个工艺步骤。
可以理解的是，光刻工艺步骤的次数，既影响面板的产能，又影响着面板的制造成本，因此光刻工艺的次数越少越好。
下面参考附图并结合具体的实施例来描述本公开。
图1为本公开实施例提供的阵列基板的平面图，参考图1所示，本公开实施例提供的阵列基板，可以包括源极161、漏极162、钝化层22、导电过孔23、像素电极24、扫描线25和数据线26，其中像素电极24可以通过导电过孔23与漏极162连通，扫描线25可以与栅极12连通且两者可以在同一光刻工艺中形成，数据线26可以与源极161连通且两者可以在同一光刻工艺中形成。应当注意的是，图1为阵列基板的平面图，由于视图角度的原因，阵列基板的部分结构并没有在图1中显示，因此在此处并没有介绍。
图2为本公开实施例提供的阵列基板的制作方法的流程图，如图2所示，本公开实施例提供的阵列基板的制作方法可以包括：
S101：在衬底基板11上沉积栅金属层，通过第一次光刻工艺，使栅金属层形成栅极12。
具体地，在衬底基板11上采用溅射或热蒸发的方法沉积厚度约为
Figure PCTCN2020080721-appb-000003
的栅金属层，栅金属层的材料可以选用Cr、W、Ti、Ta、Mo、Al、Cu等金属或其合金，由多层金属组成的栅金属层也能满足需要。图3为本公开实施例提供的阵列基板完成第一次光刻工艺后的沿AB方向的结构示意图，如图3所示，通过第一次光刻工艺，使得栅金属层形成栅极12。
S102：依次沉积栅极绝缘层13、第一半导体层14、第二半导体层15和源漏金属层16，通过第二次光刻工艺，使第一半导体层14和第二半导体层15形成有源岛，同时使源漏金属层16形成源极161和漏极162，源极161和漏极162之间形成沟道区21，再对沟道区21进行氧化处理，使得沟道区21内的第二半导体层15转化成保护层。
具体地，在完成S101的衬底基板11上通过等离子体增强化学气相沉积(PECVD)方法连续沉积厚度为
Figure PCTCN2020080721-appb-000004
的栅极绝缘层13，栅极绝缘层13的材料可以选用氧化物、 氮化物或者氧氮化合物，对应的反应气体可以为SiH 4、NH 3或N 2或者SiH 2C l2、NH 3或N 2。
然后通过溅射方法连续沉积厚度为
Figure PCTCN2020080721-appb-000005
的第一半导体层14，第一半导体层14为金属氧化物半导体层，可以是非晶氧化物半导体，也可以是多晶氧化物半导体，例如其材料可以选自非晶铟镓锌氧化物a-IGZO、HIZO、IZO、a-InZnO、ZnO:F、In 2O 3:Sn、In 2O 3:Mo、Cd 2SnO 4、ZnO:Al、TiO 2:Nb、Cd-Sn-O或其他金属氧化物，可以是单层也可以是多层。
在沉积金属氧化物半导体层时，通过控制金属氧化物半导体中氧的含量可以有效地控制金属氧化物半导体的导电性，沉积金属氧化物半导体层薄膜中氧的含量越高，该金属氧化物半导体薄膜的导电性就越好，越接近导体，沉积金属氧化物半导体层薄膜中氧的含量越低，该金属氧化物半导体薄膜的导电性就越差，越接近半导体，本公开实施例中的金属氧化物半导体层14的含氧量低，因此导电率也低，金属氧化物半导体层14直接与栅极绝缘层13接触，位于源极161和漏极162之间的金属氧化物半导体层14形成沟道区21，低含氧量的金属氧化物半导体层14形成的半导体薄膜晶体管的性能更稳定。
再通过PECVD方法连续沉积厚度为
Figure PCTCN2020080721-appb-000006
的第二半导体层15，第二半导体层15为重掺杂非晶硅半导体层。其中，掺杂指的是在四价的半导体内加入导电的元素，例如，在硅或锗中加入三价的硼或者五价的磷等来提高半导体的导电性，加入导电元素的比例越多，半导体的导电性就越强，一般是按百万分之一(ppm)数量级的比例加入,根据导电元素的加入比例不同可以分为轻掺杂、中掺杂和重掺杂，例如，5ppm以内为轻掺杂，5-20ppm(包括5，不包括20)为中掺杂，20ppm及以上为重掺杂。重掺杂非晶硅半导体层为高导电率的半导体层，其直接与源漏金属电极接触，这样可以减少半导体层和源漏金属电极的接触电阻，提升薄膜晶体管的开态电流。
接着再通过溅射或热蒸发沉积厚度为
Figure PCTCN2020080721-appb-000007
的源漏金属层16，源漏金属层16可以选用Cr、W、Ti、Ta或Mo等金属和其合金，可以是单层也可以是多层。
具体地，第二次光刻通过半色调掩膜版工艺或者一次灰色调掩膜版工艺进行。其中，半色调掩模版(Half-tone Mask，简称HTM)，是利用掩模版上的半透膜，将光阻不完全曝光的工艺。灰色调掩膜版(Gray-tone Mask),是利用掩模版上的灰阶区域挡光条，将光阻不完全曝光的工艺。
第二次光刻工艺具体可以包括下述过程：
通过掩膜版曝光显影，如图4所示——其为本公开实施例提供的阵列基板通过第二次 光刻工艺中的曝光显影后的沿AB方向的结构示意图——形成完全透光区域18、不透光区域19和部分透光区域20，不透光区域19对应于源漏极和数据线26，部分透光区域20对应于源漏极之间的沟道区21，完全透光区域18对应于除不透光区域19和部分透光区域20之外的区域。部分透光区域20位于两个不透光区域19的中间，两个完全透光区域18分别位于两个不透光区域19的两侧。
接着进行第一次刻蚀，如图5所示——其为本公开实施例提供的阵列基板通过第二次光刻工艺中的第一次刻蚀后的沿AB方向的结构示意图——通过刻蚀工艺去除掉完全透光区域18内的源漏金属层16、第二半导体层15和第一半导体层14，使得完全透光区域18内只保留栅极绝缘层13及其以下的部分。刻蚀完成后，第一半导体层14和第二半导体层15形成了有源岛，有源岛上方的源漏金属层16保留，有源岛以外的第一半导体层14、第二半导体层15和源漏金属层16均被刻蚀掉。
接着进行一次光刻灰化工艺，如图6所示，——其为本公开实施例提供的阵列基板通过第二次光刻工艺中的灰化后的沿AB方向的结构示意图——去除掉部分透光区域20内的光刻胶17。
接着进行第二次刻蚀，如图7所示——其为本公开实施例提供的阵列基板通过第二次光刻工艺后的沿AB方向的结构示意图——通过刻蚀工艺刻蚀掉部分透光区域20内的源漏金属层16，从而形成源漏极之间的沟道区21，左侧未被刻蚀掉的源漏金属层16形成源极161，右侧未被刻蚀掉的源漏金属层16则形成漏极162。
接着，再对沟道区21内的第二半导体层15进行氧化处理，氧化处理可以在干法刻蚀设备中氧等离子体环境中进行，其射频功率为5KW-10KW，气压为200mT-600mT，气体的流量为1000-4000sccm，经过氧化处理后，沟道区21内的重掺杂非晶硅半导体层转化成硅的氧化物，硅的氧化物即为保护层151。
S103：沉积钝化层22，并通过第三次光刻工艺，在漏极162上方的钝化层22之上形成导电过孔23。
图8为本公开提供实施例的阵列基板完成第三次光刻工艺后的沿AB方向的结构示意图，如图8所示，具体地，在完成S102的衬底基板11上通过等离子体增强化学气相沉积方法连续沉积厚度为
Figure PCTCN2020080721-appb-000008
的钝化层22，钝化层22的材料可以选用氧化物、氮化物或者氧氮化合物，可以是单层也可以是多层，对应的反应气体可以为SiH 4、NH 3或N 2或者SiH 2C l2、NH 3或N 2。通过第三次光刻工艺，形成具有导电过孔23的钝化层图形，导电过 孔23位于漏极162的上方。
S104：沉积透明导电层，并通过第四次光刻工艺，使透明导电层形成像素电极24并使像素电极24与漏极162通过导电过孔23连通。
图9为本公开实施例提供的阵列基板完成第四次光刻工艺后的沿AB方向的结构示意图，如图9所示，具体地，在完成S103的衬底基板11上通过溅射或热蒸发的方法连续沉积上厚度约为
Figure PCTCN2020080721-appb-000009
的透明导电层，透明导电层的材料可以是氧化铟锡ITO或氧化铟锌IZO，或者其他的透明金属氧化物。通过第四光刻工艺，使透明导电层形成像素电极24，并使像素电极24与漏极162通过导电过孔23连通。
本公开实施例提供的阵列基板的制作方法，采用金属氧化物薄膜晶体管结构，在第二次光刻工艺中使用一次半色调或灰色调掩膜版同时形成金属氧化物半导体层图案、源漏金属电极、数据扫描线以及源漏极之间的沟道区，并对沟道区内的重掺杂非晶硅半导体层进行氧化处理，使其转化为硅的氧化物，节省了2次光刻工艺，提升了生产效率；同时巧妙地设计了双层半导体层结构，上层为重掺杂非晶硅半导体层，非晶硅半导体层与源漏金属电极直接接触，可以减少源漏金属电极与半导体层的接触电阻，同时在形成源漏金属电极时也可以保护下层的金属氧化物半导体层不被腐蚀，这样的设计减少了工艺难度，提升薄膜晶体管的性能和稳定性。
本公开实施例还提供了一种阵列基板，该阵列基板通过上述方法制作而成，如图1和图9所示，该阵列基板可以包括：衬底基板11以及依次设置在衬底基板11上的栅极12、栅极绝缘层13、第一半导体层14、第二半导体层15、源漏极层、钝化层22和像素电极24，源漏极层可以包括：源极161和漏极162，源极161和漏极162之间可以具有沟道区21；其中，第一半导体层14为金属氧化物半导体层，第二半导体层15为重掺杂非晶硅半导体层，沟道区21内具有保护层151，保护层151为第二半导体层15经过氧化处理而形成的硅的氧化物；钝化层22上具有导电过孔23，像素电极24通过导电过孔23与漏极162连通。
该阵列基板还可以包括扫描线25和数据线26，扫描线25可以与栅极12连通且两者在同一光刻工艺中形成，数据线26可以与源极161连通且两者可以在同一光刻工艺中形成。
其中，栅极12的厚度可以约为
Figure PCTCN2020080721-appb-000010
并且栅极的材料可以选用Cr、W、Ti、Ta、Mo、Al、Cu等金属或其合金，由多层金属组成的栅金属层也能满足需要。
栅极绝缘层13的厚度可以为
Figure PCTCN2020080721-appb-000011
并且栅极绝缘层的材料可以选用氧化物、氮化物或者氧氮化合物，对应的反应气体可以为SiH 4、NH 3或N 2或者SiH 2C l2、NH 3或N 2。
第一半导体层14的厚度可以为
Figure PCTCN2020080721-appb-000012
第二半导体层15的厚度可以为
Figure PCTCN2020080721-appb-000013
第一半导体层14可以为金属氧化物半导体，可以是非晶氧化物半导体，也可以是多晶氧化物半导体，例如其材料可以选自非晶铟镓锌氧化物a-IGZO、HIZO、IZO、a-InZnO、ZnO:F、In 2O 3:Sn、In 2O 3:Mo、Cd 2SnO 4、ZnO:Al、TiO 2:Nb、Cd-Sn-O或其他金属氧化物，金属半导体层14为的含氧量低，因此导电率也低，金属半导体层14直接与栅极绝缘层13接触。位于薄膜晶体管的源极161和漏极162之间的金属氧化物半导体层14形成沟道区21，低含氧量的金属氧化物半导体层形成的半导体薄膜晶体管的性能更稳定。
第二半导体层15可以是重掺杂非晶硅半导体，重掺杂非晶硅半导体层可以为高导电率的半导体层，其直接与源漏金属电极接触，这样可以减少半导体层和源漏金属电极的接触电阻，提升薄膜晶体管的开态电流。
源漏金属层16的厚度可以为
Figure PCTCN2020080721-appb-000014
可以选用Cr、W、Ti、Ta或Mo等金属和其合金，可以是单层也可以是多层。
钝化层22的厚度可以为
Figure PCTCN2020080721-appb-000015
钝化层的材料可以选用氧化物、氮化物或者氧氮化合物，可以是单层也可以是多层，对应的反应气体可以为SiH 4、NH 3或N 2或者SiH 2C l2、NH 3或N 2。
本公开实施例提供的阵列基板采用双层半导体层结构，上层为重掺杂非晶半导体层，下层为含氧量低的金属氧化物半导体层，上层的非晶半导体层直接与源漏金属电极接触，减少了源漏金属电极与半导体层的接触电阻，同时能够保护下层的金属氧化物半导体层不被腐蚀，同时利用重掺杂非晶硅的氧化工艺，使得沟道区内的非晶硅转化为硅的氧化物，另一方面，在沉积下层的金属氧化物半导体层时，通过控制沉积过程中氧的含量，使得下层的金属氧化物半导体层的含氧量低，从而使其导电率低，提升了薄膜晶体管的性能和稳定性。这样的设计使得金属氧化物半导体层、源漏金属电极、数据线和沟道区在同一次光刻工艺中形成，节省了2次光刻工艺，同时避免了刻蚀阻挡层，降低了制备工艺难度。
在本公开的描述中，需要理解的是，所使用的术语“中心”、“长度”、“宽度”、“厚度”、“顶端”、“底端”、“上”、“下”、“左”、“右”、“前”、“后”、“竖直”、“水平”、“内”、“外”“轴 向”和“周向”等指示方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的位置或原件必须具有特定的方位或以特定的构造和操作，因此不能理解为对本公开的限制。
此外，术语“第一”或“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”或“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开的描述中，“多个”的含义是至少两个，例如两个或三个等，除非另有明确具体的限定。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”或“固定”等应做广义理解，例如可以是固定连接，也可以是可拆卸连接，或成为一体；可以是机械连接，也可以是电连接或者可以互相通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
在本公开中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性：
本公开实施例提供的阵列基板的制作方法及其制造的阵列基板，采用金属氧化物薄膜晶体管结构，在第二次光刻工艺中使用一次半色调或灰色调掩膜版同时形成金属氧化物半导体层图案、源漏金属电极、数据扫描线以及源漏极之间的沟道区，即，使金属氧化物半导体层、源漏金属电极、数据线和沟道区在同一次光刻工艺中形成，节省了2次光刻工艺，同时避免了刻蚀阻挡层，降低了制备工艺难度；此外，并对沟道区内的重掺杂非晶硅半导 体层进行氧化处理，使其转化为硅的氧化物；同时巧妙地设计了双层半导体层结构，上层为重掺杂非晶硅半导体层，非晶硅半导体层与源漏金属电极直接接触，可以减少源漏金属电极与半导体层的接触电阻，同时在形成源漏金属电极时也可以保护下层的金属氧化物半导体层不被腐蚀，这样的设计减少了工艺难度，另一方面，在沉积下层的金属氧化物半导体层时，通过控制沉积过程中氧的含量，使得下层的金属氧化物半导体层的含氧量低，从而使其导电率低，提升薄膜晶体管的性能和稳定性。

Claims (18)

  1. 一种阵列基板的制作方法，其特征在于，包括：
    在衬底基板上沉积栅金属层，并通过第一次光刻工艺，使所述栅金属层形成栅极；
    在形成有栅极的衬底基板上依次沉积栅极绝缘层、第一半导体层、第二半导体层、源漏金属层，通过第二次光刻工艺，使所述第一半导体层和所述第二半导体层形成有源岛，同时所述源漏金属层形成源极和漏极，所述源极和所述漏极之间形成沟道区，然后再对所述沟道区进行氧化处理，使位于所述沟道区内的所述第二半导体层转化成保护层；
    沉积钝化层，并通过第三次光刻工艺，在所述漏极上方的所述钝化层上形成导电过孔；
    沉积透明导电层，并通过第四次光刻工艺，使所述透明导电层形成像素电极并使所述像素电极与所述漏极通过所述导电过孔连通。
  2. 根据权利要求1所述的制作方法，其特征在于，所述第二次光刻工艺包括一次灰色调掩膜版工艺或半色调掩膜版工艺。
  3. 根据权利要求2所述的制作方法，其特征在于，所述第二次光刻工艺包括：
    通过掩膜版曝光显影，形成完全透光区域、部分透光区域和不透光区域，所述不透光区域对应于所述源极和所述漏极，所述部分透光区域对应于所述沟道区；
    进行第一次刻蚀，刻蚀掉所述完全透光区域对应的所述源漏金属层、所述完全透光区域对应的所述第二半导体层和所述完全透光区域对应的所述第一半导体层；
    进行一次光刻灰化工艺，去除掉部分透光区域的光刻胶；进行第二次刻蚀，刻蚀掉所述部分透光区域内的所述源漏金属层，以形成所述沟道区；
    保留不透光区域对应的所述源漏金属层，以形成所述源极和所述漏极。
  4. 根据权利要求1至3中任一项所述的制作方法，其特征在于，所述第一半导体层为金属氧化物半导体层，包括非晶铟镓锌氧化物a-IGZO。
  5. 根据权利要求4所述的制作方法，其特征在于，在沉积所述第一半导体层时，降低所述金属氧化物半导体层中氧的含量，以降低所述第一半导体层的导电率。
  6. 根据权利要求1至5中任一项所述的制作方法，其特征在于，所述第二半导体层为重掺杂非晶硅半导体层。
  7. 根据权利要求6所述的制作方法，其特征在于，所述保护层为硅的氧化物。
  8. 根据权利要求1至7中任一项所述的制作方法，其特征在于，所述第一半导体层通过溅射方法沉积形成，所述第二半导体层通过等离子体增强化学气相沉积方法沉积形成。
  9. 根据权利要求1至8中任一项所述的制作方法，其特征在于，所述第一半导体层的厚度为
    Figure PCTCN2020080721-appb-100001
    所述第二半导体层的厚度为
    Figure PCTCN2020080721-appb-100002
  10. 根据权利要求1至9中任一项所述的制作方法，其特征在于，所述氧化处理在干法刻蚀设备中氧等离子体环境中进行。
  11. 根据权利要求1至10中任一项所述的制作方法，其特征在于，所述第一半导体层为与所述栅极绝缘层直接接触的金属氧化物半导体层，所述第二半导体层为与源漏金属电极直接接触的重掺杂非晶硅半导体层，所述第一半导体层和所述第二半导体层形成双层半导体层结构。
  12. 根据权利要求1至11中任一项所述的制作方法，其特征在于，所述栅极绝缘层的厚度为
    Figure PCTCN2020080721-appb-100003
    所述栅极绝缘层的材料选用氧化物、氮化物或者氧氮化合物。
  13. 根据权利要求1至12中任一项所述的制作方法，其特征在于，所述第一半导体层的材料选自非晶铟镓锌氧化物a-IGZO、HIZO、IZO、a-InZnO、ZnO:F、In 2O 3:Sn、In 2O 3:Mo、Cd 2SnO 4、ZnO:Al、TiO 2:Nb或Cd-Sn-O，所述第一半导体层为单层或多层。
  14. 根据权利要求1至13中任一项所述的制作方法，其特征在于，所述源漏金属层的材料选自Cr、W、Ti、Ta、Mo或其合金，所述源漏金属层是单层或多层。
  15. 根据权利要求1至14中任一项所述的制作方法，其特征在于，所述钝化层的厚度为
    Figure PCTCN2020080721-appb-100004
    所述钝化层的材料选自氧化物、氮化物或者氧氮化合物，所述钝化层是单层或多层。
  16. 根据权利要求1至15中任一项所述的制作方法，其特征在于，所述透明导电层厚度为
    Figure PCTCN2020080721-appb-100005
    所述透明导电层的材料选自氧化铟锡ITO或氧化铟锌IZO。
  17. 根据权利要求1至16中任一项所述的制作方法，其特征在于，所述栅极的厚度为
    Figure PCTCN2020080721-appb-100006
    所述栅极的材料选自Cr、W、Ti、Ta、Mo、Al、Cu或其合金。
  18. 一种阵列基板，其特征在于，所述阵列基板通过如权利要求1-17任一项所述的制作方法制作而成，所述阵列基板包括衬底基板以及依次设置在所述衬底基板上的栅极、栅极绝缘层、第一半导体层、第二半导体层、源漏极层、钝化层和像素电极，所述源漏极层包括源极和漏极，所述源极和所述漏极之间具有沟道区；
    所述第一半导体层为金属氧化物半导体层，所述第二半导体层为重掺杂非晶硅半导体层；所述沟道区内具有保护层，所述保护层为所述第二半导体层经过氧化处理形成的硅的氧化物；
    所述钝化层上具有导电过孔，所述像素电极通过所述导电过孔与所述漏极连通。
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