WO2020037850A1 - Substrat de matrice et son procédé de fabrication, et panneau d'affichage - Google Patents

Substrat de matrice et son procédé de fabrication, et panneau d'affichage Download PDF

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Publication number
WO2020037850A1
WO2020037850A1 PCT/CN2018/116325 CN2018116325W WO2020037850A1 WO 2020037850 A1 WO2020037850 A1 WO 2020037850A1 CN 2018116325 W CN2018116325 W CN 2018116325W WO 2020037850 A1 WO2020037850 A1 WO 2020037850A1
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Prior art keywords
pattern
region
conductive layer
layer
light
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PCT/CN2018/116325
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English (en)
Chinese (zh)
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肖辉
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020037850A1 publication Critical patent/WO2020037850A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • the present application relates to the field of display, and in particular to an array substrate, a manufacturing method thereof, and a display panel.
  • the OLED (Organic Light-Emitting Diode) display panel has many advantages such as self-emission, low driving voltage, high luminous efficiency, short response time, high definition and contrast, and flexible display and large-area full-color display. Display panel recognized by the industry as the best development potential.
  • the pixel driving circuit of the existing OLED display panel generally includes a switching TFT (Thin Film Transistor, ie, Switch TFT, Driver TFT, and Storage Capacitor.
  • the switching TFT is controlled by the scanning signal to control the entry of data signals, and the driving TFT is used to control the current through the OLED device.
  • the storage capacitor is generally used to store the gray-scale voltage to determine the driving current of the driving TFT.
  • LTPS Low Temperature Poly-silicon
  • the present application provides an array substrate, a manufacturing method thereof, and a display panel, which can reduce the production cost, reduce the leakage current of the driving TFT, and improve the electrical performance of the driving TFT.
  • first conductive layer Forming a first conductive layer and a buffer layer in sequence on the base substrate, the first conductive layer including a first light-shielding pattern in a first region and a second light-shielding pattern in a second region;
  • the insulating layer includes a first insulating pattern located above the amorphous silicon pattern and a second insulating pattern located above the polysilicon pattern.
  • the second conductive layer includes the first insulating pattern.
  • a first gate pattern and a second gate pattern above the second insulation pattern, the second gate pattern is electrically connected to the second light-shielding pattern;
  • the dielectric layer is provided with a first contact hole and a second contact hole in the first region;
  • the second area is provided with a third contact hole and a fourth contact hole;
  • a third conductive layer is formed on the dielectric layer, and the third conductive layer includes a first source pattern and a first drain pattern in a first region, a second source pattern and a second region in a second region.
  • a drain pattern, the first source pattern and the first drain pattern covering the first contact hole and the second contact hole, respectively, and in contact with the amorphous silicon pattern, and the second source pattern and the second drain pattern, respectively Covering the third contact hole and the fourth contact hole and making contact with the polysilicon pattern;
  • anode pattern on the flat passivation layer, the anode pattern covering the fifth contact hole and making contact with the second drain pattern;
  • a light emitting layer and a cathode pattern on the anode pattern are sequentially formed in the light emitting region.
  • a third region is further included above the base substrate, the first conductive layer further includes a third light-shielding pattern located in the third region, and the insulating layer further includes a third region A third insulating pattern in the third region and above the third light-shielding pattern, and the second conductive layer further includes a third gate pattern in the third region and on the third insulating pattern, so The third conductive layer further includes a storage electrode pattern located in the third region and above the third gate pattern.
  • a material for preparing the third conductive layer is at least one of aluminum, molybdenum, titanium, chromium, copper, and silver, or,
  • the third conductive layer is made of a combination of silver and indium tin oxide.
  • the step of forming an amorphous silicon pattern above the first light-shielding pattern and a polysilicon pattern above the second light-shielding pattern on the buffer layer includes:
  • an amorphous silicon pattern above the first light-shielding pattern and an amorphous silicon pattern above the second light-shielding pattern are formed on the buffer layer by the same patterning process. .
  • the buffer layer is further provided with a sixth contact hole, the sixth contact hole exposes an upper surface of the second light-shielding pattern, and a conductive layer is deposited in the sixth contact hole, The conductive layer is used to electrically connect the second gate pattern and the second light-shielding pattern.
  • the conductive layer includes the second gate pattern covering the sixth contact hole.
  • a preparation material of the second conductive layer is at least one of aluminum, molybdenum, titanium, chromium, and copper.
  • a material for preparing the first conductive layer is at least one of molybdenum, aluminum, copper, and titanium.
  • the method further includes:
  • first gate pattern and the second gate pattern as shields, respectively, doping the amorphous silicon pattern and the polysilicon pattern to obtain source electrodes located at both ends of the amorphous silicon pattern A contact region and a drain contact region, and a source contact region and a drain contact region at both ends of the polysilicon pattern.
  • a base substrate including a first region and a second region adjacent to each other in a direction parallel to the base substrate;
  • An insulating layer and a second conductive layer including a first insulating pattern over an amorphous silicon pattern and a second insulating pattern over a polysilicon pattern; the second conductive layer including a first insulating pattern over the first insulating pattern A gate pattern and a second gate pattern located above the second insulation pattern, and the second gate pattern is electrically connected to the second light-shielding pattern;
  • a third conductive layer formed on the dielectric layer including a first source pattern and a first drain pattern in a first region, a second source pattern in a second region, and a first Two drain patterns, the first source pattern and the first drain pattern respectively covering the first contact hole and the second contact hole and contacting the amorphous silicon pattern, the second source pattern and the second drain pattern Respectively covering the third contact hole and the fourth contact hole and contacting the polysilicon pattern;
  • a flat passivation layer formed on the third conductive layer and provided with a fifth contact hole;
  • a light-emitting layer and a cathode pattern which are sequentially formed on the light-emitting region and on the anode pattern.
  • a third region is further included above the base substrate, the first conductive layer further includes a third light-shielding pattern located in the third region, and the insulating layer further includes the third region A third insulating pattern located above the third light-shielding pattern, and the second conductive layer further includes a third gate pattern located on the third region and on the third insulating pattern, and the third The conductive layer further includes a storage electrode pattern located in the third region and above the third gate pattern.
  • the material for preparing the third conductive layer is at least one of aluminum, molybdenum, titanium, chromium, copper, and silver, or,
  • the third conductive layer is made of a combination of silver and indium tin oxide.
  • the buffer layer is further provided with a sixth contact hole, the sixth contact hole exposes an upper surface of the second light-shielding pattern, and the second gate pattern covers the sixth contact hole and In contact with the second light-shielding pattern.
  • a material for the second conductive layer is at least one of aluminum, molybdenum, titanium, chromium, and copper.
  • a material for the first conductive layer is at least one of molybdenum, aluminum, copper, and titanium.
  • the second conductive layer is made by any one of chemical vapor deposition, plasma enhanced chemical vapor deposition, sputtering, and vacuum evaporation.
  • the array substrate further includes a source contact region and a drain contact region located at both ends of the amorphous silicon pattern, and a source contact region and a drain contact region located at both ends of the polysilicon pattern.
  • a display panel according to an embodiment of the present application includes the above array substrate.
  • the design of the switching TFT uses an amorphous silicon pattern
  • the driving TFT uses a polysilicon pattern based on LTPS technology.
  • the production cost can be reduced, and the gate pattern of the driving TFT is electrically connected to the light-shielding pattern.
  • the light-shielding pattern obtains a positive voltage from the gate pattern, and the light-shielding pattern forms a capacitor with the polysilicon pattern, thereby reducing the leakage current of the driving TFT, thereby improving the electrical performance of the driving TFT.
  • FIG. 1 is a schematic flowchart of an embodiment of a manufacturing method of an array substrate according to the present application
  • FIG. 2 is a schematic diagram of a scenario for manufacturing an array substrate based on the method shown in FIG. 1;
  • FIG. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present application.
  • FIG. 1 is a schematic flowchart of an embodiment of a manufacturing method of an array substrate according to the present application
  • FIG. 2 is a schematic diagram of a scene of manufacturing an array substrate based on the method shown in FIG. 1.
  • the manufacturing method may include the following steps S11 to S20.
  • a base substrate is provided.
  • the top of the base substrate includes a first region and a second region adjacent to each other in a direction parallel to the base substrate.
  • the base substrate 20 may be a glass substrate, a plastic substrate, or a flexible substrate.
  • the base substrate 20 may also be a flexible substrate, such as PI (Polyimide, polyacryl) Imine) substrate.
  • the base substrate 20 includes an adjacent first region 201 and a second region 202.
  • the first region 201 is a region where a switching TFT of the array substrate is located
  • the second region 202 is a region where a driving TFT of the array substrate is located.
  • the switching TFT is controlled by the scanning signal to control the entry of the data signal, and the driving TFT is used to control the current through the OLED device.
  • a first conductive layer and a buffer layer are sequentially formed on the base substrate.
  • the first conductive layer includes a first light-shielding pattern in a first region and a second light-shielding pattern in a second region.
  • the material of the first light shielding pattern (Light Shielding Metal, LS) 211 and the second light shielding pattern 212 may be the same, for example, both are molybdenum, aluminum, copper, or titanium, or may be a metal alloy.
  • the thickness of the two may be the same. For example, the thickness is 500 ⁇ 2000 ⁇ .
  • the first light-shielding pattern 211 and the second light-shielding pattern 212 can be formed by a mask process Mask-1. Specifically, after the base substrate 20 is cleaned and dried, a full-surface conductive layer is formed on the base substrate 20, and then a full-surface photoresist is coated on the conductive layer, and then a photomask is applied to the one The entire photoresist is exposed and developed. The exposed photoresist is removed by ashing during development, and the unexposed photoresist remains on the base substrate 20 after development, and then is etched. By removing the conductive layer not covered by the photoresist, and finally removing the remaining photoresist, a first conductive layer having a predetermined pattern can be obtained.
  • the buffer layer 22 covers the first conductive layer, and a thickness of the buffer layer 22 may be 1000 to 5000 ⁇ .
  • the buffer layer 22 can be used to prevent impurities on the surface of the substrate 20 from diffusing upwards in subsequent processes to affect the quality of the amorphous silicon pattern 23 formed later.
  • the buffer layer 22 may be a silicon oxide layer, such as a silicon oxide (SiO x ) layer, or a silicon oxide compound layer and a silicon nitride compound layer that sequentially cover the first conductive layer, such as sequentially covering the first conductive layer. SiO x layer and SiN x (silicon nitride) layer, or a combination of other non-conductive materials.
  • the buffer layer 22 may be formed by any method of chemical vapor deposition (CVD), plasma chemical vapor deposition (PACVD), sputtering, vacuum evaporation, and low pressure chemical vapor deposition (LPCVD).
  • an entire semiconductor layer is formed on the buffer layer 22, and then the entire semiconductor layer is patterned by a mask process Mask-2 to obtain amorphous silicon over the first light-shielding pattern 211.
  • the principle and process of the mask process Mask-2 and the mask process Mask-1 are similar, and will not be repeated here.
  • the amorphous silicon pattern located above the second light-shielding pattern 212 is crystallized. For example, ELA (Excimer Laser Annealing, excimer laser annealing) and other processes to crystallize the amorphous silicon pattern to obtain a polysilicon pattern 232 located above the second light-shielding pattern 212.
  • the thickness of the amorphous silicon pattern 231 may be 100 to 1000 ⁇ .
  • the insulating layer includes a first insulating pattern over an amorphous silicon pattern and a second insulating pattern over a polysilicon pattern.
  • the second conductive layer includes a first insulating pattern over the first insulating pattern.
  • a gate pattern and a second gate pattern located above the second insulation pattern, and the second gate pattern is electrically connected to the second light-shielding pattern.
  • any one of CVD, PECVD, sputtering, and vacuum evaporation may be used to sequentially form a full-surface insulating layer and a full-surface conductive layer covering the amorphous silicon pattern 231 and the polysilicon pattern 232 on the buffer layer 22.
  • the thickness of the layer can be 1000 ⁇ 3000 ⁇
  • the thickness of the second conductive layer can be 2000 ⁇ 8000 ⁇
  • the entire conductive layer can be made of metal, such as aluminum, molybdenum, titanium, chromium, copper, or metal oxide, such as Titanium oxide, or metal alloys or other conductive materials, and then pattern the entire conductive layer using a mask process Mask-3 to obtain a first gate directly above the amorphous silicon pattern 231
  • the pattern 251 and the second gate pattern 252 located directly above the polysilicon pattern 232, and the first gate pattern 251 and the second gate pattern 252 are used to etch the entire insulating layer as an etching shield,
  • the insulating layers under the first gate pattern 251 and the second gate pattern 252 are retained, so that the first insulating pattern 241 and the second insulating pattern 242 are obtained, respectively.
  • the conductive layer may be etched by using an etching solution containing phosphoric acid, nitric acid, acetic acid, or deionized water.
  • etching solution containing phosphoric acid, nitric acid, acetic acid, or deionized water.
  • dry etching may also be used.
  • the insulating layer including the first insulating pattern 241 and the second insulating pattern 242 is also referred to as a gate insulating layer (GI layer), and the material thereof may be a silicon oxide, or the gate insulating layer may include a silicon oxide layer in order. And silicon nitrogen compound layer.
  • GI layer gate insulating layer
  • the two ends of the amorphous silicon pattern 231 and the polysilicon pattern 232 are ion-doped, such as P-type doping, to obtain Source contact regions and drain contact regions at both ends of the crystalline silicon pattern 231, and source contact regions and drain contact regions at both ends of the polysilicon pattern 232.
  • the amorphous silicon pattern 231 under the first insulating pattern 241 and the polysilicon pattern 232 under the second insulating pattern 242 are not doped and become the channel layers of the respective TFTs.
  • the second gate pattern 252 and the second light-shielding pattern 212 of the present application are electrically connected.
  • a wire 254 is used to indicate that the two are electrically connected.
  • the present application may open a contact hole in the buffer layer 22 through a photomask process before the gate insulating layer is formed in step S14.
  • This application is called a sixth contact hole, and the sixth The contact hole exposes the upper surface of the second light-shielding pattern 212, and a conductive layer is deposited in the sixth contact hole, and the conductive layer is used to electrically connect the second gate pattern 252 and the second light-shielding pattern 212.
  • the conductive layer may be formed together with the second conductive layer, that is, the conductive layer may be a second gate pattern 252 covering the sixth contact hole.
  • S15 forming a dielectric layer covering a second conductive layer, an amorphous silicon pattern, a polysilicon pattern, and a buffer layer, the dielectric layer is provided with a first contact hole and a second contact hole in a first region, and a second region A third contact hole and a fourth contact hole are provided.
  • a dielectric layer also known as an interlayer dielectric isolation layer,
  • the upper surface of the ILD may be a flat surface, and its thickness may be 1 to 4 ⁇ m.
  • a mask process Mask-4 may be used to open the first contact hole 261, the second contact hole 262, the third contact hole 263, and the fourth contact hole 264 on the entire dielectric layer.
  • a full-face dielectric layer covering the second conductive layer, the amorphous silicon pattern 231, the polysilicon pattern 232, and the buffer layer 22 may be formed by any method such as CVD, PECVD, sputtering, and vacuum evaporation.
  • a whole photoresist is coated on the entire dielectric layer, and then the whole photoresist is exposed and developed using a photomask, and is exposed (that is, the first contact hole 261, the second (The areas corresponding to the contact holes 262, the third contact holes 263, and the fourth contact holes 264) are removed by ashing during development, and the unexposed photoresist remains on the dielectric layer after development. Then, the dielectric layer not covered by the photoresist is etched and removed, and the remaining photoresist is finally removed to obtain the dielectric layer 26.
  • the first contact hole 261 is the source contact hole of the switching TFT.
  • the source contact area of the amorphous silicon pattern 231 is exposed through the first contact hole 261.
  • the second contact hole 262 is the drain contact hole of the switching TFT.
  • the drain contact region of the silicon pattern 231 is exposed through the second contact hole 262.
  • the third contact hole 263 is the source contact hole of the driving TFT.
  • the source contact area of the polysilicon pattern 232 is exposed through the third contact hole 263.
  • the fourth contact hole 264 is the drain contact hole of the driving TFT, and the drain of the polysilicon pattern 232. The contact area is exposed through the fourth contact hole 264.
  • a third conductive layer is formed on the dielectric layer.
  • the third conductive layer includes a first source pattern and a first drain pattern in a first region, a second source pattern and a second drain in a second region. Pattern, the first source pattern and the first drain pattern respectively cover the first contact hole and the second contact hole and contact the amorphous silicon pattern, and the second source pattern and the second drain pattern respectively cover the third contact hole and The fourth contact hole is in contact with the polysilicon pattern.
  • the first source pattern 271 and the first drain pattern 272 are the source and drain patterns of the switching TFT, and the second source pattern 273 and the second drain pattern 274 are the source and drain patterns of the driving TFT, respectively.
  • Pattern, the thickness of the four on the dielectric layer 26 may be equal, and the thickness may be 2000 to 8000 ⁇ , and the manufacturing materials of the four include, but are not limited to, aluminum, molybdenum, titanium, chromium, copper, and metal oxides Or metal alloys or other conductive materials, of course, it can also be ITO (Indium tin oxide, indium tin oxide), or it can include three layers of ITO, silver and ITO in order.
  • a mask process, Mask-5 can be used to pattern the entire conductive layer to obtain these four patterns. The principle and process of the mask process Mask-5 and the mask process Mask-3 are similar, and will not be repeated here.
  • the first source pattern 271 is in contact with the source contact region of the amorphous silicon pattern 231 through the first contact hole 261, and the first drain pattern 272 is in contact with the amorphous silicon pattern 231 through the second contact hole 262.
  • the drain contact region contacts, the second source pattern 273 contacts the source contact region of the polysilicon pattern 232 through the third contact hole 263, and the second drain pattern 274 contacts the polysilicon pattern 232 through the fourth contact hole 264.
  • the drain contact area is in contact.
  • signal traces such as data lines, scan lines, etc.
  • various signal traces can also be formed on the dielectric layer 26 simultaneously.
  • the signal traces are made of the same material as any one of the first source pattern 271, the first drain pattern 272, the second source pattern 273, and the second drain pattern 274.
  • the switching TFT and the driving TFT of the array substrate can be obtained in this application.
  • the manufacturing method further includes:
  • a flat passivation layer is formed on the third conductive layer, and a fifth contact hole is formed.
  • the flat passivation layer may include passivation (Passivation, PV) layer 281 and flat layer (PLN) 282, the fifth contact hole 283 penetrates the passivation layer 281 and the flat layer 282, and exposes the second drain pattern 274.
  • Passivation PV
  • PPN flat layer
  • the material of the anode pattern 291 includes, but is not limited to, ITO.
  • a pixel definition layer is formed on the flat passivation layer, and the pixel definition layer is provided with a light emitting region for defining an array substrate.
  • the pixel definition layer (Pixel Define Layer, PDL) 292 is used to surround the light emitting area forming the array substrate, that is, to define the pixel opening area.
  • a light emitting layer and a cathode pattern are sequentially formed on the anode pattern in the light emitting region.
  • the array substrate of the present application further includes an electron injection layer and an electron transport layer sequentially formed between the anode pattern 291 and the light emitting layer 293, and a hole transport layer and an air transport layer sequentially formed between the light emitting layer 293 and the cathode pattern 294. Cavity injection layer.
  • the array substrate 30 shown in FIG. 3 of this application can be obtained by the above method.
  • the switching TFT located in the first region 201 uses an amorphous silicon pattern 231, and the The driving TFT uses a polysilicon pattern 232 based on LTPS technology.
  • the switching TFT of the present application does not need a crystallization process, which can reduce production costs and drive the gate pattern of the TFT (ie, the second gate pattern ) 252 is electrically connected to the light-shielding pattern (ie, the second light-shielding pattern) 212, and the light-shielding pattern 212 obtains a positive voltage from the gate pattern 252.
  • An insulating buffer layer 22 is interposed between the light-shielding pattern 212 and the polysilicon pattern 232 and both At least partially overlap, so that the light shielding pattern 212 and the polysilicon pattern 232 form a capacitor through the buffer layer 22 sandwiched therebetween, so that the leakage current of the driving TFT can be reduced, thereby improving the electrical performance of the driving TFT.
  • the third region 203 where the storage capacitor of the array substrate 30 is located further above the base substrate 20.
  • the first region 201, the second region 202 and the third region 203 are parallel to each other.
  • the substrates 20 are sequentially disposed in the direction of the base substrate 20.
  • the first conductive layer further includes a third light-shielding pattern 213 located in the third region 203.
  • the third light-shielding pattern 213 may be formed by the same mask process as the first light-shielding pattern 211 and the second light-shielding pattern 212.
  • the insulating layer further includes a third insulating pattern 243 located in the third region 203.
  • the third insulating pattern 243 is directly formed on the buffer layer 22 and directly above the third light shielding pattern 213.
  • the third insulating pattern 243 The first insulating pattern 241 and the second insulating pattern 242 may be formed by the same etching process.
  • the second conductive layer further includes a third gate pattern 253 located in the third region 203 and on the third insulating pattern 243.
  • the third gate pattern 253 may be the same as the first gate pattern 251 and the second gate pattern. 252 is formed by the same mask process.
  • the third conductive layer further includes a storage electrode pattern 275 located in the third region 203.
  • the storage electrode pattern 275 is formed on the dielectric layer 26 and is located above the third gate pattern 253.
  • the storage electrode pattern 275 may be connected to the first The source pattern 271, the first drain pattern 272, the second source pattern 273, and the second drain pattern 274 are formed by a same mask process.
  • the storage electrode pattern 275 and the third gate pattern 253 form a capacitor by the dielectric layer 26 interposed therebetween.
  • the third gate pattern 253 and the third light-shielding pattern 213 are interposed between the two.
  • the intermediate buffer layer 22 and the third insulation pattern 243 form a capacitor, and these two capacitors can form a storage capacitor of the array substrate 30 in series.
  • the present application also provides a display panel.
  • the display panel may include the array substrate 30 made in the foregoing embodiment, and thus has the same beneficial effects as the display substrate.
  • the main purpose of this application is to design the switching TFT using an amorphous silicon pattern and the driving TFT using a polysilicon pattern based on LTPS technology, thereby reducing production costs, and electrically connecting the gate pattern of the driving TFT to the light-shielding pattern.
  • the light-shielding pattern obtains a positive voltage from the gate pattern, and the light-shielding pattern and the polysilicon pattern form a capacitor by a buffer layer sandwiched therebetween, thereby reducing the leakage current of the driving TFT and improving the electrical performance of the driving TFT.

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Abstract

L'invention concerne également un substrat de matrice (30) et son procédé de fabrication, et un panneau d'affichage comprenant le substrat de matrice (30). Le substrat de matrice (30) a un TFT commutateur utilisant un motif de silicium amorphe, et un TFT d'attaque utilisant un motif de polysilicium sur la base de la technologie LTPS, de sorte que les coûts de production peuvent être réduits. De plus, un motif de grille (252) du TFT d'attaque est électriquement connecté à son motif de protection contre la lumière (212) ; son motif de protection contre la lumière (212) obtient une tension positive du motif de grille (252) ; le motif de protection contre la lumière (212) forme un condensateur pourvu d'un motif de polysilicium (232), de sorte que le courant de fuite du TFT d'attaque peut être réduit, améliorant ainsi la performance électrique du TFT d'attaque.
PCT/CN2018/116325 2018-08-21 2018-11-20 Substrat de matrice et son procédé de fabrication, et panneau d'affichage WO2020037850A1 (fr)

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CN201810955954.6A CN109148535B (zh) 2018-08-21 2018-08-21 阵列基板及其制造方法、显示面板
CN201810955954.6 2018-08-21

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CN104810382A (zh) * 2015-05-07 2015-07-29 深圳市华星光电技术有限公司 Amoled背板的制作方法及其结构
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CN107195634A (zh) * 2017-05-12 2017-09-22 深圳市华星光电技术有限公司 一种tft阵列基板及其制作方法
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