CN103560114B - A kind of tft array substrate and its manufacture method, display device - Google Patents
A kind of tft array substrate and its manufacture method, display device Download PDFInfo
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- CN103560114B CN103560114B CN201310573218.1A CN201310573218A CN103560114B CN 103560114 B CN103560114 B CN 103560114B CN 201310573218 A CN201310573218 A CN 201310573218A CN 103560114 B CN103560114 B CN 103560114B
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- 239000000758 substrate Substances 0.000 title claims abstract description 76
- 238000000034 method Methods 0.000 title claims abstract description 75
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 51
- 239000004065 semiconductor Substances 0.000 claims abstract description 87
- 238000000059 patterning Methods 0.000 claims abstract description 33
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 21
- 230000009466 transformation Effects 0.000 claims abstract description 15
- 238000005516 engineering process Methods 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims description 52
- 229910052751 metal Inorganic materials 0.000 claims description 52
- 238000012545 processing Methods 0.000 claims description 18
- 239000012212 insulator Substances 0.000 claims description 16
- 229910052802 copper Inorganic materials 0.000 claims description 15
- 239000010949 copper Substances 0.000 claims description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 13
- 230000003647 oxidation Effects 0.000 claims description 12
- 238000007254 oxidation reaction Methods 0.000 claims description 12
- BERDEBHAJNAUOM-UHFFFAOYSA-N copper(I) oxide Inorganic materials [Cu]O[Cu] BERDEBHAJNAUOM-UHFFFAOYSA-N 0.000 claims description 11
- 229940112669 cuprous oxide Drugs 0.000 claims description 11
- KRFJLUBVMFXRPN-UHFFFAOYSA-N cuprous oxide Chemical group [O-2].[Cu+].[Cu+] KRFJLUBVMFXRPN-UHFFFAOYSA-N 0.000 claims description 10
- 239000010409 thin film Substances 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 7
- 238000002161 passivation Methods 0.000 claims description 4
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- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
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- 239000007924 injection Substances 0.000 claims 1
- 238000013517 stratification Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 116
- 229920002120 photoresistant polymer Polymers 0.000 description 12
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- 229960004643 cupric oxide Drugs 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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Abstract
The embodiment of the present invention provides a kind of tft array substrate and its manufacture method, display device, is related to display technology field.Vertical stratification TFT production process can be simplified, patterning processes access times are reduced.Array base palte is included in the pattern of the drain electrode of substrate surface formation, the pattern for being formed with semiconductor active layer is handled by semiconductor transformation on the surface of the pattern of drain electrode, the pattern of active electrode is formed on the surface of the pattern of the semiconductor active layer, wherein drain electrode, semiconductor active layer, the pattern of source electrode is formed by a patterning processes.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of tft array substrate and its manufacture method, display device.
Background technology
With developing rapidly for Display Technique, TFT-LCD (Thin Film Transistor Liquid Crystal
Display, Thin Film Transistor-LCD) as a kind of panel display apparatus, because its have small volume, it is low in energy consumption, without spoke
Penetrate and the features such as cost of manufacture is relatively low, and be applied to more and more among high-performance display field.
TFT-LCD is made up of array base palte and color membrane substrates.TFT-LCD of the prior art array base palte is generally by square
Multiple dot structures composition of formation formula arrangement, its typical structure are as shown in figure 1, the grid line 10 and number that intersect including transverse and longitudinal
The multiple pixel cells 12 divided according to line 11, thin film transistor (TFT) is provided with the crossover location of grid line 10 and data wire 11
(TFT).The size of TFT regions is relevant with the pixel aperture ratio of array base palte, and TFT regions are bigger, pixel aperture ratio
It is just smaller, therefore the light emission rate of light can be reduced, so as to influence the display effect of display.
In order to improve the aperture opening ratio of pixel, a kind of vertical TFT structure of top gate type can be used in the prior art, such as Fig. 2 institutes
Show.The TFT of such a structure, its drain electrode 13 and source electrode 14 are made by the way of overlapping, thus with parallel
Source, the TFT of drain electrode compare, and the TFT zone of the top gate type vertical stratification is relatively small, so that pixel region energy
Larger aperture area is accessed, so as to improve pixel aperture ratio.
But in the prior art, as shown in Fig. 2 during top gate type vertical stratification TFT is made, first, being formed
The substrate surface for having the pattern of pixel electrode 15 coats the pattern that a kind of metal material forms drain electrode 13 by patterning processes again, so
The substrate surface deposited semiconductor material of above-mentioned pattern is being formed with afterwards, so as to pass through patterning processes formation semiconductor active layer 16
Pattern；Another metal material is coated again in the substrate surface for being formed with the pattern of semiconductor active layer 16 afterwards, so that logical
Cross the pattern of the electric level 14 in patterning processes formation source；Next patterning processes are passed through in the substrate surface for forming the pattern of active electrode 14
Sequentially form the pattern of grid 17, passivation layer 18 and public electrode 19.So, due to being employed many times in manufacturing process
Coating or depositing operation make it that making manufacturing procedure is complicated, cause low production efficiency, and production cost is improved.And multiple composition work
The use of skill can cause the superposition of mismachining tolerance, so as to reduce product quality.
The content of the invention
Embodiments of the invention provide a kind of tft array substrate and its manufacture method, display device.Vertical junction can be simplified
Structure TFT production process, reduces patterning processes access times.
To reach above-mentioned purpose, embodiments of the invention are adopted the following technical scheme that：
The one side of the embodiment of the present invention provides a kind of manufacture method of tft array substrate, including：
In substrate surface formation the first metal layer；
Semiconductor layer is formed by semiconductor transformation processing on the surface of the first metal layer；
Second metal layer is formed on the surface of the semiconductor layer；
Being formed by patterning processes includes drain electrode, the semiconductor active layer, the pattern of source electrode.
The another aspect of the embodiment of the present invention provides a kind of tft array substrate, including：
Form the pattern in the drain electrode of substrate surface；
The surface of the pattern of the drain electrode handles the pattern for being formed with semiconductor active layer by semiconductor transformation；
The surface of the pattern of the semiconductor active layer forms the pattern of active electrode.
The another aspect of the embodiment of the present invention provides a kind of display device, including any one tft array as described above
Substrate.
The present invention provides a kind of tft array substrate and its manufacture method, display device.This method is included in substrate surface shape
Into the pattern of drain electrode, the pattern of semiconductor active layer is formed by semiconductor transformation processing on the surface of the pattern of drain electrode,
The surface of the pattern of the semiconductor active layer forms the pattern of source electrode, wherein drain electrode, semiconductor active layer, the figure of source electrode
Case is formed by a patterning processes.So, production process can be simplified, manufacture craft is reduced.So as to improve production effect
Rate, reduces production cost.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
A kind of tft array substrate structure top view that Fig. 1 provides for prior art；
A kind of tft array substrate structural representation that Fig. 2 provides for prior art；
Fig. 3 is a kind of manufacture method flow chart of tft array substrate provided in an embodiment of the present invention；
Fig. 4 is the structure and manufacture method schematic diagram of a kind of tft array substrate provided in an embodiment of the present invention；
Fig. 5 is a kind of manufacture method schematic diagram of tft array substrate provided in an embodiment of the present invention；
Fig. 6 is the structural representation of another tft array substrate provided in an embodiment of the present invention；
Fig. 7 is the structural representation of another tft array substrate provided in an embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
The embodiment of the present invention provides a kind of manufacture method of tft array substrate, as shown in Figure 3, Figure 4, including：
S101, the surface of substrate 01 formed the first metal layer 03.Wherein, substrate 01 is transparency carrier, can be used transparent
Glass or transparent resin material are made.
S102, the surface of the first metal layer 03 pass through semiconductor transformation processing formed semiconductor layer 16.
S103, the surface formation second metal layer 04 in semiconductor layer 16.
S104, formed by patterning processes, including drain electrode 13, semiconductor active layer 16, the pattern of source electrode 14.
It should be noted that in the present invention, patterning processes can refer to including photoetching process, or, including photoetching process and
Etch step, while including printing, ink-jet etc. other technique for forming predetermined pattern can also to be used for；Photoetching process, refers to bag
The technique for including the formation figure such as utilization photoresist, mask plate, exposure machine of the technical process such as film forming, exposure, development.Can be according to this
The corresponding patterning processes of structure choice formed in invention.
The present invention provides a kind of manufacture method of tft array substrate.This method is included in substrate surface formation drain electrode
Pattern, is formed the pattern of semiconductor active layer by semiconductor transformation processing on the surface of the pattern of drain electrode, had in the semiconductor
The surface of the pattern of active layer forms the pattern of source electrode, and wherein drain electrode, semiconductor active layer, the pattern of source electrode passes through once
Patterning processes are formed.So, production process can be simplified, manufacture craft is reduced.So as to improve production efficiency, reduction production
Cost.
Further, above-mentioned semiconductor transformation processing can include：
Oxidation is carried out to the first metal layer 03 by oxidation technology and forms the metal oxide layer with characteristic of semiconductor.
Wherein, the oxidation technology includes ion implanting mode or electrochemical means.It is preferred that, the He of the first metal layer 03
Second metal layer 04 can be constituted using metallic copper.Cuprous oxide semiconductive thin film is formed by carrying out oxidation to metallic copper,
Therefore semiconductor layer 16 can be above-mentioned cuprous oxide semiconductive thin film.
Specifically, when the first metal layer 03 and second metal layer 04 are constituted using metallic copper, can be in the first metal layer
03 surface makes it be changed into cuprous nano film by ion implanting mode；Or, the first metal layer 03 is placed in high temperature
Oxygen atmosphere in cause the first metal layer 03 surface formed cuprous nano film；Or, by the first metal layer 03
It is placed under alcoholic environment and make it that the surface of the first metal layer 03 forms cuprous nano film.Then above-mentioned cuprous oxide is received
Rice film is used as semiconductor layer 16.Again in the redeposited layer of metal copper formation second metal layer in surface of above-mentioned semiconductor layer 16
04.So, as long as providing the processing conditions that can be aoxidized to the first metal layer 03, it is possible to form above-mentioned copper-oxygen
Change the structure of cuprous film-copper, said structure is formed without techniques such as multipass coating, sputtering or depositions.So as to
Simplify manufacture craft, reduction difficulty of processing and production cost.Certainly, it is above-mentioned that semiconductor transformation processing only is carried out to the first metal layer
For example, other modes are herein no longer one by one for example, but should all belong to protection scope of the present invention.
It should be noted that the oxide of metallic copper can be cupric oxide and cuprous oxide, they have characteristic of semiconductor,
I.e. at normal temperatures its electric conductivity between conductor (conductor) and insulator (insulator).The embodiment of the present invention is excellent
Cuprous oxide is selected as the pattern for constituting semiconductor active layer 16.Certainly, in embodiments of the present invention, to by taking metallic copper as an example
One metal level 03, semiconductor layer 16 and second metal layer 04 are illustrated, other oxides with characteristic of semiconductor
Corresponding metal is no longer illustrated one by one herein, but should all belong to protection scope of the present invention.
Further, above-mentioned patterning processes can include：
Electrode layer 02 is formed between substrate 01 and the first metal layer 03.
Using intermediate tone mask plate by mask exposure technique sequentially form including first transparency electrode 20, drain electrode 13,
The stepped stacked structure of semiconductor active layer 16, the pattern of source electrode 14.
Wherein, the area of drain electrode 13, semiconductor active layer 16 and the pattern of source electrode 14 is less than first transparency electrode 20
The area of pattern.
Specifically, as shown in figure 5, being sequentially formed with electrode layer 02, the first metal layer 03, semiconductor layer 16, the second gold medal
Belong to the substrate surface coating photoresist 05 of layer 04, processing is exposed to photoresist 05 by intermediate tone mask plate, formation does not expose
Light region P1, half-exposure region P2 and full exposure area P3.Then photoresist 05 is developed, exposure area P1 will be located at
Photoresist be fully retained；It will be removed positioned at half-exposure region P2 photoresist part；By positioned at full exposure area P3 photoetching
Glue is removed completely.Wherein as shown in figure 5, unexposed area P1 and drain electrode 13, semiconductor layer 16, the region of source electrode 14
Position is corresponding；Half-exposure region is corresponding with the position of the region of first transparency electrode 20；On substrate remainder with it is complete
The position of exposure area is corresponding.
After mask exposure is carried out to photoresist, first pass through etching technics and remove electrode corresponding with complete exposure area P3
Layer 02, the first metal layer 03, semiconductor layer 16, second metal layer 04；Ashing processing is carried out to photoresist 05, to remove half-exposure
Region P2 all photoresists 05 and unexposed area P1 part photoresist, then remove half-exposure area by etching technics
The corresponding the first metal layers 03 of domain P2, semiconductor layer 16, second metal layer 04；It is finally that unexposed area P1 photoresist is complete
Remove, being formed on substrate 01 includes first transparency electrode 20, drain electrode 13, semiconductor layer 16, the pattern of source electrode 14.So
One, it can be realized and be sequentially formed by a patterning processes on substrate 01 including the first transparent electricity using half-tone mask plate
Pole 20, drain electrode 13, semiconductor active layer 16, the pattern of source electrode 14.
Further, as shown in fig. 6, this method can also include：
Gate insulator 21, grid 17 are sequentially formed forming the substrate surface of source electrode 14 pattern by patterning processes
Pattern.So as to complete the making of tft array substrate.
Specifically, the pattern of the pattern of grid 17 and semiconductor active layer 16 is located at the two of the pattern of gate insulator 21 respectively
Side.And the pattern of grid 17 is located remotely from the side of substrate 01, drain electrode 13, active layer 16, source electrode 14 and grid 17
Stack and form along the direction perpendicular to substrate 01 successively.So, it is possible to form the tft array base of top gate type vertical stratification
Plate.The TFT of such a structure, its drain electrode 13 and source electrode 14 are made by the way of overlapping, therefore are had with traditional
The TFT structure of raceway groove compares, and the TFT zone of the top gate type vertical stratification is relatively small, so that pixel region energy
Larger aperture area is accessed, so as to improve pixel aperture ratio.
Further, as shown in fig. 7, also including before the step of forming 16 pattern of semiconductor active layer：
Form the pattern of reflecting electrode 22；Reflecting electrode 22 is with drain electrode 13 with the same material of layer.
Wherein, the area of reflecting electrode 22 is less than the area of first transparency electrode 20.That is, the reflecting electrode 22 can not be complete
It is covered in first transparency electrode 20.For example, for the array base palte of half-reflection and half-transmission structure, it is anti-that reflecting electrode 22 is constituted
The area for penetrating region is a part for pixel region, and another part of pixel region is above-mentioned reflecting electrode 22 unlapped the
The regional transmission that one transparency electrode 20 is constituted.
Specifically, being formed while drain electrode 13 being formed on substrate using foregoing mask exposure technique with this with being somebody's turn to do
Drain electrode 13 is with reflecting electrode 22 of the layer with material.So, it is possible to complete the making of Transflective array base palte.Nothing
The technique for making reflecting electrode need to additionally be increased, so as to simplify manufacturing procedure, productivity ratio is improved.
It should be noted that the display processed using the array base palte of this half-reflection and half-transmission formula is in its transmission region
The light that can be sent using backlight is shown as light source, and reflector space can be reflected with that will inject display natural light
Shown afterwards as light source.So, Transflective display be can save electric power again can be in night or low-light
Used under environment.
Further, as shown in fig. 7, the manufacture method of the tft array substrate can also include：
Passivation layer is sequentially formed being formed with the substrate surface of gate insulator 21, the pattern of grid 17 by patterning processes
18th, the pattern of second transparency electrode 23.
It should be noted that array base palte provided in an embodiment of the present invention goes for TN, (Twist Nematic are turned round
Qu Xianglie) (Advanced-Super Dimensional Switching, referred to as ADS, senior super Wei Chang are opened by type, AD-SDS
Close) production of the liquid crystal display device of type such as type, IPS (In Plane Switch, transverse electric field effect) type.It is no matter above-mentioned
Which kind of liquid crystal display device all includes the color membrane substrates and array base palte shaped to box.Unlike, the public affairs of TN type display devices
Common electrode is arranged on color membrane substrates, and pixel electrode is arranged on array base palte；ADS types display device and IPS type display devices
Public electrode and pixel electrode be arranged on array base palte.
As shown in fig. 7, first transparency electrode 20 is arranged on array base palte with second transparency electrode 23.Optionally,
One transparency electrode 20 is pixel electrode, and second transparency electrode 23 is public electrode；Or,
First transparency electrode 20 can also be public electrode, and second transparency electrode 23 can also be pixel electrode.Specifically,
Can by being patterned PROCESS FOR TREATMENT to electrode layer 02, while form first transparency electrode 20 and conductive electrode structure, wherein
First transparency electrode 20 and conductive electrode are not electrically connected, and the conductive electrode is connected with drain electrode 13.Work as first transparency electrode
20 be public electrode, and when second transparency electrode 23 is pixel electrode, the pixel electrode can be by positioned at the He of gate insulator 21
Via on passivation layer 18 is electrically connected with drain electrode 13 (or conductive electrode).Certainly, the above is also only to specific in the present invention
Electrode structure for example, and not to the limitation done of the present invention.
Specifically, first transparency electrode 20 can be planar structure, second transparency electrode 23 can be spaced narrow
Crack structure；Or, first transparency electrode 20 and second transparency electrode 23 can be narrow slit structure.
For example, array base palte provided in an embodiment of the present invention goes for AD-SDS (Advanced-Super
Dimensional Switching, referred to as ADS, senior super dimension field switch) type liquid crystal display device production.With first
Transparency electrode 20 and second transparency electrode 23 are exemplified by the electrode of spaced narrow slit structure, the array of such a structure
Substrate is often used as the production of ADS type liquid crystal display devices, and ADS technologies pass through produced by pixel electrode edge in same plane
Parallel electric field and the longitudinal electric field formation multi-dimensional electric field that produces of pixel electrode layer and public electrode interlayer, make picture in liquid crystal cell
All aligned liquid-crystal molecules can produce rotation conversion between plain electrode, directly over electrode, with other kinds of display device phase
Than ADS type liquid crystal display devices further increase planar orientation system liquid crystal operating efficiency and increase light transmission efficiency.
In the array base palte of ADS type display devices, public electrode and pixel electrode can be set with different layer, wherein positioned at upper
The electrode of layer includes multiple slit-type electrodes, and the electrode positioned at lower floor is comprising multiple slit-type electrodes or for plate-shaped electrode.
It is that at least two patterns, the different layer setting of at least two patterns refers to, respectively will at least that different layer, which is set,
Double-layer filmses pass through patterning processes at least two patterns of formation.Different for two kinds of patterns layer, which is set, to be referred to, by patterning processes, by
Double-layer filmses respectively form a kind of pattern.For example, public electrode and the different layer of pixel electrode set and referred to：It is thin by first layer electrically conducting transparent
Film forms upper electrode by second layer transparent conductive film by patterning processes formation lower electrode by patterning processes, wherein,
Lower electrode is public electrode (or pixel electrode), and upper electrode is pixel electrode (or public electrode).
In the array base palte of IPS type display devices, public electrode and pixel electrode are set with layer, and public electrode is comprising more
Individual slit-type electrodes, pixel electrode includes interval setting between multiple slit-type electrodes, multiple slit-type electrodes.
It is at least two patterns to be set with layer；At least two patterns are set with layer to be referred to：By same film
Pass through patterning processes at least two patterns of formation.For example, public electrode and pixel electrode set with layer and referred to：Transparent led by same
Conductive film passes through patterning processes formation pixel electrode and public electrode.Wherein, pixel electrode refer to by switch element (for example,
Can be thin film transistor (TFT)) electrode that is electrically connected with data wire, public electrode refers to the electrode electrically connected with public electrode wire.
The embodiment of the present invention provides a kind of tft array substrate, as shown in figure 4, including：
Form the pattern in the drain electrode 13 on the surface of substrate 01.Wherein, substrate 01 is transparency carrier, can use transparent glass
Glass or transparent resin material are made.
The surface of the pattern of drain electrode 13 handles the pattern for being formed with semiconductor active layer 16 by semiconductor transformation.
The surface of the pattern of semiconductor active layer 16 forms the pattern of active electrode 14.
It should be noted that in the present invention, patterning processes can refer to including photoetching process, or, including photoetching process and
Etch step, while including printing, ink-jet etc. other technique for forming predetermined pattern can also to be used for；Photoetching process, refers to bag
The technique for including the formation figure such as utilization photoresist, mask plate, exposure machine of the technical process such as film forming, exposure, development.Can be according to this
The corresponding patterning processes of structure choice formed in invention.
It should be noted that above-mentioned semiconductor transformation processing can include：
Oxidation is carried out to the first metal layer 03 by oxidation technology and forms the metal oxide layer with characteristic of semiconductor.
Wherein, the oxidation technology includes ion implanting mode or electrochemical means.It is preferred that, the He of the first metal layer 03
Second metal layer 04 can be constituted using metallic copper.Cuprous oxide semiconductive thin film is formed by carrying out oxidation to metallic copper,
Therefore semiconductor layer 16 can be above-mentioned cuprous oxide semiconductive thin film.
Specifically, when the first metal layer 03 and second metal layer 04 are constituted using metallic copper, can be in the first metal layer
03 surface makes it be changed into cuprous nano film by ion implanting mode；Or, the first metal layer 03 is placed in high temperature
Oxygen atmosphere in formed cuprous nano film；Or, the first metal layer 03 is placed under alcoholic environment to be formed
Cuprous nano film.Then it regard above-mentioned cuprous nano film as semiconductor layer 16.Again in above-mentioned semiconductor layer 16
The redeposited layer of metal copper formation second metal layer 04 in surface.So, as long as providing that the first metal layer 03 can be entered
The processing conditions of row oxidation, it is possible to form the structure of above-mentioned copper-cuprous oxide film-copper, without multipass coating, splashes
The technique such as penetrate or deposit to form said structure.So as to simplify manufacture craft, reduction difficulty of processing and production cost.Certainly,
It is above-mentioned only to the first metal layer carry out semiconductor transformation processing for example, other modes are no longer illustrated one by one herein
It is bright, but should all belong to protection scope of the present invention.
It should be noted that the oxide of metallic copper can be cupric oxide and cuprous oxide, they have characteristic of semiconductor,
I.e. at normal temperatures its electric conductivity between conductor (conductor) and insulator (insulator).The embodiment of the present invention is excellent
Cuprous oxide is selected as the pattern for constituting semiconductor active layer 16.Certainly, in embodiments of the present invention, to by taking metallic copper as an example
One metal level 03, semiconductor layer 16 and second metal layer 04 are illustrated, other oxides with characteristic of semiconductor
Corresponding metal is no longer illustrated one by one herein, but should all belong to protection scope of the present invention.
The present invention provides a kind of tft array substrate.The array base palte is included in the pattern of the drain electrode of substrate surface formation,
The pattern for being formed with semiconductor active layer is handled by semiconductor transformation on the surface of the pattern of drain electrode, in the semiconductor active layer
The surface of pattern form the pattern of active electrode, wherein drain electrode, semiconductor active layer, the pattern of source electrode pass through a structure
Figure technique is formed.So, production process can be simplified, manufacture craft is reduced.So as to improve production efficiency, reduction is produced into
This.
Further, as shown in figure 4, being formed with first transparency electrode 20 between substrate 01 and drain electrode 13.
First transparency electrode 20, drain electrode 13, semiconductor active layer 16, the pattern of source electrode 14 are stepped stacked structure.
Wherein, the area of drain electrode 13, semiconductor active layer 16 and the pattern of source electrode 14 is less than first transparency electrode 20
The area of pattern.Above-mentioned stepped stacked structure can be formed using intermediate tone mask plate by a patterning processes, so as to
To reduce the patterning processes for making array base palte.
Further, as shown in fig. 6, the tft array substrate also includes：
The surface of the pattern of source electrode 14 is formed with the pattern of gate insulator 21；
The surface of gate insulating layer pattern 21 is formed with the pattern of grid 17.
Wherein, the pattern of the pattern of grid 17 and semiconductor active layer 16 is located at the two of the pattern of gate insulator 21 respectively
Side.So, it is possible to form the tft array substrate of top gate type vertical stratification.The TFT of such a structure, its drain electrode
13 and source electrode 14 made by the way of overlapping, therefore compared with traditional TFT structure with raceway groove, the top gate type hangs down
The TFT zone of straight structure is relatively small, so that pixel region can obtain larger aperture area, so as to improve picture
Plain aperture opening ratio.
The embodiment of the present invention provides a kind of display device, including any one tft array substrate as described above.With with
The array base palte identical beneficial effect that present invention is provided, because array base palte has entered in the aforementioned embodiment
Detailed description is gone, here is omitted.
It is any that the display device is specifically as follows liquid crystal display, LCD TV, DPF, mobile phone, panel computer etc.
Liquid crystal display product or part with display function.
The present invention provides a kind of display device.The display device includes tft array substrate.The tft array substrate is included in
The pattern of the drain electrode of substrate surface formation, being formed with semiconductor by semiconductor transformation processing on the surface of the pattern of drain electrode has
The pattern of active layer, the pattern of active electrode is formed on the surface of the pattern of the semiconductor active layer, and wherein drain electrode, semiconductor has
Active layer, the pattern of source electrode are formed by a patterning processes.So, production process can be simplified, manufacture craft is reduced.
So as to improve production efficiency, production cost is reduced.
The foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, any
Those familiar with the art the invention discloses technical scope in, change or replacement can be readily occurred in, should all be contained
Cover within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (13)
1. a kind of manufacture method of tft array substrate, it is characterised in that including：
Electrode layer is formed on substrate；
Forming the substrate surface formation the first metal layer of the electrode layer；
Semiconductor layer is formed by semiconductor transformation processing on the surface of the first metal layer；
Second metal layer is formed on the surface of the semiconductor layer；
The pattern of first transparency electrode, drain electrode, the semiconductor active layer, source electrode is included by patterning processes formation, its
In：The pattern of the first transparency electrode is formed by the electrode layer, and the pattern of the drain electrode is by the first metal layer shape
Into the pattern of the semiconductor active layer is formed by the semiconductor layer, and the pattern of the source electrode is by the second metal layer
Formed；
The pattern of gate insulator, grid is sequentially formed by patterning processes in the substrate surface for the pattern for forming source electrode；Institute
The pattern for stating grid is located at the top that the drain electrode and reflecting electrode are connected, and is close to the gate insulator；
While the pattern of the drain electrode is formed, the pattern of the reflecting electrode is also formed；The pattern of the reflecting electrode
For planar pattern, the reflecting electrode is with the drain electrode with the same material of layer；
Wherein, the area of the reflecting electrode is less than the area of the first transparency electrode.
2. the manufacture method of tft array substrate according to claim 1, it is characterised in that semiconductor transformation processing includes：
Oxidation is carried out to the first metal layer by oxidation technology and forms the metal oxide layer with characteristic of semiconductor.
3. the manufacture method of tft array substrate according to claim 2, it is characterised in that
The first metal layer and the second metal layer are made of metallic copper；
The semiconductor layer is cuprous oxide semiconductive thin film.
4. the manufacture method of tft array substrate according to claim 1 or 2, it is characterised in that the patterning processes bag
Include：
Sequentially formed using intermediate tone mask plate by mask exposure technique including the first transparency electrode, drain electrode, described
The stepped stacked structure of semiconductor active layer, the source electrode pattern；
Wherein, the area of the drain electrode, the semiconductor active layer and the source electrode pattern is transparent less than described first
The area of electrode pattern.
5. the manufacture method of tft array substrate according to claim 1, it is characterised in that the pattern of the grid and institute
The pattern for stating semiconductor active layer is located at the both sides of the gate insulating layer pattern respectively.
6. the manufacture method of tft array substrate according to claim 5, it is characterised in that also include：
Be formed with the gate insulator, the gate pattern substrate surface by patterning processes sequentially form passivation layer,
The pattern of second transparency electrode.
7. the manufacture method of tft array substrate according to claim 6, it is characterised in that
The first transparency electrode is pixel electrode, and second transparency electrode is public electrode；Or,
The first transparency electrode is public electrode；Second transparency electrode is pixel electrode.
8. the manufacture method of tft array substrate according to claim 3, it is characterised in that the oxidation technology includes：From
Sub- injection mode or electrochemical means.
9. a kind of tft array substrate, it is characterised in that including：
The pattern of the first transparency electrode of substrate surface；
The pattern of the drain electrode on the surface of the pattern of the first transparency electrode；The surface of the pattern of the drain electrode is by partly leading
The pattern for the semiconductor active layer that body processing is formed；
The pattern of the source electrode on the surface of the pattern of the semiconductor active layer；
Gate insulator that the substrate surface of the pattern of the source electrode is sequentially formed by patterning processes, the pattern of grid；Institute
The pattern for stating grid is located at the top that the drain electrode and reflecting electrode are connected, and is close to the gate insulator；
While the pattern of the drain electrode is formed, the pattern of the reflecting electrode is also formed；The pattern of the reflecting electrode
For planar pattern, the reflecting electrode is with the drain electrode with the same material of layer；
Wherein, the area of the reflecting electrode is less than the area of the first transparency electrode.
10. tft array substrate according to claim 9, it is characterised in that
The first transparency electrode, the drain electrode, the semiconductor active layer, the source electrode pattern stack knot to be stepped
Structure；
Wherein, the area of the drain electrode, the semiconductor active layer and the source electrode pattern is transparent less than described first
The area of electrode pattern.
11. tft array substrate according to claim 10, it is characterised in that also include：
The surface of the source electrode pattern is formed with the pattern of gate insulator；
The surface of the gate insulating layer pattern is formed with the pattern of grid.
12. tft array substrate according to claim 11, it is characterised in that also include：
The pattern of the grid is located at the both sides of the gate insulating layer pattern with the pattern of the semiconductor active layer respectively.
13. a kind of display device, it is characterised in that including the tft array substrate as described in claim any one of 9-12.
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| CN104638016A (en) * | 2015-01-28 | 2015-05-20 | 京东方科技集团股份有限公司 | Thin film transistor and manufacturing method of thin film transistor, array substrate and manufacturing method of array substrate, and display device |
| CN104979406B (en) * | 2015-07-31 | 2018-05-25 | 京东方科技集团股份有限公司 | Thin film transistor (TFT), array substrate and preparation method thereof and display device |
| US10782580B2 (en) * | 2016-04-29 | 2020-09-22 | Samsung Display Co., Ltd. | Array substrate, liquid crystal display device having the same, and method for manufacturing array substrate |
| CN108899331A (en) * | 2018-07-16 | 2018-11-27 | 京东方科技集团股份有限公司 | Electronic paper display substrate and preparation method thereof, display device |
| CN109872973A (en) * | 2019-01-16 | 2019-06-11 | 南京中电熊猫液晶显示科技有限公司 | A kind of array substrate and its manufacturing method |
| US11735605B2 (en) | 2019-11-12 | 2023-08-22 | Boe Technology Group Co., Ltd. | Display substrate and method for manufacturing the same, and display apparatus |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0176179B1 (en) * | 1995-12-22 | 1999-03-20 | 김광호 | Vertical type thin film transistor |
| CN101807550A (en) * | 2009-02-18 | 2010-08-18 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method thereof and LCD monitor |
| CN103022148A (en) * | 2012-12-14 | 2013-04-03 | 京东方科技集团股份有限公司 | Array substrate, manufacture method of array substrate and display device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3479375B2 (en) * | 1995-03-27 | 2003-12-15 | 科学技術振興事業団 | Metal oxide semiconductor device in which a pn junction is formed with a thin film transistor made of a metal oxide semiconductor such as cuprous oxide, and methods for manufacturing the same |
| CN101833193B (en) * | 2009-03-13 | 2014-04-02 | 北京京东方光电科技有限公司 | Semi-transparent type crystal liquid display, transparent substrate and manufacturing method thereof |
| JP5656325B2 (en) * | 2009-11-13 | 2015-01-21 | 株式会社半導体エネルギー研究所 | Nonlinear element and display device |
| US9053937B2 (en) * | 2010-04-15 | 2015-06-09 | Electronics And Telecommunications Research Institute | Semiconductor device and method of manufacturing the same |
-
2013
- 2013-11-15 CN CN201310573218.1A patent/CN103560114B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0176179B1 (en) * | 1995-12-22 | 1999-03-20 | 김광호 | Vertical type thin film transistor |
| CN101807550A (en) * | 2009-02-18 | 2010-08-18 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method thereof and LCD monitor |
| CN103022148A (en) * | 2012-12-14 | 2013-04-03 | 京东方科技集团股份有限公司 | Array substrate, manufacture method of array substrate and display device |
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