CN102646630B - TFT-LCD (thin film transistor liquid crystal display) array substrate structure and manufacturing method thereof - Google Patents
TFT-LCD (thin film transistor liquid crystal display) array substrate structure and manufacturing method thereof Download PDFInfo
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- CN102646630B CN102646630B CN201110307042.6A CN201110307042A CN102646630B CN 102646630 B CN102646630 B CN 102646630B CN 201110307042 A CN201110307042 A CN 201110307042A CN 102646630 B CN102646630 B CN 102646630B
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Abstract
The invention relates to the liquid crystal display field, and discloses a method for making a TFT-LCD (thin film transistor liquid crystal display) array substrate and products thereof, which saves production flow and reduces product cost. The method comprises: forming a pixel electrode layer and a source and a drain electrode layers on a glass substrate provided with a semiconductor active layer by using a mask technology, and forming a pixel electrode on the pixel electrode layer by using the mask technology, forming a source and a drain electrodes on the source and the drain electrode layers, and forming a gate electrode on a gate layer through treatments of corrosion, ashing, photoresist peeling, and recorrosion or the like by using a gray level mask technology and a developing technology on an insulating layer, a gate layer and a photoresist which form in order in a pixel area, a data area and a gate area, thereby realizing first construction of the source and the drain electrodes and then construction of gate electrode. The production flow of the TFT-LCD array substrate is fished only through three mask technologies, the production flow is greatly saved and the production cost is reduced.
Description
Technical field
The present invention relates to field of liquid crystal display, particularly a kind of method and corresponding TFT-LCD array base palte and TFT-LCD that manufactures TFT-LCD array base palte.
Background technology
Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Display, be called for short: TFT-LCD) there is the features such as volume is little, low in energy consumption, radiationless, in current flat panel display market, having occupied very most is a senior super dimension switch technology (ADSDS, ADvanced Super Dimension Switch, is called for short ADS) TFT-LCD of type.Its electric field producing by electric field that in same plane, gap electrode edge produces and gap electrode layer and plate electrode interlayer forms multi-dimensional electric field, make in liquid crystal cell between gap electrode, directly over electrode, all aligned liquid-crystal molecules can both produce rotation, thereby improved liquid crystal operating efficiency and increased light transmission efficiency.Senior super dimension field switch technology can improve the picture quality of TFT-LCD product, has high-resolution, high permeability, low-power consumption, wide visual angle, high aperture, low aberration, without advantages such as water of compaction ripples (push Mura).
For TFT-LCD, its topmost parts are tft array substrate, consult shown in Fig. 1, and under prior art, the manufacture process of the tft array substrate of a senior super dimension switch technology type is as follows:
Step 1-4: the pixel region (Pixel region) at glass substrate 0 forms the first pixel electrode layer 1, and adopt masking process to form the first pixel electrode on the first pixel electrode layer 1 forming.
Specifically comprise: suppose that the etching material that the first pixel electrode layer adopts is ITO, the pixel region at glass substrate 0 forms ITO layer, then, on the ITO layer forming, adopt mask (Mask) technique to form photoresist, again the ITO layer without mask is carried out to etching, finally, photoresist is peeled off, thereby based on ITO layer, formed the first pixel electrode in Pixel region.
Step 5-8: pixel region and area of grid (Gate Pad) at the glass substrate 0 after step 1-4 form grid layer, and form gate electrode 2 according to masking process on the layer forming.
Specifically comprise: the good metal of the conductivity of usining is as material, pixel region and area of grid at glass substrate 0 form grid layer, then, on the grid layer forming, mask applies photoresist, adopts masking process to expose and development treatment to photoresist, and the photoresist of reserve area is not removed, the grid layer of again mask having been removed to photoresist carries out etching, finally, photoresist is peeled off, thereby based on grid layer, formed gate electrode 2 at pixel region and area of grid.
Step 9-10: pixel region, area of grid and the data area on the glass substrate 0 after step 5-8 (Data Pad) forms insulating barrier 3, semiconductor layer 4 and source-drain electrode 5(SD layer layer by layer).
Step 11: form photoresist 6 on the source-drain electrode layer 5 of pixel region and data area formation.
Step 12: do not carry out etching for the first time to be coated with the source-drain electrode layer 5 of photoresist 6 after step 11.
Step 13: do not carry out etching for the first time to be coated with the semiconductor layer 4 of source-drain electrode layer 5 after step 12.
Step 14: the photoresist 6 forming on pixel region and data area is carried out to ashing according to composition technique.
Step 15: the source-drain electrode layer 5 exposing after step 14 is carried out to etching for the second time, thereby form source-drain electrode at pixel region.
Step 16-17: the semiconductor layer 4 exposing after step 15 is carried out to etching, and photoresist residual on pixel region and data area 6 is peeled off.
Step 18-21: form the second insulating barrier 7 on pixel region, area of grid and data area on the glass substrate 0 after step 16-17, and on pixel region, area of grid and data area, form photoresist according to masking process, to the second insulating barrier 7 on the pixel region without mask and data area, the second insulating barrier 7 on area of grid and the first insulating barrier 3 carry out etching again.
Step 22-25: form common electrode layer 8 on pixel portion, area of grid and data area on the glass substrate 0 after step 18-21, and form public electrode according to masking process in the common electrode layer 8 forming.
Specifically comprise: suppose that the selective etch material that common electrode layer adopts is ITO, on pixel region, area of grid and the data area of glass substrate 0, form ITO layer, then, on the ITO layer forming, adopt masking process to form photoresist, again the ITO layer without mask is carried out to etching, finally, photoresist is peeled off, thereby based on ITO layer, formed public electrode on pixel region, area of grid and data area.
From above-mentioned flow process, can find out, in the production technology of the TFT-LCD array base palte of traditional ADS type, need to carry out mask 5 times, technological process is complicated, and manufacturing cost is higher.
In view of this, a kind of method of TFT-LCD array base palte of new generation ADS type need to be proposed, to simplify above-mentioned flow process.
Summary of the invention
The embodiment of the present invention provides a kind of method and corresponding TFT-LCD array base palte and TFT-LCD of the TFT-LCD of manufacture array base palte, in order to simplify the technological process of producing TFT-LCD array base palte, reduces production costs.
The concrete technical scheme that the embodiment of the present invention provides is as follows:
A method of manufacturing TFT-LCD array base palte, comprising:
Pixel region at glass substrate (0) forms semiconductor layer (A), and adopts masking process at the upper semiconductor active layer that forms of described semiconductor layer (A);
On the pixel region of described glass substrate (0) and data area, order forms pixel electrode layer (B) and source-drain electrode layer (C), and the upper pixel electrode that forms of the pixel electrode layer (B) that adopts masking process to form at pixel region, the upper source-drain electrode that forms of the source-drain electrode layer (C) forming at pixel region;
On pixel region, data area and area of grid on glass substrate (0), order forms insulating barrier (D), grid layer (E) and photoresist (F), after adopting gray level mask technique and developing process to process photoresist (F), form and remove region, complete reserve area, first's reserve area and second portion reserve area completely, wherein, the photoresist thickness of first's reserve area is greater than the photoresist thickness of second portion reserve area;
In data area on glass substrate (0), to removing grid layer (E) and the insulating barrier (D) in region completely, carry out etching, and the photoresist covering on pixel region, data area and area of grid (F) is carried out to ashing, and the grid layer (E) exposing on the pixel region on glass substrate (0) is carried out to etching, and the photoresist (F) covering on pixel region, data area and area of grid on glass substrate (0) is carried out to ashing again after photoresist (F) ashing;
On pixel region, data area and area of grid on glass substrate (0), form common electrode layer (G), and the photoresist (F) that is coated with common electrode layer (G) is peeled off, and the grid layer (E) of exposure after photoresist (F) is peeled off is carried out to etching, on the grid layer (E) of pixel region, form gate electrode, in the common electrode layer (G) of pixel region, form public electrode.
In the embodiment of the present invention, when generating TFT-LCD array base palte, first construct source-drain electrode, construct again gate electrode, the position of source-drain electrode and gate electrode compare with traditional processing technology just in time contrary, like this, by 3 masking process, can complete the production procedure of TFT-LCD array base palte, with respect to 5 traditional masking process, greatly save production procedure, reduced production cost.
accompanying drawing explanation
Fig. 1 is the TFT-LCD array base palte generating process schematic flow sheet of a senior super dimension switch technology type under prior art;
Fig. 2 A-2J is the TFT-LCD array base palte generating process schematic flow sheet of the middle-and-high-ranking super dimension switch technology type of the embodiment of the present invention;
Fig. 3 is the TFT-LCD array base palte generating process flow chart of the middle-and-high-ranking super dimension switch technology type of the embodiment of the present invention;
Fig. 4 is the TFT-LCD structural representation of the middle-and-high-ranking super dimension switch technology type of the embodiment of the present invention.
Description of reference numerals:
In Fig. 1: 0-glass substrate, 1-the first pixel electrode layer, 2-grid layer, 3-the first insulating barrier, 4-semiconductor layer, 5-source-drain electrode layer, 6-photoresist, 7-the second insulating barrier, 8, common electrode layer;
In Fig. 2: 0-glass substrate, A-semiconductor layer, B-pixel electrode layer, C-source-drain electrode layer, D-insulating barrier, E-grid layer, F-photoresist, G-common electrode layer.
Embodiment
In order to simplify the technological process of producing TFT-LCD array base palte, reduce production costs, in the embodiment of the present invention, when generating TFT-LCD array base palte, first construct source-drain electrode, construct again gate electrode, be the position of source-drain electrode and gate electrode, compare with traditional processing technology just in time contrary, like this, can effectively save production technology, reduce production costs.
Below in conjunction with accompanying drawing, the preferred embodiment of the present invention is elaborated.
Consult shown in Fig. 2 A-2J and Fig. 3, in the embodiment of the present invention, the detailed process of the TFT-LCD array base palte generating process flow process of a senior super dimension switch technology type is as follows:
Step 300(corresponding diagram 2A): the pixel region at glass substrate 0 forms semiconductor layer A and adopts masking process to form semiconductor active layer on the semiconductor layer A of formation.
Specifically comprise: the pixel region at glass substrate 0 forms semiconductor layer A, then, on the semiconductor layer A forming, adopt masking process to form photoresist, again the semiconductor layer A without mask is carried out to etching, finally, photoresist is peeled off, thereby formed semiconductor active layer at pixel region based semiconductor layer A.
Step 301(corresponding diagram 2B): on the pixel region on glass substrate 0 and data area, order forms pixel electrode layer B and source-drain electrode layer C(is SD layer), and form pixel electrode on the pixel electrode layer B that adopts masking process to form at pixel region, and form source-drain electrode on the source-drain electrode layer C forming at pixel region.
Wherein, pixel electrode is to be formed by the part not covered by source-drain electrode on pixel electrode layer B, and the part being covered by source-drain electrode also adopts pixel electrode material, and its material is transparence.
Preferably, pixel electrode layer B can adopt selective etch material, for example, and tin indium oxide (ITO), indium zinc oxide (IZO) etc.And source-drain electrode layer C can adopt the metal of good conductivity, for example, molybdenum (Mo), aluminium (AL), titanium (Ti) and copper (Cu) etc.
Specifically comprise: suppose that the material that pixel electrode layer B adopts is ITO, and the material that source-drain electrode C adopts is Mo, in pixel region and the data area of glass substrate 0, sequentially form ITO layer and Mo layer, then, on the Mo layer forming, adopt intermediate tone mask (HTM, Halfton Mask) technique forms photoresist, again the Mo layer without mask and ITO layer are carried out to etching, then, photoresist is carried out to ashing, and the Mo layer exposing after ashing is carried out to etching for the second time, then, take current ITO layer and Mo layer is mask, the semiconductor layer A that ITO layer is exposed after etching carries out etching for the second time, thereby form pixel electrode on the ITO of pixel region layer, and form source-drain electrode at the Mo of pixel region layer, simultaneously, on the ITO of data area layer and Mo layer, also formed corresponding wiring.
Step 302(corresponding diagram 2C): on the pixel region on glass substrate 0, data area and area of grid, order forms insulating barrier D and grid layer E.
Preferably, insulating barrier D can adopt the good material of insulation property, for example, and silicon nitride (SINx), silicon oxynitride (SiON) etc.And grid layer E can adopt conductive metal material, comprise Mo, AL, Ti and Cu etc.
Step 303(corresponding diagram 2D): on the grid layer E of the pixel region on glass substrate 0, data area and area of grid, adopt masking process form photoresist F and carry out development treatment.
Be specially: consult shown in Fig. 2 D, on the grid layer E of pixel region, data area and the area of grid of employing gray level mask technique on glass substrate 0, form after photoresist F, adopt developing process to process photoresist (F), formed and removed region, complete reserve area, first's reserve area and second portion reserve area completely, wherein, the photoresist thickness of first's reserve area is greater than the photoresist thickness of second portion reserve area.
Step 304(corresponding diagram 2E): in the data area on glass substrate 0 to not being coated with the region of removal completely that photoresist F(is photoresist) grid layer E and insulating barrier D carry out etching.Then the photoresist F covering on pixel region, data area and area of grid is carried out to ashing, thereby remove the photoresist of second portion reserve area.
Step 305(corresponding diagram 2F): the grid layer E exposing after photoresist F ashing on the pixel region on glass substrate 0 is carried out to etching.
Step 306(corresponding diagram 2G): the photoresist F covering on the pixel region on glass substrate 0, data area and area of grid is carried out to ashing again, thereby remove the photoresist of first's reserve area.
Step 307(corresponding diagram 2H): on the pixel region on coloured glaze substrate 0, data area and area of grid, form common electrode layer G.
Preferably, the etching material that common electrode layer G adopts, can comprise ITO and IZO etc.
Step 308(corresponding diagram 2I): the photoresist F that is coated with common electrode layer G on the pixel region on coloured glaze substrate 0, data area and area of grid is peeled off.
Preferably, common electrode layer G can ITO, IZO etc.
Step 309(corresponding diagram 3J): the grid layer E exposing after photoresist F peels off on the pixel region on coloured glaze substrate 0, data area and area of grid is carried out to etching, thereby on the grid layer E of pixel region, form on gate electrode, the common electrode layer G at pixel region and form public electrode, and the grid layer E on data area and area of grid and public electrode G formation corresponding wiring line.
So far, the manufacturing process flow of TFT-LCD array base palte completes.
Based on above-described embodiment, to consult shown in Fig. 4, in the present embodiment, the TFT-LCD array base palte generating through above-mentioned technological process comprises:
Be positioned at the semiconductor active layer being formed by semiconductor layer A on pixel region on glass substrate 0;
Cover the pixel electrode being formed by the pixel electrode layer B not covered by source-drain electrode on described semiconductor active layer;
Cover the upper source-drain electrode being formed by source-drain electrode layer C of described pixel electrode layer B;
Cover the insulating barrier D on described source-drain electrode;
Cover the gate electrode being formed by grid layer E on described insulating barrier D;
Cover the public electrode being formed by common electrode layer G on described gate electrode.
Based on technique scheme, a kind of TFT-LCD, comprises above-mentioned TFT-LCD array base palte.
In sum, in the embodiment of the present invention, when generating TFT-LCD array base palte, first construct source-drain electrode, construct again gate electrode, be the position of source-drain electrode and gate electrode, compare with traditional processing technology just in time contrary, like this, by 3 masking process, can complete the production procedure of TFT-LCD array base palte, with respect to 5 traditional masking process, greatly save production procedure, reduced production cost.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (4)
1. a method of manufacturing Thin Film Transistor-LCD TFT-LCD array base palte, is characterized in that, comprising:
Pixel region at glass substrate forms semiconductor layer, and adopts masking process to form semiconductor active layer on described semiconductor layer;
On the pixel region of described glass substrate and data area, order forms pixel electrode layer and source-drain electrode layer, and form pixel electrode on the pixel electrode layer that adopts masking process to form at pixel region, on the source-drain electrode layer of pixel region, form source-drain electrode;
On pixel region on glass substrate, data area and area of grid, order forms insulating barrier, grid layer and photoresist, after adopting gray level mask technique and developing process to process photoresist, form and remove region, complete reserve area, first's reserve area and second portion reserve area completely, wherein, the photoresist thickness of first's reserve area is greater than the photoresist thickness of second portion reserve area;
In data area on glass substrate, to removing grid layer and the insulating barrier in region completely, carry out etching, and the photoresist covering on pixel region, data area and area of grid is carried out to ashing, and the grid layer exposing on the pixel region on glass substrate is carried out to etching, and the photoresist covering on the pixel region on glass substrate, data area and area of grid is carried out to ashing again after photoresist ashing;
On pixel region on glass substrate, data area and area of grid, form common electrode layer, and the photoresist that is coated with common electrode layer is peeled off, and the grid layer exposing after photoresist lift off is carried out to etching, on the grid layer of pixel region, form gate electrode, in the common electrode layer of pixel region, form public electrode.
2. the method for claim 1, is characterized in that, described pixel electrode layer and common electrode layer adopt tin indium oxide ITO or indium zinc oxide IZO.
3. the method for claim 1, is characterized in that, described source-drain electrode layer and grid layer adopt conductive metal material, comprise molybdenum Mo, aluminium AL, titanium Ti or copper Cu.
4. the method for claim 1, is characterized in that, described insulating barrier adopts silicon nitride SiN
xor silicon oxynitride SiON.
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| CN103474396B (en) * | 2013-09-24 | 2015-09-02 | 深圳市华星光电技术有限公司 | The manufacture method of TFT-LCD array substrate |
| CN103715137B (en) | 2013-12-26 | 2018-02-06 | 京东方科技集团股份有限公司 | Array base palte and its manufacture method, display device |
| CN105097943A (en) | 2015-06-24 | 2015-11-25 | 京东方科技集团股份有限公司 | Thin film transistor and manufacturing method thereof, array substrate and display device |
| CN108962827B (en) * | 2018-07-13 | 2020-12-08 | 京东方科技集团股份有限公司 | Manufacturing method of double-layer metal layer in array substrate and array substrate |
| CN113658912B (en) * | 2021-07-09 | 2024-04-16 | 深圳莱宝高科技股份有限公司 | Array substrate manufacturing method, array substrate, electronic paper device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20040223091A1 (en) * | 2003-05-09 | 2004-11-11 | Au Optronics Corp. | Bonding pad and method for manufacturing the same |
| CN101105615A (en) * | 2006-06-29 | 2008-01-16 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and method for fabricating the same |
| TW201131269A (en) * | 2010-03-10 | 2011-09-16 | Prime View Int Co Ltd | A pixel structure and fabrication method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040223091A1 (en) * | 2003-05-09 | 2004-11-11 | Au Optronics Corp. | Bonding pad and method for manufacturing the same |
| CN101105615A (en) * | 2006-06-29 | 2008-01-16 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and method for fabricating the same |
| TW201131269A (en) * | 2010-03-10 | 2011-09-16 | Prime View Int Co Ltd | A pixel structure and fabrication method thereof |
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