CN203480181U - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
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- CN203480181U CN203480181U CN201320613176.5U CN201320613176U CN203480181U CN 203480181 U CN203480181 U CN 203480181U CN 201320613176 U CN201320613176 U CN 201320613176U CN 203480181 U CN203480181 U CN 203480181U
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Abstract
The utility model provides an array substrate and a display device. The array substrate comprises a base substrate, a grid electrode formed on the base substrate, a grid electrode insulating layer formed on the grid electrode, a pixel electrode formed on the grid electrode insulating layer, a first transparent electric conduction part, a second transparent electric conduction part, source electrodes, drain electrodes, a doped semiconductor layer, an active layer and a passivation layer. A grid electrode insulating layer through hole is formed in the grid electrode insulting layer, the source electrodes and the drain electrodes are arranged on the first transparent electric conduction part and the second transparent electric conduction part respectively, the doped semiconductor layer is formed on the source electrode and the drain electrode, the active layer is formed on the doped semiconductor layer and is only arranged at the position corresponding to the drain electrode and the source electrode which form a TFT channel region, and then a TFT channel is formed. The passivation layer is arranged above the active layer, a passivation layer through hole is formed in the passivation layer, and electric connecting parts are arranged in the passivation layer through hole and the grid electrode insulating layer through hole. According to the manufacturing method of the array substrate, the manufacturing processes can be reduced, and the quality of the array substrate is improved.
Description
Technical field
The utility model relates to display technique field, relates in particular to a kind of array base palte and display device.
Background technology
Thin-film transistor LCD device (Thin Film Transistor Liquid Crystal Display is called for short TFT-LCD) is a kind of main panel display apparatus.Existing array base palte (Array Substrate) comprising: grid line, data line, thin film transistor (TFT) (Thin Film Transistor, referred to as TFT) and pixel electrode.Grid line is horizontally installed on underlay substrate, and data line is longitudinally arranged on underlay substrate, and the infall of grid line and data line is provided with TFT.TFT is active switch element.
As shown in Figure 1, existing array base palte comprises: grid 10, gate insulation layer 20, active layer 30, source electrode 50, drain electrode 60, passivation layer 70.Said structure is all arranged on underlay substrate 80.Wherein grid 10 is one-body molded with grid line, and source electrode 50, drain electrode 60 and data line are one-body molded, and drain electrode 60 is electrically connected to pixel electrode 90.While inputting Continuity signal in grid line, active layer 30 conductions, the data-signal of data line can arrive drain electrode 60 through TFT raceway groove 31 from source electrode 50, finally inputs to pixel electrode 90.Pixel electrode 90 obtains being formed for public electrode 91 electric field that drives liquid crystal to rotate after signal.
At present in order to adapt to higher integrated level, high PPI product has become the main flow of demonstration, but with regard to this product, the product requirement of preparing high PPI is higher, needing 7 composition techniques to form structure graph completes, because like this could integrated GOA technology (GOA technology is the capable Driving technique of Gate Driver on Array(array base palte), be that direct Will gate driver circuit (Gate driver ICs) is produced on array base palte, Come replaces a kind of technology of wafer of driving of being made by external silicium wafer.The application of this technology can directly be made in the panel few production process of ， Minus around, and reduces cost of products, improves the high integration of TFT-LCD panel, makes more slimming of panel) and via hole prepare enough little.The technique such as comprise respectively again each time mask exposure, development, etching in composition technique and peel off, wherein etching technics comprises dry etching and wet etching, so the number of times of composition technique can be weighed the complicated and simple degree of manufacturing TFT-LCD array base palte, the number of times that reduces composition technique just means the reduction of manufacturing cost.
The processing procedure of the TFT-LCD array base palte of traditional ADS pattern as shown in Figure 3.ADSDS(is called for short ADS, ADvanced Super Dimension Switch, a senior super dimension switch technology).The autonomous innovation of ADSShi BOE take the core technology general designation that wide visual angle technology is representative.It is the wide visual angle of plane electric fields core technology-senior super dimension switch technology, its core technology characteristic description is: the electric field producing by electric field that in same plane, gap electrode edge produces and gap electrode layer and plate electrode interlayer forms multi-dimensional electric field, make in liquid crystal cell between gap electrode, directly over electrode, all aligned liquid-crystal molecules can both produce rotation, thereby improved liquid crystal work efficiency and increased light transmission efficiency.Senior super dimension field switch technology can improve the picture quality of TFT-LCD product, has high resolving power, high permeability, low-power consumption, wide visual angle, high aperture, low aberration, without advantages such as water of compaction ripples (push Mura).First, by composition technique for the first time at the upper grid line that forms of glass substrate (glass); Then, deposition gate insulation layer 20 and active layer 30, by the active layer of composition technique formation for the second time 30 figures; Then, pixel deposition electrode, by the pixel electrode of composition technique formation for the third time; Then, on gate insulation layer 20, by the 4th composition technique, form via hole (GI via hole); Then, depositing metal layers, forms signal wire and active layer 30 figures by the 5th composition technique, and wherein signal wire is realized conducting by GI via hole and grid line, and at channel region, forms the figure of signal wire and active layer 30; Then, deposit passivation layer (PVX), and form passivation layer via hole by the 6th composition technique; Finally, depositing conducting layer, and form public electrode by the 7th composition technique, thus, totally seven mask plate technique completes the structure graph of array base palte.
As can be seen here, at present for TFT-LCD array base palte processing procedure, when the high PPI of preparation and comprise GOA product time, for the factor such as intensive that connects up often adopts 7mask preparation in preparation process, therefore usually because the more output of mask can not get promoting; And the formation of raceway groove utilizes etching to form in existing TFT-LCD array base palte, often because the reasons such as technology and equipment in etching process cause raceway groove bad, and this kind bad often occurred frequently in producing line, affects product quality.
Utility model content
The purpose of this utility model is to provide a kind of array base palte and display device, can reduce processing procedure, improves product quality.
Technical scheme provided by the utility model is as follows:
An array base palte, comprising:
Underlay substrate;
Be formed at the grid on described underlay substrate;
Be formed on described grid, and cover the gate insulator of whole described underlay substrate, described gate insulator is provided with gate insulator via hole, and the top of described gate insulator via hole in grid described at least a portion;
Be formed at the pixel electrode on described gate insulator;
With the first electrically conducting transparent portion of described pixel electrode with layer setting;
With the second electrically conducting transparent portion that described pixel electrode arranges with layer, described the second electrically conducting transparent portion and described the first electrically conducting transparent portion lay respectively at the position of the both sides of described grid;
Be arranged at the source electrode on described the first electrically conducting transparent portion;
Be arranged on described the second electrically conducting transparent portion, and the drain electrode arranging with layer with described source electrode, described source electrode and described drain electrode lay respectively at the position of the both sides of described grid, wherein between a part of described source electrode and described drain electrode, form TFT channel region, between source electrode and described drain electrode, described gate insulator via hole is set described in another part;
Be formed at respectively the doping semiconductor layer on described source electrode and described drain electrode;
Be formed at the semiconductor layer on described doping semiconductor layer, wherein said semiconductor layer is only arranged on the described drain electrode and the corresponding position of electrode, described source that forms described TFT channel region, forms TFT raceway groove;
Be formed at the passivation layer on described semiconductor layer, wherein said passivation layer is provided with passivation layer via hole in the position corresponding with described gate insulator via hole, and described passivation layer via hole and described gate insulator via hole connect, and in described passivation layer via hole and described gate insulator via hole, be provided with for by least one electrical junction being electrically connected of described grid and described source electrode, described drain electrode.
Further, described the second electrically conducting transparent portion and described pixel electrode are connected as a single entity.
Further, described array base palte also comprises: be formed at the public electrode on described passivation layer.
Further, described public electrode adopts identical material and one-body molded by a same composition technique with described electrical junction.
Further, described array base palte comprises viewing area and the neighboring area that is located in described viewing area periphery;
Wherein, in described grid, a part is positioned at described viewing area, and another part is positioned at described neighboring area, and described gate insulator via hole is arranged on the top of the described grid that is positioned at neighboring area.
Further, the shape of described source electrode and described the first electrically conducting transparent portion matches;
The shape of described drain electrode and described the second electrically conducting transparent portion matches.
Further, described array base palte also comprises grid line and data line, wherein,
Described grid line and described grid arrange with layer, and described grid line is identical with the material of described grid, and by one-body molded with a composition technique;
Described data line and described source electrode and described drain electrode arrange with layer, and described data line is identical with the material of described source electrode and described drain electrode, and by one-body molded with a composition technique.
A display device, comprises array base palte as above.
Array base palte provided by the utility model and display device have the following advantages:
Compare with traditional TFT-LCD array base palte, array base palte of the present utility model can reduce the manufacture of composition technique number of times and form, and reduces processing procedure, reduces manufacturing cost, improves production capacity; And, array base palte of the present utility model, its TFT raceway groove is to form in depositing semiconductor layers process, adopts etching mode to form TFT raceway groove compare with traditional TFT-LCD array base palte, fundamentally avoided the bad generation of TFT raceway groove, thus improving product quality greatly.
Accompanying drawing explanation
Fig. 1 is the cross-section cutaway view of traditional TFT-LCD array base palte;
Fig. 2 is the 7mask processing procedure schematic diagram of traditional TFT-LCD array base palte;
Figure 3 shows that on underlay substrate by the sectional view after the grid of composition technique formation for the first time;
Figure 4 shows that the sectional view depositing successively after gate insulating film, the first transparent conductive film, source leakage metallic film and doping a-si film on the underlay substrate that forms the first figure;
Figure 5 shows that in the structure of Fig. 4 and applied after photoresist, and photoresist has been carried out to the sectional view after exposure and development treatment;
Figure 6 shows that the structure of Fig. 5 has been carried out to the sectional view after the second etching technics;
Figure 7 shows that the photoresist in Fig. 6 has been carried out to cineration technics sectional view afterwards;
Fig. 8 is for to have carried out the sectional view after the 3rd etching technics to the structure of Fig. 7;
Fig. 9 is the sectional view having peeled off in the structure of Fig. 8 after residue photoresist;
Figure 10 shows that on the underlay substrate that forms second graph and deposit successively the sectional view after a-si film;
Figure 11 shows that in the structure of Figure 10 and applied after photoresist, and photoresist has been carried out to the sectional view after exposure and development treatment;
Figure 12 has been for to have carried out the 4th etching technics to the structure of Figure 11, and peeled off the sectional view after residue photoresist;
Figure 13 shows that the structure in Figure 12 is carried out to the cut-open view after composition technique the 4th time;
Figure 14 shows that the structure in Figure 13 is carried out to the cut-open view after composition technique the 5th time;
Figure 15 shows that the structure cut-open view of array base palte provided by the utility model.
Embodiment
Below in conjunction with accompanying drawing, principle of the present utility model and feature are described, example, only for explaining the utility model, is not intended to limit scope of the present utility model.
It should be noted that: in for example " X-shaped is formed on Y " described in the utility model " on " comprised X and contact with Y, and X is positioned at the meaning of the top of Y, in the utility model, as shown in drawings, underlay substrate is defined as and is arranged at below; The alleged composition technique of the utility model comprises the techniques such as photoresist coating, mask, exposure, development, etching, photoresist lift off, and photoresist be take positive photoresist as example.
The preferred embodiment of TFT-LCD array base palte provided by the utility model is below described.
In the present embodiment, substrate mainly comprises grid line, data line, TFT and pixel electrode, and orthogonal grid line and data line have defined pixel cell, and TFT and pixel electrode are formed in pixel cell, grid line is for providing start signal to TFT, and data line is for providing data-signal to pixel electrode.TFT is active switch element.
Be the cross-section cutaway view of array base palte of the present utility model as shown in figure 15.Array base palte provided by the utility model is provided with viewing area and is located in the neighboring area of described viewing area periphery; As shown in figure 15, described array base palte comprises:
Be formed at the grid 200 on described underlay substrate 100, wherein grid 200 parts are positioned at the viewing area of array base palte, and another part is positioned at the neighboring area of array base palte;
Be formed on described grid 200, and cover the gate insulator 300 of whole described underlay substrate 100, described gate insulator 300 is provided with gate insulator via hole 301, and the top of described gate insulator via hole 301 in grid described at least a portion 200, preferably, described gate insulator via hole 301 is arranged on the top of the grid 200 that is positioned at described neighboring area;
Be formed at the pixel electrode 400 on described gate insulator 300;
With the first electrically conducting transparent portion 401 of described pixel electrode 400 with layer setting;
With the second electrically conducting transparent portion 402 that described pixel electrode 400 arranges with layer, described the second electrically conducting transparent portion 402 and described the first electrically conducting transparent portion 401 lay respectively at the position of the both sides of described grid 200;
Be arranged at the source electrode 501 on described the first electrically conducting transparent portion 401;
Be arranged on described the second electrically conducting transparent portion 402, and the drain electrode 502 arranging with layer with described source electrode 501, described source electrode 501 and described drain electrode 502 lay respectively at the position of the both sides of described grid 200, preferably, wherein between a part of described source electrode 501 and described drain electrode 502, the viewing area in array base palte forms TFT channel region, source electrode 501 and the neighboring area of described drain electrode 502 in array base palte described in another part, arrange the both sides of described gate insulator via hole 301;
Be formed at respectively the doping semiconductor layer 600 on described source electrode 501 and described drain electrode 502;
Be formed at the semiconductor layer 700 on described doping semiconductor layer 600, the described drain electrode 502 of the described TFT channel region of formation that wherein said semiconductor layer 700 is only arranged on viewing area and the corresponding position of described source electrode 501, thus TFT raceway groove 220 formed;
Be formed at the passivation layer 800 on described semiconductor layer 700, wherein, described passivation layer 800 position corresponding with described gate insulator via hole 301 in neighboring area is provided with passivation layer via hole 801, and described passivation layer via hole 801 connects with described gate insulator via hole 301, and in described passivation layer via hole 801 and described gate insulator via hole 301, be provided with at least one electrical junction being electrically connected 901 with described source electrode 501, described drain electrode 502 by described grid 200.
In the present embodiment, preferred, as shown in figure 15, described the second electrically conducting transparent portion 402 is connected as a single entity with described pixel electrode 400.Adopt such scheme, the first electrically conducting transparent portion 401, the second electrically conducting transparent portion 402 and pixel electrode 400 can be by one-body molded through etching by same transparency conducting layer with a composition technique.
In the present embodiment, preferred, as shown in figure 15, described array base palte also comprises: be formed at the public electrode 902 on described passivation layer 800.The public electrode 902 of ADS panel is also arranged on array base palte, certainly can understand, and for other types panel, public electrode can not be arranged on array base palte yet.
In the present embodiment, preferred, as shown in figure 15, described public electrode 902 adopts identical material and one-body molded by a same composition technique with described electrical junction 901.Certainly can understand, in practical application, described public electrode 902 can be also to adopt unlike material with described electrical junction 901, and forms by isomorphic graphs technique not, but can increase processing procedure like this.
In the present embodiment, as shown in figure 15, described source electrode 501 matches with the shape of described the first electrically conducting transparent portion 401; Described drain electrode 502 matches with the shape of described the second electrically conducting transparent portion 402.Adopt such scheme, described source electrode 501 can be by one-body molded with a composition technique (gray level mask technique) with described the first electrically conducting transparent portion 401 that is positioned at its below; Described drain electrode 502 can be by one-body molded with a composition technique (gray level mask technique) with described the second electrically conducting transparent portion 402 that is positioned at its below.
In addition, in the present embodiment, preferred, described array base palte also comprises grid line (not shown) and data line (not shown), and wherein, described grid line and described grid 200 arrange with layer, and described grid line is identical with the material of described grid 200, and by one-body molded with a composition technique; Described data line and described source electrode 501 and described drain electrode 502 arrange with layer, and described data line is identical with the material of described source electrode 501 and described drain electrode 502, and by one-body molded with a composition technique.
In addition, it should be noted that, in this preferred embodiment, in described grid 200, a part is positioned at described viewing area, and another part is positioned at described neighboring area, and described gate insulator via hole 301 is arranged on the top of the described grid 200 that is positioned at neighboring area.Should be understood that, in actual applications, described gate insulator via hole 301 also can be arranged at part of grid pole 200 tops of viewing area.
Array base palte provided by the utility model, its method for making is compared with traditional TFT-LCD manufacturing method of array base plate, has reduced composition technique number of times, and the utility model composition technique number of times is 5 times, reduces processing procedure 2 times, reduces manufacturing cost, improves production capacity; And in the utility model, TFT raceway groove is to form in depositing semiconductor layers process, form TFT raceway groove with traditional employing etching mode and compare, fundamentally avoided the bad generation of TFT raceway groove, thus improving product quality greatly.
The manufacture method of above-mentioned TFT-LCD array base palte provided by the utility model is below described.The method comprises:
Fig. 3 to Figure 14 has illustrated the manufacturing process of the array base palte that the utility model preferred embodiment provides successively.
Be illustrated in figure 3 on underlay substrate by the sectional view after the grid 200 of composition technique formation for the first time.Particularly, on underlay substrate, the process by the grid 200 of composition technique formation for the first time comprises:
One underlay substrate 100 is provided;
First, adopt magnetron sputtering, thermal evaporation or other film build method, on described underlay substrate 100, deposit one deck grid metallic film, wherein grid metallic film can be the single thin film that the metals such as molybdenum, aluminium, aluminium neodymium alloy, tungsten, chromium, copper form, and can be also the multilayer film that above metallic multilayer deposition forms;
Secondly, on described grid metallic film, apply photoresist;
Then, by common mask plate, photoresist is exposed and development treatment, make at least in the position of grid 200 correspondences, to retain photoresist;
Then, by the first etching technics, etch away the grid metallic film exposing, to form the first figure that comprises grid 200;
Finally, peel off residue photoresist, obtain the structure of the first figure as shown in Figure 3.
So far, complete composition technique for the first time, on underlay substrate 100, form grid 200.
It should be noted that, in composition technique for the first time, also can when exposure, development treatment, in the position corresponding with grid line, retain photoresist, thereby can etch away after the grid metallic film exposing by the first etching technics, form grid line.
Be illustrated in figure 4 the sectional view depositing successively after gate insulating film, the first transparent conductive film, source leakage metallic film and doping a-si film on the underlay substrate 100 that forms the first figure.Be illustrated in figure 5 in the structure of Fig. 4 and applied after photoresist, photoresist has been carried out to the sectional view after exposure and development treatment.Be illustrated in figure 6 the structure of Fig. 5 has been carried out to the sectional view after the second etching technics.Be illustrated in figure 7 the photoresist in Fig. 6 has been carried out to cineration technics sectional view afterwards.Fig. 8 is for to have carried out the sectional view after the 3rd etching technics to the structure of Fig. 7.Fig. 9 is the sectional view having peeled off in the structure of Fig. 8 after residue photoresist.
Incorporated by reference to Fig. 4 to 9 and Figure 15, particularly, on underlay substrate 100, by the pixel electrode 400 of composition technique formation for the second time, source electrode 501, drain electrode 502 and doping semiconductor layer 600, comprising:
First, as shown in Figure 4, adopt plasma reinforced chemical vapour deposition (PECVD), magnetron sputtering, thermal evaporation or other film build method, on underlay substrate 100 (as glass substrate or quartz base plate), deposit successively gate insulating film 101, the first transparent conductive film 102, source leakage metallic film 103 and doping a-si film 104, wherein the single thin film that metallic film 103 can be the metal formation such as molybdenum, aluminium, aluminium neodymium alloy, tungsten, chromium, copper is leaked in source, can be also the multilayer film that above metallic multilayer deposition forms.The first transparent conductive film 102 can be ITO, IZO etc.;
Secondly, as shown in Fig. 5 and Figure 15, on doping a-si film 104, apply photoresist 1000, by two tune mask plates (partly adjusting mask plate or tone mask plate), described photoresist 1000 is exposed and development treatment, make described photoresist 1000 form the complete reserved area of photoresist, photoresist half reserved area and photoresist are removed district completely, the complete reserved area of wherein said photoresist comprises source electrode 501, the corresponding position of drain electrode 502, described photoresist half reserve area correspondence comprises the corresponding position of pixel electrode 400, described photoresist is removed corresponding position except the complete reserved area of described photoresist and described photoresist half reserved area, district completely, there is not photoresist 1000 in TFT raceway groove 220 and the corresponding position of gate insulator via hole 301 wherein, in described photoresist, remove district completely, wherein gate insulator via hole is preferably arranged at the neighboring area of array base palte, TFT raceway groove is arranged at the viewing area of array base palte,
Then, as Fig. 6, shown in Fig. 5 and Figure 15, by the second etching technics, etch away the first transparent conductive film 102 that described photoresist is removed district completely completely, metallic film 103 and doping a-si film 104 are leaked in source, thereby form described the first electrically conducting transparent portion 401, the second electrically conducting transparent portion 402, source electrode 501, drain electrode 502 and doping semiconductor layer 600, and the first transparent conductive film 102 above forming TFT channel region 220 ' between source electrode 501 and drain electrode 502 and removing gate insulator 300 in gate insulator via hole 301 positions, metallic film 103 and doping a-si film 104 are leaked in source, wherein, can adopt the etching mode of dry quarter and wet etching combination, particularly, can to doping a-si film (being N+a-Si) 104, carry out etching by gases such as SF6, HCl, Cl2, He, the etching agent that potpourri by phosphoric acid and nitric acid makes leaks metallic film 103 to source and carries out etching, by etching agents such as sulfuric acid or superoxide, the first transparent conductive film 102 (ITO or IZO) is carried out to etching,
Then, as shown in Fig. 7, Fig. 6 and Figure 15, by cineration technics, remove the photoresist 1000 of described photoresist half reserved area, expose the doping a-si film 104 of described photoresist half reserved area, expose the doping a-si film 104 of pixel electrode 400 corresponding positions;
Afterwards, as shown in Fig. 8, Fig. 7 and Figure 15, metallic film is leaked in the doping a-si film and the source that by the 3rd etching technics, etch away described photoresist half reserved area completely, and metallic film and doping a-si film are leaked in the source that etches away pixel electrode 400 tops, expose described pixel electrode 400;
Finally, peel off residue photoresist 1000, obtain the structure after second graph that is formed with as shown in Figure 9.
So far, complete composition technique for the second time.
It should be noted that, in composition technique for the second time, also can expose, during development treatment, in the position corresponding with data line, retain photoresist 1000, thereby can etch away the first transparent conductive film 102, source leakage metallic film 103 and doping a-si film 104 by the second etching technics, form the figure of data line.
As shown in figure 10 for depositing successively the sectional view after a-si film on the underlay substrate 100 forming second graph.In structure for Figure 10, applied after photoresist 1000 as shown in figure 11 the sectional view that photoresist 1000 has been carried out after exposure and development treatment.Figure 12 is for having carried out the 4th etching technics to the structure of Figure 11 and having peeled off the sectional view after residue photoresist 1000.
As shown in Figure 10 to 12, and in conjunction with Figure 15, particularly, on underlay substrate 100, by the TFT of composition technique formation for the third time raceway groove 220, semiconductor layer 700 and gate insulator via hole 301, comprising:
First, as shown in Figure 10 and Figure 15, conventionally can adopt PECVD or other film build method, deposition one deck a-si film 201; After this deposition, in data line, source electrode 501 and the corresponding position of drain electrode 502, a-si film 201 is deposited on doping semiconductor layer 600, in the corresponding position of pixel electrode 400, a-si film 201 is deposited on pixel electrode 400, in other region, (comprise TFT raceway groove 220 and the corresponding position of gate insulator via hole 301), a-si film 201 is deposited on gate insulator 300;
Then, as shown in Figure 11, Figure 10 and Figure 15, first on a-si film 201, apply photoresist 1000, then by common mask plate, photoresist 1000 is exposed and development treatment, photoresist 1000 is covered on the corresponding position of semiconductor layer 700, and other region is without residue photoresist 1000.Preferably, as shown in Figure 11 and Figure 15, photoresist 1000 only covers the TFT raceway groove 220 of viewing area and the source electrode 501 of both sides and the corresponding position of drain electrode 502 of array base palte, and does not have photoresist 1000 at the gate insulator via hole of neighboring area of array base palte and the source electrode 501 of both sides thereof and the corresponding position of drain electrode 502;
Then, as shown in Figure 12, Figure 11 and Figure 15, by the 4th etching technics, utilize etching agent to etch away and there is no the a-si film 201 of photoresist 1000 coverings, formed the figure of semiconductor layer 700, and by gate insulator 300 described in described the 4th etching technics etching, formed gate insulator via hole 301 in the position of described gate insulator via hole 301 correspondences, wherein, semiconductor layer 700 is formed on the TFT raceway groove of viewing area and the source electrode 501 of both sides and drain electrode 502, the semiconductor layer 700 being positioned on TFT channel region has formed TFT raceway groove 220, like this, utilize a-si film 201 depositions and do not need etching directly to form TFT raceway groove, avoid because etching forms the problem that TFT raceway groove produces, and, after semiconductor layer 700 etchings complete, can utilize etch rate to select the relation (that is: utilizing grid 200 protective seam etch rates far above the process conditions of data wire metal etch rate) of ratio to carry out gate insulator 300 etchings, and not can or the less mode of data wire metal etching is carried out, thereby form gate insulator via hole 301,
Finally, peel off remaining photoresist 1000, obtained the structure after the 3rd figure that is formed with as shown in figure 12.
As shown in figure 13 for the structure in Figure 12 is carried out to the cut-open view after composition technique the 4th time.Particularly, the process by the 4th composition technique formation passivation layer 800 comprises:
First, at whole underlay substrate 100, adopt PECVD or other film build method deposition one deck passivation layer film, form passivation layer 800.Passivation layer film can adopt the single thin film of SiNx, SiOx or SiOxNy, or the multilayer film of above-mentioned material plane SH wave formation;
Secondly, on described passivation layer film, apply photoresist;
Then, by mask plate, photoresist is exposed and development treatment, at least in the corresponding position of passivation layer via hole 801, remove photoresist, wherein said passivation layer via hole 801 is corresponding with the position of described gate insulator via hole 301;
Then, by the 5th etching technics, etch away the passivation layer film exposing, form the passivation layer via hole 801 communicating with described gate insulator via hole 301;
Finally, peel off residue photoresist, obtain the structure that is formed with the 4th figure that comprises passivation layer 800 as shown in figure 13.
As shown in figure 14 for the structure in Figure 13 is carried out to the cut-open view after composition technique the 5th time.Particularly, the process by the 5th composition technique formation electrical junction 901 comprises:
First, on the underlay substrate 100 that forms described the 4th figure, deposit the second transparent conductive film, the second transparent conductive film can be ITO, IZO etc.;
Secondly, on described the second transparent conductive film, apply photoresist;
Then, by common mask plate, photoresist is exposed and development treatment, at least in the position of described passivation layer via hole 801 correspondences, retain photoresist;
Then, by the 6th etching technics, etch away the second transparent conductive film exposing, thereby in described passivation layer via hole 801 formation electrical junctions, place 901;
Finally, peel off residue photoresist, obtain TFT-LCD array base palte provided by the utility model.
It should be noted that, array base palte for ADS pattern, when forming described electrical junction 901, can pass through when exposure, development treatment, in the corresponding position of public electrode 902, retain photoresist, through described the 6th etching technics colleague, on passivation layer 800, form public electrode 902 again, obtain structure as shown in figure 15.
So far, by 5 composition processing procedures, obtain array base palte of the present utility model.
In addition, the utility model also provides a kind of display device, and it comprises array base palte described in the utility model.
The above is preferred implementation of the present utility model; should be understood that; for those skilled in the art; do not departing under the prerequisite of principle described in the utility model; can also make some improvements and modifications, these improvements and modifications also should be considered as protection domain of the present utility model.
Claims (9)
1. an array base palte, is characterized in that, described array base palte comprises:
Underlay substrate;
Be formed at the grid on described underlay substrate;
Be formed on described grid, and cover the gate insulator of whole described underlay substrate, described gate insulator is provided with gate insulator via hole, and the top of described gate insulator via hole in grid described at least a portion;
Be formed at the pixel electrode on described gate insulator;
With the first electrically conducting transparent portion of described pixel electrode with layer setting;
With the second electrically conducting transparent portion that described pixel electrode arranges with layer, described the second electrically conducting transparent portion and described the first electrically conducting transparent portion lay respectively at the position of the both sides of described grid;
Be arranged at the source electrode on described the first electrically conducting transparent portion;
Be arranged on described the second electrically conducting transparent portion, and the drain electrode arranging with layer with described source electrode, described source electrode and described drain electrode lay respectively at the position of the both sides of described grid, wherein between a part of described source electrode and described drain electrode, form TFT channel region, between source electrode and described drain electrode, described gate insulator via hole is set described in another part;
Be formed at respectively the doping semiconductor layer on described source electrode and described drain electrode;
Be formed at the semiconductor layer on described doping semiconductor layer, wherein said semiconductor layer is only arranged on the described drain electrode and the corresponding position of electrode, described source that forms described TFT channel region, forms TFT raceway groove;
Be formed at the passivation layer on described semiconductor layer, wherein said passivation layer is provided with passivation layer via hole in the position corresponding with described gate insulator via hole, and described passivation layer via hole and described gate insulator via hole connect, and in described passivation layer via hole and described gate insulator via hole, be provided with for by least one electrical junction being electrically connected of described grid and described source electrode, described drain electrode.
2. array base palte according to claim 1, is characterized in that,
Described the second electrically conducting transparent portion and described pixel electrode are connected as a single entity.
3. array base palte according to claim 1, is characterized in that,
Described array base palte also comprises: be formed at the public electrode on described passivation layer.
4. array base palte according to claim 3, is characterized in that,
Described public electrode adopts identical material and one-body molded by a same composition technique with described electrical junction.
5. array base palte according to claim 1, is characterized in that,
Described array base palte comprises viewing area and is located in the neighboring area of described viewing area periphery;
Wherein, in described grid, a part is positioned at described viewing area, and another part is positioned at described neighboring area, and described gate insulator via hole is arranged on the top of the described grid that is positioned at neighboring area.
6. array base palte according to claim 1, is characterized in that,
The shape of described source electrode and described the first electrically conducting transparent portion matches;
The shape of described drain electrode and described the second electrically conducting transparent portion matches.
7. array base palte according to claim 1, is characterized in that,
Described array base palte also comprises grid line, wherein,
Described grid line and described grid arrange with layer, and described grid line is identical with the material of described grid, and by one-body molded with a composition technique.
8. array base palte according to claim 1, is characterized in that,
Described array base palte also comprises data line, wherein,
Described data line and described source electrode and described drain electrode arrange with layer, and described data line is identical with the material of described source electrode and described drain electrode, and by one-body molded with a composition technique.
9. a display device, is characterized in that, comprises the array base palte as described in claim 1 to 8.
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| CN201320613176.5U CN203480181U (en) | 2013-09-30 | 2013-09-30 | Array substrate and display device |
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| CN201320613176.5U CN203480181U (en) | 2013-09-30 | 2013-09-30 | Array substrate and display device |
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| CN203480181U true CN203480181U (en) | 2014-03-12 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103489877A (en) * | 2013-09-30 | 2014-01-01 | 北京京东方光电科技有限公司 | Array substrate, manufacturing method thereof and display device |
| CN106990632A (en) * | 2017-04-14 | 2017-07-28 | 京东方科技集团股份有限公司 | Array base palte and display device |
| CN113394236A (en) * | 2021-05-28 | 2021-09-14 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
-
2013
- 2013-09-30 CN CN201320613176.5U patent/CN203480181U/en not_active Expired - Lifetime
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103489877A (en) * | 2013-09-30 | 2014-01-01 | 北京京东方光电科技有限公司 | Array substrate, manufacturing method thereof and display device |
| WO2015043282A1 (en) * | 2013-09-30 | 2015-04-02 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method therefor, and display apparatus |
| CN103489877B (en) * | 2013-09-30 | 2015-12-09 | 北京京东方光电科技有限公司 | Array base palte and manufacture method thereof and display unit |
| US9716110B2 (en) | 2013-09-30 | 2017-07-25 | Boe Technology Group Co., Ltd. | Array substrate, method for manufacturing the same, and display device |
| CN106990632A (en) * | 2017-04-14 | 2017-07-28 | 京东方科技集团股份有限公司 | Array base palte and display device |
| WO2018188656A1 (en) * | 2017-04-14 | 2018-10-18 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN113394236A (en) * | 2021-05-28 | 2021-09-14 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| CN113394236B (en) * | 2021-05-28 | 2024-04-09 | 武汉天马微电子有限公司 | Display panel and display device |
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