CN108847408A - A kind of manufacturing method and tft array substrate of tft array substrate - Google Patents
A kind of manufacturing method and tft array substrate of tft array substrate Download PDFInfo
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- CN108847408A CN108847408A CN201810561085.9A CN201810561085A CN108847408A CN 108847408 A CN108847408 A CN 108847408A CN 201810561085 A CN201810561085 A CN 201810561085A CN 108847408 A CN108847408 A CN 108847408A
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- 239000000758 substrate Substances 0.000 title claims abstract description 88
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 239000010410 layer Substances 0.000 claims abstract description 83
- 239000000463 material Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000011241 protective layer Substances 0.000 claims abstract description 17
- 239000004020 conductor Substances 0.000 claims abstract description 16
- 238000002161 passivation Methods 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 13
- 239000007789 gas Substances 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000004380 ashing Methods 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 229910052733 gallium Inorganic materials 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 5
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 4
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 4
- UMVBXBACMIOFDO-UHFFFAOYSA-N [N].[Si] Chemical compound [N].[Si] UMVBXBACMIOFDO-UHFFFAOYSA-N 0.000 claims description 4
- 238000003475 lamination Methods 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 229910052725 zinc Inorganic materials 0.000 claims description 4
- 239000011701 zinc Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical group 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 3
- 239000007772 electrode material Substances 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 abstract description 8
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 238000002207 thermal evaporation Methods 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- OLUKZDDFBTYGCS-UHFFFAOYSA-N methane trifluoroborane Chemical compound C.B(F)(F)F OLUKZDDFBTYGCS-UHFFFAOYSA-N 0.000 description 2
- 208000032750 Device leakage Diseases 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
Abstract
The present invention provides a kind of manufacturing method of tft array substrate, the method includes：Substrate is provided, is sequentially prepared grid, gate insulating layer and active layer in the substrate surface；The active layer includes channel, source doping region and drain doping region；Protective layer is prepared in the channel surface, and by the source doping region and the drain doping region conductor；Source electrode and drain electrode is formed in the substrate surface；The protective layer is removed, finally prepares passivation layer in the substrate surface.The present invention also provides tft array substrates made of a kind of production method using above-mentioned tft array substrate.Beneficial effect：The manufacturing method and tft array substrate of a kind of tft array substrate provided by the present invention, by source doping region and drain doping region conductor, avoid additional addition barrier material, it further reduced etching difficulty, the loss etched to active layer channel is further prevented, the production cost of tft array substrate is eventually reduced.
Description
Technical field
The present invention relates to the manufacturing methods and TFT that belong to technical field of flat panel display more particularly to a kind of tft array substrate
Array substrate.
Background technique
At present TFT-LCD (Thin Film Transistors-LCD display panel) due to micro energy lose, low-work voltage, without X-ray
The advantages that radiation, fine definition, small size, is now widely used in the portable electronic products such as mobile phone, palm PC.Its
In, TFT is the luminous switch of control, is to realize the large-sized key of liquid crystal display, is directly related to high performance flat and shows
The developing direction of device.Now, the bottom gate type IGZO in TFT structure (Indium Gallium Zinc Oxide, indium gallium zinc)
Manufacturing process because selection than the problems such as, cause etching technics that can have damage to IGZO, cause IGZO surface defect, influence device
Leakage current and threshold voltage and stability；When source-drain electrode uses steel structure, because of itself and substrate or SiO and SiNx poor adhesive force,
Copper diffuses to the problems such as channel, need to additionally add barrier material, on the one hand increases etching cost, on the other hand has residual wind
Danger.
In conclusion the manufacturing method and tft array substrate of the tft array substrate of the prior art, due to tft array substrate
Source-drain electrode and substrate or gate insulating layer poor adhesive force, cause it to diffuse to active layer channel, and then cause to increase in manufacturing process
Add additional barrier material, cause etching increased costs and has the technical issues of residual risk.
Summary of the invention
The present invention provides the manufacturing method and tft array substrate of a kind of tft array substrate, with to avoid TFT gusts existing
Source-drain electrode remains in active layer channel in column substrate manufacturing process, to solve to need caused by residual of the source-drain electrode material in channel
Increase additional barrier material, further result in etching increased costs and has the technical issues of residual risk.
To solve the above problems, technical solution provided by the invention is as follows：
The present invention provides a kind of manufacturing method of tft array substrate, the method includes：
S10 provides substrate, prepares grid in the substrate surface, prepares gate insulating layer in the substrate surface later；
S20 is prepared with active layer in the gate insulator layer surface, and the active layer includes channel, is located at the channel one
The source doping region at end and positioned at the drain doping region of the channel other end；
S30 prepares protective layer in the channel surface, and by the source doping region and the drain doping region conductor
Change；
S40 prepares metal layer in the substrate surface, and performs etching to the metal layer, forms source electrode and drain electrode；
S50 removes the protective layer, finally prepares passivation layer in the substrate surface.
According to one preferred embodiment of the present invention, the material of the active layer be metal oxide, including indium gallium zinc or
Indium zinc oxide.
According to one preferred embodiment of the present invention, the protective layer is photoresist.
According to one preferred embodiment of the present invention, the S30 further includes：
S301 forms pattern after developing by intermediate tone mask plate to the substrate；
S302 carries out ashing processing to the protective layer.
According to one preferred embodiment of the present invention, gas used in the podzolic process is one in oxygen or fluoroform
Kind or more than one combination, ashing time are between 20 seconds to 100 seconds.
According to one preferred embodiment of the present invention, the gas used during the conductor is rare gas, conductor
Time is between 30 seconds to 60 seconds.
According to one preferred embodiment of the present invention, the source electrode and the material of the drain electrode are copper.
According to one preferred embodiment of the present invention, the material of the gate insulating layer and the passivation layer is silica, nitridation
The lamination layer structure that two or more any combination in silicon, nitrogen silicon compound is constituted.
According to one preferred embodiment of the present invention, the active layer with a thickness of 40 nanometers, the source electrode and the drain electrode
With a thickness of 500 nanometers, the passivation layer with a thickness of 100~400 nanometers.
The present invention also provides a kind of tft array substrates, including：
Substrate；
Grid is located at the substrate surface；
Gate insulating layer is located at the substrate surface；
Active layer is located at the gate insulator layer surface, and the active layer includes channel, positioned at the source of described channel one end
Pole doped region and positioned at the drain doping region of the channel other end；
Source electrode and drain electrode is located at the substrate surface；
Passivation layer is located at the substrate surface；
Beneficial effects of the present invention are：The manufacturing method and tft array base of a kind of tft array substrate provided by the present invention
Source doping region and drain doping region conductor are avoided additional addition barrier material, it is difficult to further reduced etching by plate
Degree further prevents the loss etched to active layer channel, eventually reduces the production cost of tft array substrate.
Detailed description of the invention
It, below will be to embodiment or the prior art in order to illustrate more clearly of embodiment or technical solution in the prior art
Attached drawing needed in description is briefly described, it should be apparent that, the accompanying drawings in the following description is only some of invention
Embodiment for those of ordinary skill in the art without creative efforts, can also be attached according to these
Figure obtains other attached drawings.
Fig. 1 is the manufacturing method flow chart of tft array substrate of the present invention.
Figure 1A -1E is the manufacturing method schematic diagram of tft array substrate described in Fig. 1.
Fig. 2 is tft array substrate structural schematic diagram of the present invention.
Specific embodiment
The explanation of following embodiment is referred to the additional illustration, the particular implementation that can be used to implement to illustrate the present invention
Example.The direction term that the present invention is previously mentioned, such as [on], [under], [preceding], [rear], [left side], [right side], [interior], [outer], [side]
Deng being only the direction with reference to annexed drawings.Therefore, the direction term used be to illustrate and understand the present invention, rather than to
The limitation present invention.The similar unit of structure is with being given the same reference numerals in the figure.
The present invention is directed to existing tft array substrate, due to source-drain electrode in tft array substrate manufacturing process and substrate or grid
Pole insulating layer poor adhesive force, causes it to diffuse to active layer channel, and then causes to increase additional barrier material, causes to etch
Increased costs and have residual risk the technical issues of, the present embodiment is able to solve the defect.
As shown in Figure 1, the present invention provides a kind of tft array substrate preparation method process, the method includes：
S10 provides substrate 101, prepares grid 102 in the substrate surface, prepares grid in the substrate surface later
Insulating layer 103.
Specifically, the S10 further includes：
Gate electrode pattern is formed in 101 surface etch of substrate first with physical vapor deposition method, obtains grid
102；Then, gate insulating layer is deposited using physical vapor deposition method on the surface of the substrate 101 and the grid 102
103, as shown in Figure 1A.
Wherein, the substrate 101 is glass substrate；The material of the grid 102 can be used as Cu/Ti composite material,
Wherein in the grid 102 Cu layers with a thickness of 300nm, in the grid 102 Ti layers with a thickness of 30nm；The gate insulator
The composite layer knot that the material of layer 103 is made of two or more of any combination in silica, silicon nitride, nitrogen silicon compound
Structure, the gate insulating layer with a thickness of 300nm.
S20 prepares active layer on 103 surface of gate insulating layer, and the active layer includes channel 104, positioned at described
The source doping region 105 of channel one end and positioned at the drain doping region 106 of the channel other end.
Specifically, the S20 further includes：
It deposits to form the active layer using physical vapor deposition method on 103 surface of gate insulating layer, it is described to have
Active layer includes channel 104, mixes positioned at the source doping region 105 of described channel one end and positioned at the drain electrode of the channel other end
Miscellaneous area 106, as shown in Figure 1B.
Wherein, the material of the active layer is metal oxide, including indium gallium zinc or indium zinc oxide；The active layer
With a thickness of 40nm；The source doping region 105 and area phase positioned at the drain doping region 106 of the channel other end
Together.
S30 prepares protective layer 107 on 104 surface of channel, and the source doping region 105 and the drain electrode is mixed
Miscellaneous 106 conductor of area.
Specifically, the S30 further includes：
It is armor coated on the substrate 101 first, then pattern is formed after developing by halftone mask；Then to institute
It states protective layer and carries out ashing processing, the protective layer on 101 surface of substrate is thinned, keeps the channel 104 completely described
Photoresist covering；Conductor is carried out to the source doping region 105 and the drain doping region 106 by plasma again, is such as schemed
Shown in 1C.
Wherein, the protective layer is photoresist, and photoresist selects positive resistance material；Gas used in the podzolic process is
One of oxygen or borontrifluoride methane or more than one combination, the ashing time are 20s~100s.Preferably, described
The mixed gas of borontrifluoride methane and oxygen, ashing time 30s can be used in podzolic gas；Preferably, the podzolic gas
Oxygen, ashing time 40s can be used；Gas used in the conductor process is rare gas, when the conductor
Between be 30s~60s, preferably argon gas or helium.
S40 prepares metal layer on 101 surface of substrate, and performs etching to the metal layer, forms 108 He of source electrode
Drain electrode 109；
Specifically, the S40 further includes：
Metal layer is deposited on 101 surface by physical vapor deposition method first；Then the metal layer is carried out
Etching forms source electrode 108 and drain electrode 109 by photoresist；It is protected at this time due to the channel 104 by the protective layer 107,
It etches unaffected during the metal layer, avoids the etching to the channel；The source doping region of conductor
105 and the drain doping region 106 act as barrier material, it is therefore prevented that the metal layer diffuses to the channel 104, such as scheme
Shown in 1D.
Wherein, material used in the metal layer is copper；The metal layer with a thickness of 500 nanometers；In etching process,
Not fluorine-containing copper acid can be used.
S50 removes the protective layer 107, finally prepares passivation layer 110 on 101 surface of substrate.
Specifically, the S50 further includes：
The protective layer 107 is removed using stripper, deposits the passivation layer on 101 surface of substrate, at this point,
Tft array substrate channel is completely formed pattern, as referring to figure 1E.
Wherein, the material of the passivation layer 110 is silica, silicon nitride, two or more of in nitrogen silicon compound
Meaning combines constituted lamination layer structure；The passivation layer 110 with a thickness of 100~400 nanometers；Prepare the mistake of the passivation layer
Thermal evaporation gas used in journey is N2Or O2, thermal evaporation handle the time be 60~150min, thermal evaporation treatment temperature be 200~
400℃.Preferably, the passivation layer 110 is SiO/SiNx lamination, with a thickness of 300/200nm；Preferably, at the thermal evaporation
During reason, thermal evaporation gas is oxygen；Time is 120min, and temperature is 250 DEG C.Preferably, in thermal evaporation treatment process, heat
Boil-off gas is nitrogen；Time is 100min, and temperature is 300 DEG C.
According to above-mentioned production method, a kind of array substrate of TFT element using back channel-etch type can be obtained, such as scheme
Shown in 2, including：
Substrate 201；
Grid 202 is located at 201 surface of substrate；
Gate insulating layer 203 is located at 201 surface of substrate；
Active layer, the active layer include channel 204, positioned at described channel one end source doping region 205 and be located at
The drain doping region 206 of the channel other end is located at 203 surface of gate insulating layer；
Source electrode 207 and drain electrode 208, are located at 201 surface of substrate；
Passivation layer 108 is located at the substrate surface；
Wherein, the source doping region 205 and drain doping region 206 carry out conductor processing.
Beneficial effects of the present invention are：The manufacturing method and tft array base of a kind of tft array substrate provided by the present invention
Source doping region and drain doping region conductor are avoided additional addition barrier material, it is difficult to further reduced etching by plate
Degree further prevents the loss etched to active layer channel, eventually reduces the production cost of tft array substrate.
In conclusion although the present invention has been disclosed above in the preferred embodiment, but above preferred embodiment is not to limit
The system present invention, those skilled in the art can make various changes and profit without departing from the spirit and scope of the present invention
Decorations, therefore protection scope of the present invention subjects to the scope of the claims.
Claims (10)
1. a kind of manufacturing method of tft array substrate, which is characterized in that the method includes：
S10 provides substrate, prepares grid in the substrate surface, prepares gate insulating layer in the substrate surface later；
S20 is prepared with active layer in the gate insulator layer surface, and the active layer includes channel, positioned at described channel one end
Source doping region and positioned at the drain doping region of the channel other end；
S30 prepares protective layer in the channel surface, and by the source doping region and the drain doping region conductor；
S40 prepares metal layer in the substrate surface, and performs etching to the metal layer, forms source electrode and drain electrode；
S50 removes the protective layer, finally prepares passivation layer in the substrate surface.
2. the manufacturing method of tft array substrate according to claim 1, which is characterized in that the material of the active layer is
Metal oxide, including indium gallium zinc or indium zinc oxide.
3. the manufacturing method of tft array substrate according to claim 1, which is characterized in that the protective layer is photoresist.
4. the manufacturing method of tft array substrate according to claim 1, which is characterized in that the S30 further includes：
S301 forms pattern after developing by intermediate tone mask plate to the substrate；
S302 carries out ashing processing to the protective layer.
5. the manufacturing method of tft array substrate according to claim 4, which is characterized in that used in the podzolic process
Gas be one of oxygen or fluoroform or more than one combination, ashing time be 20 seconds to 100 seconds between.
6. the manufacturing method of tft array substrate according to claim 1, which is characterized in that during the conductor
The gas used is rare gas, and the conductor time is between 30 seconds to 60 seconds.
7. the manufacturing method of tft array substrate according to claim 1, which is characterized in that the source electrode and the drain electrode
Material be copper.
8. the manufacturing method of tft array substrate according to claim 1, which is characterized in that the gate insulating layer and institute
State what the material of passivation layer was made of two or more any combination in silica, silicon nitride, nitrogen silicon compound
Lamination layer structure.
9. the manufacturing method of tft array substrate according to claim 1, which is characterized in that the active layer with a thickness of
40 nanometers, the thickness of the source electrode and the drain electrode is 500 nanometers, the passivation layer with a thickness of 100~400 nanometers.
10. a kind of tft array substrate manufactured using method as in one of claimed in any of claims 1 to 9, feature are existed
In, including：
Substrate；
Grid is located at the substrate surface；
Gate insulating layer is located at the substrate surface；
Active layer, is located at the gate insulator layer surface, and the active layer includes that channel, the source electrode positioned at described channel one end are mixed
Miscellaneous area and positioned at the drain doping region of the channel other end；
Source electrode and drain electrode is located at the substrate surface；
Passivation layer is located at the substrate surface.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810561085.9A CN108847408A (en) | 2018-06-04 | 2018-06-04 | A kind of manufacturing method and tft array substrate of tft array substrate |
| PCT/CN2018/104554 WO2019232955A1 (en) | 2018-06-04 | 2018-09-07 | Manufacturing method for tft array substrate, and tft array substrate |
| US16/094,351 US20210225898A1 (en) | 2018-06-04 | 2018-09-07 | Manufacturing method of tft array substrate and tft array substrate |
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| CN201810561085.9A CN108847408A (en) | 2018-06-04 | 2018-06-04 | A kind of manufacturing method and tft array substrate of tft array substrate |
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| US (1) | US20210225898A1 (en) |
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| WO (1) | WO2019232955A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111048523A (en) * | 2019-11-25 | 2020-04-21 | 武汉华星光电半导体显示技术有限公司 | Array substrate and preparation method thereof |
| WO2021003884A1 (en) * | 2019-07-09 | 2021-01-14 | 武汉华星光电半导体显示技术有限公司 | Array substrate and preparation method therefor |
| CN113394235A (en) * | 2021-05-20 | 2021-09-14 | 北海惠科光电技术有限公司 | Array substrate and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104319278A (en) * | 2014-10-22 | 2015-01-28 | 京东方科技集团股份有限公司 | Array substrate, display panel and array substrate manufacturing method |
| CN107464820A (en) * | 2017-09-28 | 2017-12-12 | 深圳市华星光电半导体显示技术有限公司 | ESL type TFT substrates and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TW583890B (en) * | 2002-05-17 | 2004-04-11 | Au Optronics Corp | Manufacturing method of active type organic electroluminescent display |
| CN102651322A (en) * | 2012-02-27 | 2012-08-29 | 京东方科技集团股份有限公司 | Thin film transistor and manufacturing method thereof, array substrate and display device |
| CN102723309B (en) * | 2012-06-13 | 2014-07-02 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof as well as display device |
| CN105470195B (en) * | 2016-01-04 | 2018-11-09 | 武汉华星光电技术有限公司 | The production method of TFT substrate |
| CN106876327B (en) * | 2017-02-17 | 2019-10-15 | 京东方科技集团股份有限公司 | A kind of array substrate and preparation method thereof, display device |
-
2018
- 2018-06-04 CN CN201810561085.9A patent/CN108847408A/en active Pending
- 2018-09-07 WO PCT/CN2018/104554 patent/WO2019232955A1/en active Application Filing
- 2018-09-07 US US16/094,351 patent/US20210225898A1/en not_active Abandoned
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104319278A (en) * | 2014-10-22 | 2015-01-28 | 京东方科技集团股份有限公司 | Array substrate, display panel and array substrate manufacturing method |
| CN107464820A (en) * | 2017-09-28 | 2017-12-12 | 深圳市华星光电半导体显示技术有限公司 | ESL type TFT substrates and preparation method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2021003884A1 (en) * | 2019-07-09 | 2021-01-14 | 武汉华星光电半导体显示技术有限公司 | Array substrate and preparation method therefor |
| CN111048523A (en) * | 2019-11-25 | 2020-04-21 | 武汉华星光电半导体显示技术有限公司 | Array substrate and preparation method thereof |
| CN113394235A (en) * | 2021-05-20 | 2021-09-14 | 北海惠科光电技术有限公司 | Array substrate and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
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| WO2019232955A1 (en) | 2019-12-12 |
| US20210225898A1 (en) | 2021-07-22 |
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