CN108847408A - 一种tft阵列基板的制造方法及tft阵列基板 - Google Patents
一种tft阵列基板的制造方法及tft阵列基板 Download PDFInfo
- Publication number
- CN108847408A CN108847408A CN201810561085.9A CN201810561085A CN108847408A CN 108847408 A CN108847408 A CN 108847408A CN 201810561085 A CN201810561085 A CN 201810561085A CN 108847408 A CN108847408 A CN 108847408A
- Authority
- CN
- China
- Prior art keywords
- tft array
- array substrate
- layer
- manufacturing
- doping region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 88
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 239000010410 layer Substances 0.000 claims abstract description 83
- 239000000463 material Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000011241 protective layer Substances 0.000 claims abstract description 17
- 239000004020 conductor Substances 0.000 claims abstract description 16
- 238000002161 passivation Methods 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 13
- 239000007789 gas Substances 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000004380 ashing Methods 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 229910052733 gallium Inorganic materials 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 5
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 4
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 4
- UMVBXBACMIOFDO-UHFFFAOYSA-N [N].[Si] Chemical compound [N].[Si] UMVBXBACMIOFDO-UHFFFAOYSA-N 0.000 claims description 4
- 238000003475 lamination Methods 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 229910052725 zinc Inorganic materials 0.000 claims description 4
- 239000011701 zinc Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical group 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 3
- 239000007772 electrode material Substances 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 abstract description 8
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 238000002207 thermal evaporation Methods 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- OLUKZDDFBTYGCS-UHFFFAOYSA-N methane trifluoroborane Chemical compound C.B(F)(F)F OLUKZDDFBTYGCS-UHFFFAOYSA-N 0.000 description 2
- 208000032750 Device leakage Diseases 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
Abstract
本发明提供一种TFT阵列基板的制造方法，所述方法包括：提供基板，在所述基板表面依次制备栅极、栅极绝缘层以及有源层；所述有源层包括沟道、源极掺杂区以及漏极掺杂区；在所述沟道表面制备保护层，并将所述源极掺杂区和所述漏极掺杂区导体化；在所述基板表面形成源极和漏极；剥离所述保护层，最后在所述基板表面制备钝化层。本发明还提供一种使用上述TFT阵列基板的制作方法制成的TFT阵列基板。有益效果：本发明所提供的一种TFT阵列基板的制造方法及TFT阵列基板，将源极掺杂区和漏极掺杂区导体化，避免了额外添加阻挡层材料，进一步降低了刻蚀难度，更进一步防止了刻蚀对有源层沟道的损失，最终降低了TFT阵列基板的生产成本。
Description
技术领域
本发明涉及属于平板显示技术领域，尤其涉及一种TFT阵列基板的制造方法及TFT阵列基板。
背景技术
目前TFT-LCD(薄膜晶体管-液晶显示面板)由于具有微功耗、低工作电压、无X射线辐射、高清晰度、小体积等优点，目前广泛应用于手机、掌上电脑等便携式电子产品中。其中，TFT是控制发光的开关，是实现液晶显示器大尺寸的关键，直接关系到高性能平板显示器的发展方向。现在，TFT结构中的底栅型IGZO(Indium Gallium Zinc Oxide，氧化铟镓锌)在制作过程因选择比等问题，导致刻蚀工艺会对IGZO有损伤，造成IGZO表面缺陷，影响器件漏电流及阈值电压和稳定性；源漏极采用铜结构时，因其与基板或者SiO及SiNx附着力差，铜扩散至沟道等问题，需额外添加阻挡层材料，一方面增加刻蚀成本，另一方面会有残留风险。
综上所述，现有技术的TFT阵列基板的制造方法及TFT阵列基板，由于TFT阵列基板制造工艺中源漏极与基板或栅极绝缘层附着力差，致使其扩散至有源层沟道，进而致使增添额外的阻挡层材料，造成刻蚀成本增加且有残留风险的技术问题。
发明内容
本发明提供一种TFT阵列基板的制造方法及TFT阵列基板，用以避免现有的TFT阵列基板制造工艺中源漏极在有源层沟道内残留，以解决源漏极材在沟道内的残留导致的需增添额外的阻挡层材料，进一步造成刻蚀成本增加且有残留风险的技术问题。
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种TFT阵列基板的制造方法，所述方法包括：
S10，提供基板，在所述基板表面制备栅极，之后在所述基板表面制备栅极绝缘层；
S20，在所述栅极绝缘层表面制备有源层，所述有源层包括沟道、位于所述沟道一端的源极掺杂区以及位于所述沟道另一端的漏极掺杂区；
S30，在所述沟道表面制备保护层，并将所述源极掺杂区和所述漏极掺杂区导体化；
S40，在所述基板表面制备金属层，并对所述金属层进行刻蚀，形成源极和漏极；
S50，剥离所述保护层，最后在所述基板表面制备钝化层。
根据本发明一优选实施例，所述有源层的材料为金属氧化物，包括氧化铟镓锌或氧化铟锌。
根据本发明一优选实施例，所述保护层为光刻胶。
根据本发明一优选实施例，所述S30还包括：
S301，通过半色调掩膜板对所述基板显影后形成图案；
S302，对所述保护层进行灰化处理。
根据本发明一优选实施例，所述灰化过程中使用的气体为氧气或三氟甲烷中的一种或一种以上的组合，灰化时间为20秒到100秒之间。
根据本发明一优选实施例，所述导体化的过程中使用的气体为稀有气体，导体化时间为30秒到60秒之间。
根据本发明一优选实施例，所述源极和所述漏极的材料为铜。
根据本发明一优选实施例，所述栅极绝缘层和所述钝化层的材料为氧化硅、氮化硅、氮硅化合物中的两种或两种以上的任意组合所构成的复合层结构。
根据本发明一优选实施例，所述有源层的厚度为40纳米，所述源极和所述漏极的厚度为500纳米，所述钝化层的厚度为100～400纳米。
本发明还提供一种TFT阵列基板，包括：
基板；
栅极，位于所述基板表面；
栅极绝缘层，位于所述基板表面；
有源层，位于所述栅极绝缘层表面，所述有源层包括沟道、位于所述沟道一端的源极掺杂区以及位于所述沟道另一端的漏极掺杂区；
源极和漏极，位于所述基板表面；
钝化层，位于所述基板表面；
本发明的有益效果为：本发明所提供的一种TFT阵列基板的制造方法及TFT阵列基板，将源极掺杂区和漏极掺杂区导体化，避免了额外添加阻挡层材料，进一步降低了刻蚀难度，更进一步防止了刻蚀对有源层沟道的损失，最终降低了TFT阵列基板的生产成本。
附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明TFT阵列基板的制造方法流程图。
图1A-1E为图1所述TFT阵列基板的制造方法示意图。
图2为本发明TFT阵列基板结构示意图。
具体实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有的TFT阵列基板，由于TFT阵列基板制造工艺中源漏极与基板或栅极绝缘层附着力差，致使其扩散至有源层沟道，进而致使增添额外的阻挡层材料，造成刻蚀成本增加且有残留风险的技术问题，本实施例能够解决该缺陷。
如图1所示，本发明提供一种TFT阵列基板制备方法流程，所述方法包括：
S10，提供基板101，在所述基板表面制备栅极102，之后在所述基板表面制备栅极绝缘层103。
具体的，所述S10还包括：
首先利用物理气象沉积法在所述基板101表面刻蚀形成栅极电极图案，得到栅极102；然后，在所述基板101和所述栅极102的表面上利用物理气象沉积法沉积出栅极绝缘层103，如图1A所示。
其中，所述基板101为玻璃基板；所述栅极102的材料可使用为Cu/Ti复合层材料，其中所述栅极102中Cu层的厚度为300nm，所述栅极102中Ti层的厚度为30nm；所述栅极绝缘层103的材料为氧化硅、氮化硅、氮硅化合物中的两种或多种的任意组合所构成的复合层结构，所述栅极绝缘层的厚度为300nm。
S20，在所述栅极绝缘层103表面制备有源层，所述有源层包括沟道104、位于所述沟道一端的源极掺杂区105以及位于所述沟道另一端的漏极掺杂区106。
具体的，所述S20还包括：
在所述栅极绝缘层103表面上利用物理气象沉积法沉积形成所述有源层，所述有源层包括沟道104、位于所述沟道一端的源极掺杂区105以及位于所述沟道另一端的漏极掺杂区106，如图1B所示。
其中，所述有源层的材料为金属氧化物，包括氧化铟镓锌或氧化铟锌；所述有源层的厚度为40nm；所述源极掺杂区105以及位于所述沟道另一端的漏极掺杂区106的面积相同。
S30，在所述沟道104表面制备保护层107，并将所述源极掺杂区105和所述漏极掺杂区106导体化。
具体的，所述S30还包括：
首先在所述基板101上涂覆保护层，再通过半色调光罩显影后形成图案；然后对所述保护层进行灰化处理，减薄所述基板101表面的所述保护层，使所述沟道104完全被所述光阻覆盖；再通过等离子体对所述源极掺杂区105和所述漏极掺杂区106进行导体化，如图1C所示。
其中，所述保护层为光刻胶，光刻胶选用正阻材料；所述灰化过程中使用的气体为氧气或三氟化甲烷中的一种或一种以上的组合，所述灰化时间为20s～100s。优选地，所述灰化气体可以使用三氟化甲烷和氧气的混合气体，灰化时间为30s；优选地，所述灰化气体可以使用氧气，灰化时间为40s；所述导体化过程中使用的气体为稀有气体，所述导体化时间为30s～60s，优选为氩气或氦气。
S40，在所述基板101表面制备金属层，并对所述金属层进行刻蚀，形成源极108和漏极109；
具体的，所述S40还包括：
首先通过物理气象沉积法在所述101表面沉积出金属层；然后对所述金属层进行刻蚀，通过光刻胶形成源极108和漏极109；此时由于所述沟道104被所述保护层107保护，在刻蚀所述金属层的过程中不受影响，避免了对所述沟道的刻蚀；导体化的所述源极掺杂区105和所述漏极掺杂区106充当了阻挡层材料，防止了所述金属层扩散至所述沟道104，如图1D所示。
其中，所述金属层所使用的材料为铜；所述金属层的厚度为500纳米；刻蚀过程中，可以使用不含氟铜酸。
S50，剥离所述保护层107，最后在所述基板101表面制备钝化层110。
具体的，所述S50还包括：
使用剥离液剥离所述保护层107，在所述基板101表面沉积出所述钝化层，此时，TFT阵列基板沟道全部形成图案，如图1E所示。
其中，所述钝化层110的材料为氧化硅、氮化硅、氮硅化合物中的两种或多种的任意组合所构成的复合层结构；所述钝化层110的厚度为100～400纳米；制备所述钝化层的过程中使用的热蒸发气体为N2或O2，热蒸发处理时间为60～150min，热蒸发处理温度为200～400℃。优选地，所述钝化层110为SiO/SiNx叠层，厚度为300/200nm；优选地，所述热蒸发处理过程中，热蒸发气体为氧气；时间为120min，温度为250℃。优选地，热蒸发处理过程中，热蒸发气体为氮气；时间为100min，温度为300℃。
根据上述的制作方法，可得到一种采用背沟道刻蚀型的TFT元件的阵列基板，如图2所示，包括：
基板201；
栅极202，位于所述基板201表面；
栅极绝缘层203，位于所述基板201表面；
有源层，所述有源层包括沟道204、位于所述沟道一端的源极掺杂区205以及位于所述沟道另一端的漏极掺杂区206，位于所述栅极绝缘层203表面；
源极207以及漏极208，位于所述基板201表面；
钝化层108，位于所述基板表面；
其中，所述源极掺杂区205以及漏极掺杂区206均进行导体化处理。
本发明的有益效果为：本发明所提供的一种TFT阵列基板的制造方法及TFT阵列基板，将源极掺杂区和漏极掺杂区导体化，避免了额外添加阻挡层材料，进一步降低了刻蚀难度，更进一步防止了刻蚀对有源层沟道的损失，最终降低了TFT阵列基板的生产成本。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
Claims (10)
1.一种TFT阵列基板的制造方法，其特征在于，所述方法包括：
S10，提供基板，在所述基板表面制备栅极，之后在所述基板表面制备栅极绝缘层；
S20，在所述栅极绝缘层表面制备有源层，所述有源层包括沟道、位于所述沟道一端的源极掺杂区以及位于所述沟道另一端的漏极掺杂区；
S30，在所述沟道表面制备保护层，并将所述源极掺杂区和所述漏极掺杂区导体化；
S40，在所述基板表面制备金属层，并对所述金属层进行刻蚀，形成源极和漏极；
S50，剥离所述保护层，最后在所述基板表面制备钝化层。
2.根据权利要求1所述的TFT阵列基板的制造方法，其特征在于，所述有源层的材料为金属氧化物，包括氧化铟镓锌或氧化铟锌。
3.根据权利要求1所述的TFT阵列基板的制造方法，其特征在于，所述保护层为光刻胶。
4.根据权利要求1所述的TFT阵列基板的制造方法，其特征在于，所述S30还包括：
S301，通过半色调掩膜板对所述基板显影后形成图案；
S302，对所述保护层进行灰化处理。
5.根据权利要求4所述的TFT阵列基板的制造方法，其特征在于，所述灰化过程中使用的气体为氧气或三氟甲烷中的一种或一种以上的组合，灰化时间为20秒到100秒之间。
6.根据权利要求1所述的TFT阵列基板的制造方法，其特征在于，所述导体化的过程中使用的气体为稀有气体，导体化时间为30秒到60秒之间。
7.根据权利要求1所述的TFT阵列基板的制造方法，其特征在于，所述源极和所述漏极的材料为铜。
8.根据权利要求1所述的TFT阵列基板的制造方法，其特征在于，所述栅极绝缘层和所述钝化层的材料为氧化硅、氮化硅、氮硅化合物中的两种或两种以上的任意组合所构成的复合层结构。
9.根据权利要求1所述的TFT阵列基板的制造方法，其特征在于，所述有源层的厚度为40纳米，所述源极和所述漏极的厚度均为500纳米，所述钝化层的厚度为100～400纳米。
10.一种使用如权利要求1至9中任意一项所述的方法制造的TFT阵列基板，其特征在于，包括：
基板；
栅极，位于所述基板表面；
栅极绝缘层，位于所述基板表面；
有源层，位于所述栅极绝缘层表面，所述有源层包括沟道、位于所述沟道一端的源极掺杂区以及位于所述沟道另一端的漏极掺杂区；
源极和漏极，位于所述基板表面；
钝化层，位于所述基板表面。
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810561085.9A CN108847408A (zh) | 2018-06-04 | 2018-06-04 | 一种tft阵列基板的制造方法及tft阵列基板 |
| US16/094,351 US20210225898A1 (en) | 2018-06-04 | 2018-09-07 | Manufacturing method of tft array substrate and tft array substrate |
| PCT/CN2018/104554 WO2019232955A1 (zh) | 2018-06-04 | 2018-09-07 | 一种tft阵列基板的制造方法及tft阵列基板 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810561085.9A CN108847408A (zh) | 2018-06-04 | 2018-06-04 | 一种tft阵列基板的制造方法及tft阵列基板 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108847408A true CN108847408A (zh) | 2018-11-20 |
Family
ID=64210626
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810561085.9A Pending CN108847408A (zh) | 2018-06-04 | 2018-06-04 | 一种tft阵列基板的制造方法及tft阵列基板 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20210225898A1 (zh) |
| CN (1) | CN108847408A (zh) |
| WO (1) | WO2019232955A1 (zh) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111048523A (zh) * | 2019-11-25 | 2020-04-21 | 武汉华星光电半导体显示技术有限公司 | 阵列基板及其制备方法 |
| WO2021003884A1 (zh) * | 2019-07-09 | 2021-01-14 | 武汉华星光电半导体显示技术有限公司 | 阵列基板及其制备方法 |
| CN113394235A (zh) * | 2021-05-20 | 2021-09-14 | 北海惠科光电技术有限公司 | 阵列基板及阵列基板的制造方法 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104319278A (zh) * | 2014-10-22 | 2015-01-28 | 京东方科技集团股份有限公司 | 阵列基板、显示面板和阵列基板的制作方法 |
| CN107464820A (zh) * | 2017-09-28 | 2017-12-12 | 深圳市华星光电半导体显示技术有限公司 | Esl型tft基板及其制作方法 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW583890B (en) * | 2002-05-17 | 2004-04-11 | Au Optronics Corp | Manufacturing method of active type organic electroluminescent display |
| CN102651322A (zh) * | 2012-02-27 | 2012-08-29 | 京东方科技集团股份有限公司 | 一种薄膜晶体管及其制造方法、阵列基板、显示器件 |
| CN102723309B (zh) * | 2012-06-13 | 2014-07-02 | 京东方科技集团股份有限公司 | 一种阵列基板及其制造方法和显示装置 |
| CN105470195B (zh) * | 2016-01-04 | 2018-11-09 | 武汉华星光电技术有限公司 | Tft基板的制作方法 |
| CN106876327B (zh) * | 2017-02-17 | 2019-10-15 | 京东方科技集团股份有限公司 | 一种阵列基板及其制备方法、显示装置 |
-
2018
- 2018-06-04 CN CN201810561085.9A patent/CN108847408A/zh active Pending
- 2018-09-07 US US16/094,351 patent/US20210225898A1/en not_active Abandoned
- 2018-09-07 WO PCT/CN2018/104554 patent/WO2019232955A1/zh active Application Filing
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104319278A (zh) * | 2014-10-22 | 2015-01-28 | 京东方科技集团股份有限公司 | 阵列基板、显示面板和阵列基板的制作方法 |
| CN107464820A (zh) * | 2017-09-28 | 2017-12-12 | 深圳市华星光电半导体显示技术有限公司 | Esl型tft基板及其制作方法 |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021003884A1 (zh) * | 2019-07-09 | 2021-01-14 | 武汉华星光电半导体显示技术有限公司 | 阵列基板及其制备方法 |
| CN111048523A (zh) * | 2019-11-25 | 2020-04-21 | 武汉华星光电半导体显示技术有限公司 | 阵列基板及其制备方法 |
| CN113394235A (zh) * | 2021-05-20 | 2021-09-14 | 北海惠科光电技术有限公司 | 阵列基板及阵列基板的制造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20210225898A1 (en) | 2021-07-22 |
| WO2019232955A1 (zh) | 2019-12-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10312271B2 (en) | Array substrate, manufacturing method thereof and display device | |
| US9391207B2 (en) | Thin film transistor, array substrate and manufacturing method thereof, and display device | |
| US7569856B2 (en) | Semiconductor device and method for manufacturing the same | |
| US9761616B2 (en) | Manufacturing method of array substrate with reduced number of patterning processes array substrate and display device | |
| TWI385760B (zh) | 製造陣列基板的方法 | |
| US9935177B2 (en) | Manufacturing methods of thin film transistor having an ohmic contact region and array substrate including the same | |
| CN110867458B (zh) | 金属氧化物半导体薄膜晶体管阵列基板及制作方法 | |
| CN108550625A (zh) | 一种薄膜晶体管及其制作方法 | |
| CN108847408A (zh) | 一种tft阵列基板的制造方法及tft阵列基板 | |
| US20160284741A1 (en) | Array substrate fabricating method | |
| WO2015096307A1 (zh) | 氧化物薄膜晶体管、显示器件、及阵列基板的制造方法 | |
| US20150295094A1 (en) | Thin film transistor, manufacturing method thereof, array substrate and display device | |
| WO2015165174A1 (zh) | 一种薄膜晶体管及其制作方法、显示基板、显示装置 | |
| CN106384714B (zh) | 薄膜晶体管及其制备方法、阵列基板 | |
| CN107808826A (zh) | 一种底发射顶栅自对准薄膜晶体管的制备方法 | |
| CN105068335A (zh) | 一种ffs阵列基板的制造方法 | |
| KR101423907B1 (ko) | 산화물 박막 트랜지스터 및 그 제조방법 | |
| WO2020232964A1 (zh) | 一种薄膜晶体管基板的制备方法 | |
| US20140183541A1 (en) | Thin film transistor, manufacturing method thereof, array substrate and display device | |
| US10340387B2 (en) | Low temperature poly-silicon thin film transistor, manufacturing method thereof, and array substrate | |
| CN104091832A (zh) | 薄膜晶体管及其制作方法、阵列基板和显示装置 | |
| US9478665B2 (en) | Thin film transistor, method of manufacturing the same, display substrate and display apparatus | |
| CN107369719B (zh) | 一种氧化物薄膜晶体管纯铜复合结构源漏电极及其制备方法 | |
| JPH08250743A (ja) | 半導体装置の作製方法 | |
| EP3267473B1 (en) | Pixel structure manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20181120 |
|
| RJ01 | Rejection of invention patent application after publication |