CN104091832A - 薄膜晶体管及其制作方法、阵列基板和显示装置 - Google Patents

薄膜晶体管及其制作方法、阵列基板和显示装置 Download PDF

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CN104091832A
CN104091832A CN201410302915.8A CN201410302915A CN104091832A CN 104091832 A CN104091832 A CN 104091832A CN 201410302915 A CN201410302915 A CN 201410302915A CN 104091832 A CN104091832 A CN 104091832A
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active layer
film transistor
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silicon oxide
ohmic contact
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CN104091832B (zh
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谢振宇
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Beijing BOE Optoelectronics Technology Co Ltd
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Abstract

本发明实施例公开了一种薄膜晶体管及其制作方法、阵列基板和显示装置，涉及显示技术领域，能够有效降低薄膜晶体管边缘漏电流IOFF(edge)。该薄膜晶体管包括有源层、栅极、源极和漏极，所述有源层的侧面上设置有氧化硅层。

Description

薄膜晶体管及其制作方法、阵列基板和显示装置
技术领域
本发明涉及显示技术领域，尤其涉及一种薄膜晶体管及其制作方法、阵列基板和显示装置。
背景技术
薄膜晶体管的漏电流IOFF过大是显示装置的一种常见缺陷，具体地，漏电流为薄膜晶体管处于关闭状态时，薄膜晶体管内部的电流，漏电流过大会造成像素电极显示灰度偏差、显示装置电能耗损变大等不利现象出现。因此，如何抑制漏电流成为本领域技术人员的一个重要研究方向。
图1所示为现有技术中的一种薄膜晶体管，该薄膜晶体管包括依次设置的有源层1’、栅极绝缘层2’、栅极3’、层间绝缘层4’、源极5’和漏极6’。对于上述结构的薄膜晶体管而言，漏电流主要包括两部分：源极5’和漏极6’之间的薄膜晶体管主体漏电流IOFF(main)、栅极3’与源极5’之间的漏电流和栅极3’与漏极6’之间的漏电流组成的薄膜晶体管边缘漏电流IOFF(edge)。
当有源层1’侧面的栅极绝缘层2’覆盖性不佳或栅极绝缘层2’较薄时，栅极3’与源极5’、栅极3’与漏极6’形成的寄生电容较大，导致薄膜晶体管边缘漏电流IOFF(edge)增大，进而导致薄膜晶体管的漏电流增大。
发明内容
本发明所要解决的技术问题在于提供一种薄膜晶体管及其制作方法、阵列基板和显示装置，能够有效降低薄膜晶体管边缘漏电流IOFF(edge)。
为解决上述技术问题，本发明实施例提供了一种薄膜晶体管，采用如下技术方案：
一种薄膜晶体管，包括有源层、栅极、源极和漏极，所述有源层的侧面上设置有氧化硅层。
所述氧化硅层的厚度为
所述有源层包括用于与所述源极和所述漏极接触的欧姆接触区，以及位于所述欧姆接触区内侧的低掺杂区。
所述薄膜晶体管还包括栅极绝缘层和层间绝缘层，所述栅极绝缘层位于所述有源层上方，所述栅极位于所述栅极绝缘层上方，所述层间绝缘层位于所述栅极上方，所述源极和所述漏极位于所述层间绝缘层上方，并通过所述层间绝缘层和所述栅极绝缘层的过孔与所述有源层电连接。
本发明实施例提供了一种薄膜晶体管，该薄膜晶体管包括有源层、栅极、源极和漏极，有源层的侧面上设置有氧化硅层。由于氧化硅层为绝缘体，因此，在形成栅极绝缘层之前，整个有源层侧面均覆盖有绝缘的氧化硅层，从而保证了有源层侧面的绝缘层的厚度以及绝缘效果，进而可以有效降低薄膜晶体管边缘漏电流IOFF(edge)，进而降低薄膜晶体管的漏电流，改善显示装置的显示效果，降低显示装置的电能耗损。
此外，本发明实施例还提供了一种阵列基板，该阵列基板包括衬底基板以及以上任一项所述的薄膜晶体管。
此外，本发明实施例还提供了一种显示装置，该显示装置包括以上所述的阵列基板。
为了进一步解决上述技术问题，本发明实施例还提供了一种薄膜晶体管的制作方法，采用如下技术方案：
一种薄膜晶体管的制作方法包括：
在衬底基板上形成包括有源层的图形；
在所述有源层的侧面上形成氧化硅层。
所述在所述有源层的侧面上形成氧化硅层，包括：
对所述有源层的侧面进行氧化工艺处理，以形成所述氧化硅层。
所述在衬底基板上形成包括有源层的图形，包括：
在所述衬底基板上形成一层非晶硅，经过晶化工艺使所述非晶硅转变为多晶硅；
在所述多晶硅上形成一层光刻胶，经过曝光、显影、刻蚀后，形成包括所述有源层的图形，所述有源层上覆盖有所述光刻胶；
对所述有源层的侧面进行氧化工艺处理，以形成所述氧化硅层，之后包括：
剥离所述有源层上覆盖的所述光刻胶。
所述氧化工艺处理为热氧化工艺处理或者氧等离子体氧化工艺处理。
所述氧化工艺处理为氧等离子体氧化工艺处理，所述氧化工艺处理的时间为10s～40s。
所述薄膜晶体管的制作方法还包括：
使所述有源层形成欧姆接触区和低掺杂区，所述低掺杂区位于所述欧姆接触区内侧。
所述使所述有源层形成欧姆接触区和低掺杂区，包括：
通过离子注入的方法向有源层内掺入B元素；
通过离子注入的方法向所述有源层的用于与所述源极或者所述漏极连接的区域中掺入P元素，以形成所述欧姆接触区；
通过离子注入的方法向位于所述欧姆接触区内侧的区域掺杂比所述欧姆接触区少的P元素，以形成所述低掺杂区。
本发明实施例提供了一种薄膜晶体管的制作方法，该薄膜晶体管的制作方法包括在衬底基板上形成包括有源层的图形，在有源层的侧面上形成氧化硅层。由于氧化硅层为绝缘体，因此，在形成栅极绝缘层之前，整个有源层侧面均覆盖有绝缘的氧化硅层，从而保证了有源层侧面的绝缘层的厚度以及绝缘效果，进而可以有效降低薄膜晶体管边缘漏电流IOFF(edge)，进而降低薄膜晶体管的漏电流，改善显示装置的显示效果，降低显示装置的电能耗损。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中的薄膜晶体管的示意图；
图2为本发明实施例中的薄膜晶体管的平面示意图；
图3为图2所示的薄膜晶体管沿A-A’方向的截面示意图；
图4为本发明实施例中的薄膜晶体管的制作流程图一；
图5为本发明实施例中的薄膜晶体管的制作流程图二。
附图标记说明：
1—衬底基板；     2—有源层；     21—欧姆接触区；
22—低掺杂区；    3—栅极绝缘层； 4—栅极；
5—层间绝缘层；   6—源极；       7—漏极；
8—氧化硅层。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例一
本发明实施例提供了一种薄膜晶体管，能够有效降低薄膜晶体管边缘漏电流IOFF(edge)。
具体地，如图2和图3所示，该薄膜晶体管包括有源层2、栅极4、源极6和漏极7，其中，有源层2的侧面上设置有氧化硅层8。由于氧化硅层8为绝缘体，因此，在形成栅极绝缘层之前，整个有源层2侧面均覆盖有绝缘的氧化硅层8，从而保证了有源层2侧面的绝缘层的厚度以及绝缘效果，进而可以有效降低薄膜晶体管边缘漏电流IOFF(edge)。其中，所述有源层2的侧面是指除有源层的上表面和底表面之外的侧面。具体地，有源层2的材质为多晶硅，氧化硅层8的厚度可以为，优选为
进一步地，为了降低有源层2和源极6、漏极7的接触电阻，改善薄膜晶体管的性能，本发明实施例中的有源层2包括用于与源极6和漏极7接触的欧姆接触区21。进一步地，为了降低薄膜晶体管的源极6和漏极7之间的薄膜晶体管主体漏电流IOFF(main)，如图2和图3所示，本发明实施例中的有源层2还包括位于欧姆接触区21内侧的低掺杂区22。所述欧姆接触区21位于有源层的两侧的区域，所述低掺杂层位于有源层的欧姆接触区21的内侧，且与所述欧姆接触区21相邻。
此外，如图3所示，薄膜晶体管还包括栅极绝缘层3和层间绝缘层5，具体地，栅极绝缘层3位于有源层2上方，栅极4位于栅极绝缘层3上方，层间绝缘层5位于栅极4上方，源极6和漏极7位于层间绝缘层5上方，并通过层间绝缘层5和栅极绝缘层3的过孔与有源层2电连接。需要说明的是，本发明实施例中提供的薄膜晶体管的结构并不局限于此，本领域技术人员可以根据实际情况进行设定，本发明实施例对此不进行赘述。
进一步地，本发明实施例中的薄膜晶体管还包括位于衬底基板1与有源层2之间的缓冲层(图中未示出)，缓冲层用于将衬底基板1与有源层2隔绝，避免衬底基板1中的杂质进入有源层2，影响薄膜晶体管的性能，此外缓冲层还可减少形成有源层2的过程中温度对衬底基板1的影响。缓冲层的材质优选为氧化硅或者氮化硅。
本发明实施例提供了一种薄膜晶体管，该薄膜晶体管包括有源层、栅极、源极和漏极，有源层的侧面上设置有氧化硅层。由于氧化硅层为绝缘体，因此，整个有源层侧面均覆盖有绝缘的氧化硅层，从而保证了有源层侧面的绝缘层的厚度以及绝缘效果，进而可以有效降低薄膜晶体管边缘漏电流IOFF(edge)，进而降低薄膜晶体管的漏电流，改善显示装置的显示效果，降低显示装置的电能耗损。
此外，本发明实施例还提供了一种阵列基板，该阵列基板包括衬底基板以及以上任一种实施方式所述的薄膜晶体管。该阵列基板还可以包括像素电极、钝化层等结构，本领域技术人员基于本申请的前提下，在不付出创造性劳动的情况下即可获得，本发明实施例对此不再进行赘述。
此外，本发明实施例还提供了一种显示装置，该显示装置包括以上所述的阵列基板。具体地，该显示装置可为：液晶面板、电子纸、液晶电视、液晶显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
实施例二
本发明实施例提供了一种薄膜晶体管的制作方法，具体地，如图4所示，该薄膜晶体管的制作方法包括：
步骤S401、在衬底基板上形成包括有源层的图形。
具体地，在衬底基板1上形成包括有源层2的图形，包括：
首先，在衬底基板1上形成一层非晶硅，经过晶化工艺使非晶硅转变为多晶硅。晶化工艺包括激光退火工艺、金属诱导工艺等。本发明实施例中的晶化工艺优选为激光退火工艺，具体地，激光退火工艺的基本原理为利用高能量的准分子激光照射到非晶硅表面，使非晶硅融化、冷却、再结晶，从而使非晶硅转变为多晶硅。然后，在多晶硅上形成一层光刻胶，经过曝光、显影、刻蚀后，形成包括有源层2的图形，有源层2上覆盖有光刻胶，以保证后续在有源层2的侧面形成氧化硅层8的过程中不对有源层2的其他区域产生影响。
进一步地，为了改善制作的薄膜晶体管的性能，本发明实施例优选在衬底基板1上形成有源层2之前先在衬底基板1上形成缓冲层。
步骤S402、在有源层的侧面上形成氧化硅层。
具体地，在有源层2的侧面上形成氧化硅层8，包括对有源层2的侧面进行氧化工艺处理，以形成氧化硅层8。氧化工艺处理可以为热氧化工艺处理或者氧等离子体氧化工艺处理。本发明实施例中优选氧化工艺处理为氧等离子体氧化工艺处理，氧化工艺处理的时间为10s～40s，优选为20s。氧等离子体氧化工艺处理形成氧化硅层8的过程可以为：首先，在干法刻蚀设备中使氧气在电场作用下发生电离从而形成氧等离子体；而后，利用电场对生成的氧等离子体进行加速，并将电离加速后的氧等离子体注入到有源层2侧面，使得氧等离子体与有源层2侧面的具有不饱和键的硅原子接触，氧等离子体与该不饱和键结合，形成硅氧键，此外具有一定速度的氧等离子体还可以打破原有的硅硅键，形成硅氧键，从而在有源层2的侧面形成氧化硅层8。
对有源层2的侧面进行氧化工艺处理，形成氧化硅层之后剥离有源层2上覆盖的光刻胶。
此外，由于通常采用干法刻蚀的方法来形成包括有源层2的图形，干法刻蚀过程中，离子对有源层2侧面的轰击会对有源层2造成潜藏性损伤，从而影响薄膜晶体管的特性和稳定性。示例性地，上述潜藏性损伤可以表现为有源层2侧面不平整，侧面存在许多缺陷和不饱和键。本发明实施例中采用氧等离子体氧化工艺处理形成氧化硅层8的过程中，在氧等离子体的作用下，经过干法刻蚀形成的具有许多缺陷和不饱和键的有源层2的侧面形成了氧化硅层8，进而实现了对有源层2内的潜藏性损伤的修复，进一步提高了薄膜晶体管的特性和稳定性。
上述薄膜晶体管的制作方法还可以包括：使有源层2形成欧姆接触区21和低掺杂区22，其中，欧姆接触区21的作用在于降低有源层2和源极6、漏极7的接触电阻，提升薄膜晶体管的性能，低掺杂区22位于有源层2的欧姆接触区21内侧，低掺杂区22的作用在于降低薄膜晶体管主体漏电流IOFF(main)，以进一步降低薄膜晶体管的漏电流。
进一步地，为了便于本领域技术人员理解，本发明实施例提供了一种如图5所示的薄膜晶体管的具体制作方法，该制作方法包括：首先，在衬底基板1上形成缓冲层(图中未示出)，以保证在有源层2晶化过程中衬底基板1不受损坏，在缓冲层上形成包括有源层2的图形，在有源层2的侧面形成氧化硅层8，剥离有源层2上的光刻胶；然后，通过离子注入的方法使有源层2成为p型半导体，示例性地，可以通过离子注入的方法向有源层2内掺入B元素以使得有源层2成为p型半导体；再通过离子注入的方法使有源层2上形成欧姆接触区，示例性地，可以通过离子注入的方法向有源层2的用于与源极6或者漏极7连接的区域中掺入P元素，从而增加该区域的电子浓度，以形成欧姆接触区21；然后，依次形成栅极绝缘层3、形成包括栅极4的图形、形成层间绝缘层5以及形成包括源极6和漏极7的图形；最后，通过离子注入的方法使有源层2形成低掺杂区22，示例性地，通过离子注入的方法向位于欧姆接触区21内侧的区域掺杂比欧姆接触区21少的P元素，以形成低掺杂区22。
本发明实施例提供了一种薄膜晶体管的制作方法，该薄膜晶体管的制作方法包括在衬底基板上形成包括有源层的图形，在有源层的侧面上形成氧化硅层。由于氧化硅层为绝缘体，因此，在形成栅极绝缘层之前，整个有源层侧面均覆盖有绝缘的氧化硅层，从而保证了有源层侧面的绝缘层的厚度以及绝缘效果，
进而可以有效降低薄膜晶体管边缘漏电流IOFF(edge)，进而降低薄膜晶体管的漏电流，改善显示装置的显示效果，降低显示装置的电能耗损。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (13)

1.一种薄膜晶体管，包括有源层、栅极、源极和漏极，其特征在于，所述有源层的侧面上设置有氧化硅层。
2.根据权利要求1所述的薄膜晶体管，其特征在于，所述氧化硅层的厚度为
3.根据权利要求1所述的薄膜晶体管，其特征在于，所述有源层包括用于与所述源极和所述漏极接触的欧姆接触区，以及位于所述欧姆接触区内侧的低掺杂区。
4.根据权利要求1所述的薄膜晶体管，其特征在于，还包括栅极绝缘层和层间绝缘层，所述栅极绝缘层位于所述有源层上方，所述栅极位于所述栅极绝缘层上方，所述层间绝缘层位于所述栅极上方，所述源极和所述漏极位于所述层间绝缘层上方，所述源极和所述漏极通过所述层间绝缘层和所述栅极绝缘层的过孔与所述有源层电连接。
5.一种阵列基板，其特征在于，包括衬底基板以及如权利要求1-4任一项所述的薄膜晶体管。
6.一种显示装置，其特征在于，包括如权利要求5所述的阵列基板。
7.一种薄膜晶体管的制作方法，其特征在于，包括：
在衬底基板上形成包括有源层的图形；
在所述有源层的侧面上形成氧化硅层。
8.根据权利要求7所述的薄膜晶体管的制作方法，其特征在于，所述在所述有源层的侧面上形成氧化硅层，包括：
对所述有源层的侧面进行氧化工艺处理，以形成所述氧化硅层。
9.根据权利要求8所述的薄膜晶体管的制作方法，其特征在于，
所述在衬底基板上形成包括有源层的图形，包括：
在所述衬底基板上形成一层非晶硅，经过晶化工艺使所述非晶硅转变为多晶硅；
在所述多晶硅上形成一层光刻胶，经过曝光、显影、刻蚀后，形成包括所述有源层的图形，所述有源层上覆盖有所述光刻胶；
对所述有源层的侧面进行氧化工艺处理，以形成所述氧化硅层，之后包括：
剥离所述有源层上覆盖的所述光刻胶。
10.根据权利要求8或9所述的薄膜晶体管的制作方法，其特征在于，
所述氧化工艺处理为热氧化工艺处理或者氧等离子体氧化工艺处理。
11.根据权利要求10所述的薄膜晶体管的制作方法，其特征在于，
所述氧化工艺处理为氧等离子体氧化工艺处理，所述氧化工艺处理的时间为10s～40s。
12.根据权利要求9所述的薄膜晶体管的制作方法，其特征在于，还包括：
使所述有源层形成欧姆接触区和低掺杂区，所述低掺杂区位于所述欧姆接触区内侧。
13.根据权利要求12所述的薄膜晶体管的制作方法，其特征在于，所述使所述有源层形成欧姆接触区和低掺杂区，包括：
通过离子注入的方法向有源层内掺入B元素；
通过离子注入的方法向所述有源层的用于与所述源极或者所述漏极连接的区域中掺入P元素，以形成所述欧姆接触区；
通过离子注入的方法向所述有源层的位于所述欧姆接触区内侧的区域掺杂比所述欧姆接触区少的P元素，以形成所述低掺杂区。
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