WO2013185454A1

WO2013185454A1 - Array substrate, fabrication method thereof, and display device

Info

Publication number: WO2013185454A1
Application number: PCT/CN2012/086309
Authority: WO
Inventors: 黄炜赟; 玄明花; 高永益
Original assignee: 京东方科技集团股份有限公司; 成都京东方光电科技有限公司
Priority date: 2012-06-13
Filing date: 2012-12-10
Publication date: 2013-12-19
Also published as: CN102723309A; CN102723309B

Abstract

An array substrate, a fabrication method thereof, and a display device. The fabrication method of the array substrate comprises: sequentially depositing a first transparent conductive thin film (25) and an insulating thin film (26) on a gate insulating layer (24), a semiconductor active layer (34), a data line (21), a source (22), and a drain (23); forming, through one patterning process, a pixel electrode (253) that is located at a pixel electrode region, formed of the first transparent conductive thin film, and connected to the drain, a data line additional layer (252) that is located at a data line region and formed of the first transparent conductive thin film, and a passivation layer (261) that is located at the pixel electrode region, the data line region, a source region, and a drain region, covers the pixel electrode, the data line additional layer, the source, and the drain, and is formed of the insulating thin film. The edge of the pixel electrode is located under the coverage of the passivation layer.

Description

Array substrate, manufacturing method thereof and display device

Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique

Advanced Super-Dimensional Field Switching (ADS), which forms a multi-dimensional electric field by the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer, so that the inside of the liquid crystal cell All the aligned liquid crystal molecules between the slit electrodes and directly above the electrodes can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency. Advanced super-dimensional field switching technology can improve the picture quality of TFT-LCD (Thin Film Transistor-Liquid Crystal Display) products with high resolution, high transmittance, low power consumption, wide viewing angle and high Opening ratio, low chromatic aberration, and no push mura.

Compared with other liquid crystal displays, ADS liquid crystal displays have the advantage of expanding the viewing angle, and occupy an important position in the current flat panel display market. However, for ADS liquid crystal displays, the array substrate and its manufacturing process determine the performance and price of the product. In the traditional manufacturing process, the array substrate is usually fabricated with a mask process of 6 times. Yes, gate mask, semiconductor active layer mask, source drain mask, first indium tin oxide (1 ^st ITO ) mask, passivation layer mask, second indium tin oxide (2 ^nd ITO ) mask.

However, the cost and complexity of the masking process are high, and the more applications, the higher the manufacturing cost and the lower the production efficiency. Summary of the invention

Embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a display device. By reducing the number of mask processes, manufacturing costs are reduced, process flow is simplified, and production efficiency is improved.

In order to achieve the above object, embodiments of the present invention use the following technical solutions:

In one aspect, a method of fabricating an array substrate is provided, including

Forming on the substrate including a gate line, a gate, a gate insulating layer, a semiconductor active layer, a data line, a source Pole and drain patterns;

Depositing a first transparent conductive film and an insulating film on the gate insulating layer, the semiconductor active layer, the data line, the source, and the drain;

Forming, by a patterning process, a pixel electrode formed by the first transparent conductive film and connected to the drain, and a data line formed by the first transparent conductive film in the data line region is attached a layer, the pixel electrode region, the data line region, the source region, and the drain region covering the pixel electrode, the data line additional layer, the source, and the drain formed by the insulating film The edge of the pixel electrode is located within the coverage of the passivation layer.

In one embodiment, the manufacturing method may further deposit a second transparent conductive film on the passivation layer, and form a common electrode having slits by a patterning process.

In one aspect, an array substrate is provided, including:

Substrate

a gate line, a gate, a gate insulating layer, a semiconductor active layer, a data line, a source and a drain formed on the substrate;

Forming an additional layer of conductive data lines over the data line, a pixel electrode formed in the pixel electrode region; wherein the data line additional layer is in the same layer as the pixel electrode and has the same material; formed in the data a line additional layer and a passivation layer on the pixel electrode; wherein an edge of the pixel electrode is located within a coverage of the passivation layer.

In one embodiment, the array substrate may further include a common electrode formed on the passivation layer.

The data line additional layer, the pixel electrode, and the passivation layer can be obtained by a single patterning process using a common mask template.

In one aspect, a display device is provided, including the array substrate described above.

In the array substrate and the manufacturing method thereof and the display device provided by the embodiments of the present invention, in the method for manufacturing the array substrate, after the first transparent conductive film and the insulating film are sequentially deposited on the substrate, the pixel electrode and the pattern are formed by one patterning process. a passivation layer, and the edge of the etched pixel electrode is located within the range of the passivation layer, which can be in the array compared to the prior art method of fabricating the pixel electrode and the passivation layer by two mask processes The number of mask processes is reduced during the fabrication of the substrate, thereby reducing manufacturing costs, simplifying the process flow, and improving production efficiency. DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, and are not intended to limit the present invention. .

1 is a schematic diagram showing a partial structure of an array substrate according to an embodiment of the present invention; FIG. 2 is a schematic diagram showing a partial structure of another array substrate according to an embodiment of the present invention; FIG. 3 to FIG. 8 are provided according to an embodiment of the present invention. Schematic diagram of the structure of the array substrate in the process of manufacturing an array substrate;

FIG. 9 is a schematic diagram of another array substrate according to an embodiment of the present invention; FIG.

FIG. 10 to FIG. 16 are schematic diagrams showing the structure of an array substrate in another method of fabricating an array substrate according to an embodiment of the present invention. detailed description

The technical solutions of the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings of the embodiments of the present invention. It is apparent that the described embodiments are part of the embodiments of the invention, rather than all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.

The method for manufacturing an array substrate provided by the embodiment of the invention includes:

Sl l, forming a pattern including a gate line, a gate, a gate insulating layer, a semiconductor active layer, a data line, a source, and a drain on the substrate.

The step S11 can be specifically implemented by, for example, the following two methods, but is not limited thereto: The first method may include the following steps: The structure of the formed array substrate (partial structure of the array substrate) is as shown in FIG. 1:

Sl lal, depositing a first metal thin film on the substrate 20, and forming a pattern including a gate line (not shown) and a gate electrode 201 by a patterning process.

S 11 a2, a gate insulating layer 24 is formed on the gate line, the gate electrode 201, and the substrate 20.

Sl la3 forms a pattern including the semiconductor active layer 34, the data line 21, the source 22, and the drain 23 on the gate insulating layer 24. The gate electrode 201, the semiconductor active layer 34, the source electrode 22, and the drain electrode 23 constitute a TFT. The second method may include the following steps: The structure of the formed array substrate (partial structure of the array substrate) is as shown in FIG. 2:

Sl lb1, a semiconductor thin film is deposited on the substrate 20, and a pattern including the semiconductor active layer 34 is formed by one patterning process.

Sl lb2, a first gate insulating layer 38 is formed on the semiconductor active layer 34, and a first via 351 and a second via 352 are formed on the first gate insulating layer 38 by one patterning process. The first via 351 and the second via 352 are respectively located at both ends of the semiconductor active layer 34, and the semiconductor active layer 34 is exposed.

Sl lb3, depositing a first metal thin film on the first gate insulating layer 38, and forming a pattern including a gate line (not shown) and a gate electrode 201 by one patterning process.

Sl lb4, using the gate electrode 201 as a mask, the semiconductor active layer 34 outside the coverage of the gate electrode 201 is converted into the doped semiconductor active layer 36 by an ion implantation process.

Sl lb5, a second gate insulating layer 37 is formed on the gate line and the gate electrode 201, and a third via hole 353 and a fourth via hole 354 are formed on the second gate insulating layer 37 by one patterning process. The third via 353 corresponds to the first via 351 and exposes the first via 351; the fourth via 354 corresponds to the second via 352, and the second via is exposed 352.

It should be noted that the via holes are formed by two etchings on the two gate insulating layers, or may be formed by one etching after the second gate insulating layer 37 is formed.

Sl lb6, a pattern including the data line 21, the source 22, and the drain 23 is formed on the second gate insulating layer 37.

Thus, a TFT array substrate in which the semiconductor active layer is under the gate is formed. Further, the gate electrode 201, the source electrode 22, the drain electrode 23, the semiconductor active layer 34, and the doped semiconductor active layer 36 constitute a TFT.

S12, sequentially depositing a first transparent conductive film and an insulating film on the gate insulating layer, the semiconductor active layer, the data line, the source, and the drain. The first transparent conductive film 25 and the insulating film 26 are deposited on the gate insulating layer 24, the semiconductor active layer 34, the data line 21, the source 22, and the drain 23, respectively. The material of the insulating film 26 may be silicon nitride, and the first transparent conductive film may be an indium tin oxide film having a thickness of 400A.

S13, forming, by a patterning process, a pixel electrode formed by the first transparent conductive film and connected to the drain, located in a pixel electrode region, located in a data line region a data line additional layer formed by the first transparent conductive film, the pixel electrode region, the data line region, the source region, and the drain region covering the pixel electrode, the data line additional layer, the source, and the drain a passivation layer formed of the insulating film; wherein an edge of the pixel electrode is located within a coverage of the passivation layer.

It should be noted that the edge of the pixel electrode is located within the coverage of the passivation layer, which means that the pixel electrode is completely covered by the passivation layer, and the edge thereof is completely retracted into the edge of the passivation layer. This structure can be realized by over-engraving the first transparent conductive film (the film layer forming the pixel electrode). This can effectively prevent the subsequent formation of the common electrode from being short-circuited with the pixel electrode, resulting in a defect.

Moreover, preferably, the edge of the additional layer of the data line after the etching process is also located within the coverage of the passivation layer. This can effectively prevent the subsequently formed common electrode from being short-circuited with the data line through the additional layer of the data line, resulting in a defect.

S14, depositing a second transparent conductive film on the passivation layer, and forming a common electrode having a slit by a patterning process.

For example, the thickness of the second transparent conductive film is greater than the thickness of the first transparent conductive film, i.e., the thickness of the pixel electrode is smaller than the thickness of the common electrode.

It should be noted that, in this embodiment, since the data line additional layer is disposed above the data line, the resistance on the data line can be effectively reduced, and the product quality is improved; and, in the data pad area (Pad area), the data line is attached. The layer can function to protect the data lines (specifically, the data line leads). Moreover, in the present embodiment, the thickness of the pixel electrode is smaller than the thickness of the common electrode, so as to ensure that the first transparent conductive film has a thickness of 400 A and the second transparent conductive film has a thickness of 800 A.

Step S13 can be obtained by the following method, as shown in FIG. 4 to FIG. 8.

5131, as shown in FIG. 4, a photoresist 27 is coated on the insulating film 26, and after exposure, development, forming a corresponding data line region, a pixel electrode region, a source region, and a drain region on the insulating film. A photoresist retention region 271, and a photoresist completely removed region exposing the insulating film. That is, a normal mask (monotone mask) is used at this time, instead of a two-tone mask such as a halftone mask or a gray mask.

5132, as shown in FIG. 5, the insulating film 26 of the photoresist completely removed region 271 is etched away by a first etching process, and is formed to include the pixel electrode region, the data line 21 region, The source 22 region and the drain 23 region cover the passivation layer 261 of the first transparent conductive film 25.

S133, as shown in FIG. 6, the exposed first transparent conductive film 251 is etched away by a second etching process to form a data line additional layer 252 located in the data line region and a pixel electrode 253 located in the pixel electrode region. The edge of the pixel electrode 253 is located within the coverage of the passivation layer 261.

For example, the etching process is to control the etching time so that the edge of the pixel electrode 253 is located within the coverage of the passivation layer 261, thereby ensuring that the pixel electrode 253 and the common electrode formed later are not shorted together, thereby ensuring product quality.

S134, as shown in FIG. 7, stripping off the remaining photoresist.

The above is an implementation manner of the embodiment S13, and a common mask is used to implement the patterning process. Of course, the step can also be implemented by other methods, such as using a two-color mask, which is not described herein. Thereafter, as in the prior art, as shown in Fig. 8, a common electrode 28 having slits is formed on the passivation layer 261 by a patterning process.

The above steps S12 and S13 are described by taking the structure of the semiconductor active layer above the gate as an example, and the finally obtained array substrate is as shown in FIG. The structure of the semiconductor active layer under the gate can also be realized by the same fabrication method as described above, and the structure of the finally formed array substrate is as shown in FIG.

It should be noted that the sequence of S133 and S134 may be reversed in the method steps provided by the embodiments of the present invention, because the passivation layer 261 acts as a photoresist for protecting the first transparent conductive film 25, Thus, it is obvious that the same object can be achieved as the above embodiment. Specifically, in the manufacturing process, after the step S11b6, the steps S12 and S14 are performed on the data line, the source, the drain, and the second gate insulating layer, and details are not described herein again. .

The method for manufacturing an array substrate provided by the embodiment of the present invention, after sequentially depositing the first transparent conductive film and the insulating film, forming a pixel electrode and a patterned passivation layer by one patterning process, and etching the processed pixel electrode The edge is located within the range of the passivation layer. Compared with the prior art, the number of mask processes can be reduced during the fabrication process of the array substrate, thereby reducing manufacturing costs, simplifying the process flow, and improving production efficiency.

It should be noted that in the above step S1 la3, the existing manufacturing process can be used, first in the gate A semiconductor thin film is deposited on the edge layer 24, and the semiconductor active layer 34 is formed by one patterning process; a metal thin film is deposited, and a pattern including the data line 21, the source 22, and the drain 23 is formed by one patterning process. This step Sla3 is completed using two patterning processes. In order to further reduce the number of times of the mask process, optionally, the semiconductor active layer of the step S1 la3, the data line, the source and the drain may also be formed by one patterning process, which may be specifically obtained by the following method, as shown in FIG. ~ Figure 16,

Sl la31, a semiconductor film 31 is deposited on the gate insulating layer 24, as shown in FIG.

Sl la32, depositing a second metal film 32 on the semiconductor film 31, as shown in FIG. 11; Sl la33, coating a photoresist 33 on the second metal film 32, masking with a gray mask or a semi-transparent film After the template is exposed and developed, a photoresist completely reserved region 331 corresponding to the data line region, the source region and the drain region, a photoresist semi-reserved region 332 corresponding to the channel region, and exposed are formed on the second metal film. The photoresist of the second metal thin film completely removes the region, as shown in FIG.

Sl la34, etching the second metal film 32 and the semiconductor film 31 in the completely removed region of the photoresist by etching, as shown in FIG.

Sl la35, the photoresist 332 of the photoresist semi-reserved area 332 is removed by ashing, and a portion of the second metal film 321 is exposed, as shown in FIG.

Sl la36 etches the exposed second metal thin film 321 to form a trench 34, as shown in FIG.

Sl la37, the photoresist of the photoresist completely remaining region 331 is stripped off to obtain a pattern including the semiconductor active layer 31, the data line 21, the source 22, and the drain 23, as shown in FIG.

In this way, since the active layer, the data line, the source and the drain are formed by one patterning process, the mask is reduced once, so that only four mask processes are used in the process of manufacturing the array substrate, thereby Further reduce manufacturing costs, simplify process flow, and increase production efficiency.

Referring to FIG. 8 or FIG. 9, the array substrate provided by the embodiment of the present invention includes:

a substrate 20; a gate line, a gate electrode 201, a gate insulating layer, a semiconductor active layer, a data line 21, a source 22, and a drain 23 formed on the substrate 20; and conductive data formed over the data line 21 a line additional layer 252, a pixel electrode 253 formed in the pixel electrode region; wherein the data line additional layer 252 is in the same layer and the same material as the pixel electrode 253; formed on the data line additional layer 252 and the pixel electrode 253 a passivation layer 261 thereon, wherein an edge of the pixel electrode 253 is located Within the coverage of the passivation layer 261; a common electrode 28 formed on the passivation layer 261.

The data line additional layer 252, the pixel electrode 253, and the passivation layer 261 can be processed by one patterning process using a common mask.

The gate line, the gate electrode 201, the gate insulating layer, the semiconductor active layer, the data line 21, the source 22, and the drain 23 formed on the substrate 20 may have a specific structure as shown in FIG. a gate line (not shown) formed on the substrate, a gate electrode 201; a gate insulating layer 24 formed on the substrate 20, the gate line, and the gate electrode 201; formed in the gate insulating layer a semiconductor active layer 31 on the layer 24; a source 22, a drain 23 formed on the semiconductor active layer 31, and a data line 21 formed on the gate insulating layer 24; further, as shown in FIG. The structure may also be a semiconductor active layer 34 and a doped semiconductor active layer 36 formed on the substrate 20; wherein the doped semiconductor active layer 36 is located on both sides of the semiconductor active layer 34. a first gate insulating layer 38 formed on the substrate 20, the semiconductor active layer 34, and the doped semiconductor active layer 36; a gate line formed on the first gate insulating layer 38 (Fig. Not shown in the middle), the gate 201; formed on the gate line (not shown), a second insulating layer 37 on the pole 201; a data line 21, a source 22, and a drain 23 formed on the second gate insulating layer 37; wherein the source 22 passes through the fifth via 35 and the The doped semiconductor active layer 36 on the side of the semiconductor active layer 34 is connected, and the drain 23 passes through the sixth via 35 and the doped semiconductor active layer 36 on the other side of the semiconductor active layer. connection. As shown in FIG. 9, the fifth via 35 is composed of a second via 352 and a fourth via 354, and the sixth via 35 is composed of a first via 351 and a third via 353.

It should be noted that since the data line additional layer 252 is formed over the data line 21, the resistance on the data line can be effectively reduced, and the product quality can be improved.

In the array substrate provided by the embodiment of the present invention, after the first transparent conductive film and the insulating film are sequentially deposited, the pixel electrode and the patterned passivation layer are formed by one patterning process, and the edge of the pixel electrode after the etching process is located. Within the range of the passivation layer, and further, a data line additional layer is formed over the data line. Compared with the prior art, the number of mask processes (ie, the number of mask processes) is reduced during the fabrication of the array substrate, thereby reducing manufacturing. Cost, simplify the process, increase production efficiency, and effectively reduce the resistance on the data line, thereby further improving product quality.

Preferably, the thickness of the pixel electrode is smaller than the thickness of the common electrode, so that the fault of the common electrode and the passivation layer is not damaged, and the product quality is further ensured. Specifically, the pixel electrode may be an indium tin oxide film having a thickness of 400 A, and the common electrode may have a thickness of 800A indium tin oxide film.

In the above embodiment of the array substrate and the method of manufacturing the same, the case where the pixel electrode and the common electrode are formed on the array substrate has been described as an example. However, the array substrate according to an embodiment of the present invention may also not form a common electrode, such as an array substrate of a liquid crystal display device for a vertical electric field mode. Exceptionally, the array substrate according to the present invention can be applied not only to a liquid crystal display panel but also to an organic light emitting display (OLED) or the like.

The embodiment of the invention further provides a display device comprising any one of the above array substrates. The display device may be: a liquid crystal panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc., any product or component having a display function.

The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.

Claims

claims

1. A manufacturing method for an array substrate, including:

Forming a pattern including a gate line, a gate electrode, a gate insulating layer, a semiconductor active layer, a data line, a source electrode and a drain electrode on the substrate;

Deposit a first transparent conductive film and an insulating film sequentially on the gate insulating layer, the semiconductor active layer, the data line, the source electrode and the drain electrode; and

A pixel electrode formed by the first transparent conductive film in the pixel electrode area and connected to the drain electrode is formed through a patterning process. A data line formed by the first transparent conductive film in the data line area is additionally formed. layer, a passivation layer formed by the insulating film located in the pixel electrode area, the data line area, the source area, and the drain area covering the pixel electrode, the data line additional layer, the source electrode, and the drain electrode. passivation layer; wherein, the edge of the pixel electrode is located within the coverage of the passivation layer.

2. The manufacturing method of the array substrate according to claim 1, further comprising: after forming the passivation layer:

A second transparent conductive film is deposited on the passivation layer, and a common electrode with slits is formed through a patterning process.

3. The manufacturing method of an array substrate according to claim 1 or 2, wherein said forming on the substrate includes a gate line, a gate electrode, a gate insulating layer, a semiconductor active layer, a data line, a source electrode and a drain electrode. Graphics include:

Deposit a first metal film on the substrate, and form a pattern including gate lines and gate electrodes through a patterning process;

forming a gate insulating layer on the gate line, the gate electrode and the substrate; and

A pattern including a semiconductor active layer, data lines, source electrodes, and drain electrodes is formed on the gate insulating layer.

4. The manufacturing method of an array substrate according to claim 1 or 2, wherein said forming on the substrate includes a gate line, a gate electrode, a gate insulating layer, a semiconductor active layer, a data line, a source electrode and a drain electrode. Graphics include:

Deposit a semiconductor film on the substrate, and form a pattern including the semiconductor active layer through a patterning process;

A first gate insulating layer is formed on the semiconductor active layer and processed through a patterning process. A first via hole and a second via hole are formed on the first gate insulating layer, wherein the first via hole and the second via hole are respectively located at both ends of the semiconductor active layer and expose the semiconductor active layer. source layer;

Deposit a first metal film on the first gate insulating layer, and form a pattern including gate lines and gate electrodes through a patterning process;

Using the gate as a mask, the semiconductor active layer outside the gate coverage is converted into a doped semiconductor active layer through an ion implantation process;

A second gate insulating layer is formed on the gate line and gate electrode, and a third via hole and a fourth via hole are formed on the second gate insulating layer through a patterning process; wherein, the third via hole The fourth via hole corresponds to the first via hole and exposes the first via hole; the fourth via hole corresponds to the second via hole and exposes the second via hole; and

A pattern including data lines, source electrodes and drain electrodes is formed on the second gate insulating layer.

5. The manufacturing method of an array substrate according to any one of claims 1 to 4, wherein the first transparent conductive film formed by the first transparent conductive film in the pixel electrode region and connected to the drain electrode is formed through a patterning process. Pixel electrode, a data line additional layer formed of the first transparent conductive film located in the data line area, located in the pixel electrode area, data line area, source area, and drain area covering the pixel electrode and the data line The steps of adding a layer, a passivation layer formed by the insulating film to the source electrode and the drain electrode include:

Coat photoresist on the insulating film, and after exposure and development, a photoresist retained area including a corresponding data line area, pixel electrode area, source area, and drain area is formed on the insulating film, and exposed The photoresist completely removed area of the insulating film;

The insulating film in the area where the photoresist is completely removed is etched away through the first etching process to form an area covering the pixel electrode area, the data line area, the source area, and the drain area. The passivation layer of the first transparent conductive film;

Etching away the exposed first transparent conductive film through a second etching process to form an additional layer of data lines located in the data line region and a pixel electrode located in the pixel electrode region; and

Peel off the remaining photoresist.

6. The manufacturing method of an array substrate according to any one of claims 1 to 4, wherein the first transparent conductive film formed by the first transparent conductive film in the pixel electrode region and connected to the drain electrode is formed through a patterning process. Pixel electrode, an additional layer of data line formed by the first transparent conductive film located in the data line area, located in the pixel electrode area, data line area, source area, and drain area The step of covering the pixel electrode, the data line additional layer, the source electrode, and the drain electrode with a passivation layer formed by the insulating film includes:

The insulating film in the area where the photoresist is completely removed is etched away through the first etching process to form an area covering the pixel electrode area, the data line area, the source area, and the drain area. The patterned passivation layer of the first transparent conductive film;

Strip off remaining photoresist; and

Using the passivation layer as a mask, the exposed first transparent conductive film is etched away through a second etching process to form a data line additional layer located in the data line area and a pixel electrode located in the pixel electrode area.

7. The manufacturing method of an array substrate according to claim 3, wherein forming a pattern including a semiconductor active layer, data lines, source electrodes, and drain electrodes on the gate insulating layer includes:

depositing a semiconductor film on the gate insulating layer;

depositing a second metal film on the semiconductor film;

Coat photoresist on the second metal film, use a grayscale mask or a semi-transparent film mask for exposure and development, and then form corresponding data line areas, source areas, and drain electrodes on the second metal film. The photoresist is completely retained in the region, the photoresist is semi-retained in the corresponding channel region, and the photoresist is completely removed in which the second metal film is exposed;

Etch away the second metal film and semiconductor film in the area where the photoresist is completely removed by etching;

Remove the photoresist in the semi-reserved area of the photoresist through ashing treatment to expose part of the second metal film;

Etching the exposed second metal film to form a channel; and

The photoresist in the completely reserved area of the photoresist is peeled off to obtain a pattern including the semiconductor active layer, data lines, source electrodes, and drain electrodes.

8. The method of manufacturing an array substrate according to claim 2, wherein the thickness of the pixel electrode is smaller than the thickness of the common electrode.

9. The method of manufacturing an array substrate according to claim 8, wherein: the pixel electrode The thickness is 400A, and the thickness of the common electrode is 800A.

10. An array substrate, including:

substrate;

Gate lines, gate electrodes, gate insulating layers, semiconductor active layers, data lines, source electrodes and drain electrodes formed on the substrate;

A conductive data line additional layer formed above the data line and a pixel electrode formed in the pixel electrode region, wherein the data line additional layer is in the same layer and has the same material as the pixel electrode; and

A passivation layer is formed on the data line additional layer and the pixel electrode, wherein the edge of the pixel electrode is located within the coverage of the passivation layer.

11. The array substrate according to claim 10, further comprising:

A common electrode is formed on the passivation layer.

12. The array substrate according to claim 10 or 11, wherein,

The gate line and the gate electrode are formed on the substrate;

The gate insulating layer is formed on the substrate, the gate line and the gate electrode;

The semiconductor active layer is formed on the gate insulating layer;

The source electrode and drain electrode are formed on the semiconductor active layer, and the data line is formed on the gate insulating layer.

13. The array substrate according to claim 10 or 11, wherein,

The semiconductor active layer is formed on the substrate and portions on both sides of the semiconductor active layer are doped;

The gate insulating layer includes a first gate insulating layer and a second gate insulating layer;

The first gate insulating layer is formed on the substrate and the semiconductor active layer;

The gate line and gate electrode are formed on the first gate insulating layer;

The second gate insulating layer is formed on the gate line and gate electrode;

The data line, source electrode, and drain electrode are formed on the second gate insulating layer,

Wherein, the source electrode is connected to the doped portion on one side of the semiconductor active layer through a via hole penetrating the first gate insulating layer and the second gate insulating layer, and the drain electrode passes through the third gate insulating layer. A gate insulating layer and a via hole in the second gate insulating layer are connected to the doped portion on the other side of the semiconductor active layer.

14. The array substrate according to claim 11, wherein the thickness of the pixel electrode is smaller than the thickness of the common electrode.

15. The array substrate according to claim 14, wherein the thickness of the pixel electrode is 400A, and the thickness of the common electrode is 800A.

16. A display device, including the array substrate according to any one of claims 10 to 15.