WO2014015628A1

WO2014015628A1 - Array substrate, method for manufacturing same, and display device

Info

Publication number: WO2014015628A1
Application number: PCT/CN2012/086776
Authority: WO
Inventors: 曹占锋; 童晓阳; 姚琪
Original assignee: 京东方科技集团股份有限公司
Priority date: 2012-07-27
Filing date: 2012-12-17
Publication date: 2014-01-30
Also published as: CN102768990B; CN102768990A

Abstract

A method for manufacturing an array substrate, the array substrate and a display device are provided. The method for manufacturing the array substrate comprises the following steps: S1: forming a pattern of a gate electrode (2) and a gate line on an insulating substrate; S2: forming a gate insulating layer (3), an active layer pattern (4), a source/drain (5) and a data line pattern on the substrate after the step S1; and S3: forming a passivation layer pattern and a pixel electrode pattern on the substrate after the step S2 by one-mask process, the pixel electrode pattern being contacted with the source/drain pattern and covering the gate insulating layer (3). The method for manufacturing the array substrate only involves three masks, and only one gray-scale mask is utilized. Therefore, the cost is reduced and the yield rate is increased. The pixel electrode of the array substrate according to the method is directly arranged on the gate insulating layer, so that the array substrate structure is beneficial for improving the transmittance.

Description

Array substrate, manufacturing method thereof, and display device

Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique

With the increasing use of liquid crystals, the production competition of liquid crystal panels is becoming increasingly fierce, and the cost reduction is crucial for liquid crystal production. At present, most of the TFT panel fabrication process is 4mask or 5mask technology (mask process), that is, 4 or 5 exposures and developments are required to meet the requirements. Currently, the TFT manufacturing process is the most expensive, and the longest time is required. Developing exposure, so reducing the number of masks is important for cost reduction. The traditional 3mask process generally uses two grayscale masking techniques, and the reduced grayscale masking technique is helpful for improving production efficiency and product yield. Summary of the invention

Embodiments of the present invention provide a method for fabricating an array substrate, including the following steps:

S1: forming a pattern including a gate electrode and a gate line on the insulating substrate;

S2: forming a gate insulating layer, an active layer pattern, a source/drain pattern, and a data line pattern on the substrate after the step S1;

S3: forming a passivation layer pattern and a pixel electrode pattern by using a mask on the substrate after the step S2, contacting the pixel electrode pattern with the source/drain pattern, and covering the gate insulating layer.

The step S1 specifically includes:

Forming a gate metal film on the transparent insulating substrate;

Coating a photoresist on the gate metal film, and retaining the photoresist in the gate pattern region by exposing and developing the photoresist;

The exposed gate metal film is etched away and the remaining photoresist is stripped to form a pattern including the gate and gate lines.

The step S2 specifically includes:

Forming a gate insulating film, an active layer sequentially on a substrate on which a pattern including a gate electrode and a gate line is formed a thin film and a source/drain metal film, and coating a photoresist on the source/drain metal film;

曝光 Exposing and developing the photoresist with a two-tone mask, leaving the photoresist corresponding to the source region and the drain region and the photoresist corresponding to the channel region, and the thickness of the photoresist corresponding to the channel region is smaller than the source a photoresist corresponding to the polar region and the drain region;

Etching off the exposed source/drain metal film and the active layer film, removing the photoresist corresponding to the channel region by ashing, and etching the source/drain metal film to form a channel;

The remaining photoresist is stripped to form a gate insulating layer, an active layer pattern, a source/drain pattern, and a data line pattern.

The step S3 specifically includes:

Forming a passivation layer film on the substrate forming the gate insulating layer, the active layer pattern, the source/drain pattern, and the data line pattern, and coating the passivation layer film with the first photoresist;

Exposing and developing the first photoresist to form a photoresist completely reserved region and a photoresist completely unretained region, the photoresist does not completely retain a region corresponding to a portion of the drain region and the pixel electrode region, and the photolithography The glue completely reserved area corresponds to an area outside the region where the photoresist is not completely retained;

Removing the passivation layer film in the completely non-retained region of the photoresist by an etching process to expose a portion of the drain and pixel electrode regions;

Forming a pixel electrode metal film, coating a second photoresist on the pixel electrode metal film, and planarizing the second photoresist, corresponding to the gate, source/drain, and blunt The first photoresist is retained above the layer, and the second photoresist over the first photoresist is less than the second photoresist corresponding to the portion of the drain region and the pixel electrode region thickness of;

Performing ashing treatment on the second photoresist to expose a pixel electrode metal layer over the first photoresist, and retaining the second lithography of the partial drain region and the pixel electrode region Removing a pixel electrode metal layer over the first photoresist by an etching process;

The remaining first photoresist and the second photoresist are stripped to form a pixel electrode pattern. The second photoresist is a photoresist having a viscosity in the range of 2 to 4 mPas.

The planarity of the photoresist is planarized by rotating the substrate.

Embodiments of the present invention also provide an array substrate including a gate line formed on an insulating substrate, a gate insulating layer, a data line, and a pixel unit formed between the gate line and the data line, the pixel unit including a thin film transistor and a pixel electrode, the gate insulating layer being over the gate of the gate line and the thin film transistor, the pixel electrode being over the gate insulating layer, and the thin film transistor The drain connection.

Wherein, the array substrate further includes a passivation layer formed on the source/drain and the data line.

Embodiments of the present invention also provide a display device including the above array substrate. DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, and are not intended to limit the present invention. .

1 is a schematic cross-sectional view of a substrate after forming a gate and a gate line through a first mask and etching in an array substrate manufacturing method according to an embodiment of the present invention;

2 is a schematic cross-sectional view showing a substrate in which a gate insulating film, an active layer film, and a source/drain metal film are sequentially deposited on the substrate of FIG. 1;

3 is a schematic cross-sectional view showing a substrate after forming a gate insulating film, an active layer, a source/drain, and a data line through a second mask and etching on the substrate of FIG. 2;

4 is a schematic cross-sectional view showing a substrate on which a passivation layer film is deposited on the basis of the substrate of FIG. 3, and a first photoresist is coated on the passivation layer film;

5 is a schematic cross-sectional view of the substrate after the third mask is formed and etched to form a passivation layer pattern on the basis of the substrate of FIG. 4;

6 is a schematic cross-sectional view showing a substrate on which a pixel electrode metal film is deposited on the basis of the substrate of FIG. 5, and a planarized second photoresist is coated on the pixel electrode metal film;

7 is a schematic cross-sectional view of a substrate after a second photoresist other than a pixel electrode region and a pixel electrode pattern and a source/drain pattern contact region is ashed on the basis of the substrate of FIG. 6;

Figure 8 is a schematic cross-sectional view showing a substrate after etching the exposed metal film of the pixel electrode on the basis of the substrate of Figure 7;

9 is a schematic cross-sectional view of the array substrate finally formed after the remaining first photoresist and the second photoresist are peeled off on the basis of the substrate of FIG. 8;

FIG. 10 is a schematic plan view of an array substrate according to an embodiment of the present invention. detailed description The technical solutions of the embodiments of the present invention will be clearly and completely described in the following with reference to the accompanying drawings. It is apparent that the described embodiments are part of the embodiments of the invention, rather than all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.

Example 1

The method for fabricating an array substrate provided in this embodiment may include the following steps:

Step 1, forming a gate metal film on the glass substrate 1 (which can be formed by sputtering, deposition or spin coating), coating a photoresist on the gate metal film, and performing photolithography through the mask Exposure development of the glue to retain the photoresist in the gate pattern area A, etching away the exposed gate metal film and stripping the remaining photoresist, as shown in FIG. 1, forming the gate 2 and the gate line (in the figure) Gate lines are not shown, and a common electrode is also typically formed).

Step 2: sequentially forming a gate insulating film, an active layer film, and a source/drain metal film on the substrate on which the gate electrode 2 and the gate line are formed (which may be formed by sputtering, deposition or spin coating), as shown in As shown in Fig. 2, a gate insulating film and an active layer film are deposited by plasma enhanced chemical vapor deposition (PECVD), and a source/drain metal film is deposited by sputtering. The photoresist is coated on the source/drain metal film.曝光 Exposing and developing the photoresist with a two-tone mask (gray mask or halftone mask), leaving the photoresist corresponding to the source region B and the drain region C and the photoresist corresponding to the channel region D And the thickness of the photoresist corresponding to the channel region D is smaller than the photoresist corresponding to the source region B and the drain region C. The exposed active layer film and the source/drain metal film are etched away, and the photoresist corresponding to the channel region D is removed by ashing treatment and etched to form a channel. The remaining photoresist is stripped and a gate insulating layer 3, an active layer 4, a source/drain 5, and a data line (not shown) are formed as shown in FIG.

Step 3: forming a passivation layer on the substrate on which the gate insulating layer 3, the active layer 4, the source/drain 5, and the data line are formed by only one mask (which may be formed by sputtering, deposition, or spin coating) The pixel electrode, the specific steps are as follows:

Step 3.1, as shown in FIG. 4, depositing a passivation layer film on the substrate on which the gate insulating layer 3, the active layer 4, the source/drain 5, and the data line are formed, and coating the passivation layer film The first photoresist 100 is overcoated. The first photoresist 100 is exposed and developed by using a mask to form a photoresist completely reserved region and a photoresist completely unretained region, as shown in FIG. 5, in which the photoresist is not retained at all. The region corresponds to a portion of the drain region F (the region where the drain is in contact with the pixel electrode) and the pixel electrode region G, and the photoresist completely reserved region corresponds to a region outside the completely non-retained region of the photoresist, that is, the passivation layer pattern region E . The passivation layer film exposed by the partial drain region F and the pixel electrode region G is etched away, as shown in FIG. 5, such that the drain of the partial drain region F and the gate insulating layer 3 of the pixel electrode region G are exposed. The exposed first passivator 100 is also removed after etching away the exposed passivation film.

Step 3.2, after the substrate after step 3.1, that is, the substrate shown in FIG. 5, a metal film of a pixel electrode is deposited by sputtering deposition, and a second photoresist 200 is coated on the metal film of the pixel electrode. The second photoresist 200 is a fluidity-sensitive photoresist having a viscosity in the range of 2 to 4 mPas, and the second photoresist 200 can be planarized by rotation. The substrate after the planarization of the second photoresist 200 is as shown in FIG. 6. After the planarization of the substrate after step 3.1 (FIG. 5), after planarization, the second lithography over the remaining first photoresist 100 is performed. The thickness of the glue 200 is smaller than the thickness of the second photoresist 200 on the corresponding partial drain region F and the pixel electrode region G.

In step 3.3, the second photoresist 200 is ashed, because the thickness of the second photoresist 200 in the partial drain region F and the pixel electrode region G is greater than the second photoresist 200 above the first photoresist 100. The thickness of the second photoresist 200 capable of retaining a portion of the drain region F and the pixel electrode region G after ashing, thereby graying out the second photoresist 200 over the first photoresist 100, so that the first The pixel electrode metal film over the photoresist 100 is exposed, as shown in FIG. 7, and the exposed metal film of the pixel electrode is etched, as shown in FIG.

Step 3.4, stripping the remaining first photoresist 100 and the second photoresist 200 to form the passivation layer 6 and the pixel electrode 7, and finally forming an array substrate, as shown in FIG.

The above manufacturing process uses only one mask in the step 3 to make the passivation layer and the pixel electrode, and reduces the mask once compared with the prior art, together with the mask in steps 1 and 2, a total of three masks, and only in step 2 There is a grayscale masking technique or a halftone masking technique, which reduces the cost and improves the yield.

Example 2

9 and 10 (FIG. 9 is a cross-sectional view taken along line AA of FIG. 10), which is an array substrate fabricated according to the method described in Embodiment 1, the array substrate comprising: a gate line formed on the glass substrate 1. 8. A gate insulating layer 3, a data line 9 and a pixel unit formed between the gate line 8 and the data line 9. The pixel unit includes a thin film transistor and a pixel electrode 7. The thin film transistor further includes a gate electrode 2 and a gate insulating layer 3. Active layer 4, source/drain 5. The gate insulating layer 3 is located above the gate line 8 and the gate electrode 2. The pixel electrode 7 directly overlies the gate insulating layer 3 and is connected to the source/drain 5 of the thin film transistor. Since the pixel electrode 7 directly covers the gate insulating layer 3, a two-layer structure of a gate insulating layer and a passivation layer is formed between the conventional pixel electrode and the glass substrate, which is advantageous for improving transmittance.

Example 3

Embodiments of the present invention also provide a display device including the array substrate of Embodiment 2 above. The display device can be: a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, and the like, or any display product or component.

The method for fabricating an array substrate according to an embodiment of the present invention achieves the purpose of forming an array substrate by using only three times of masks by combining the passivation layer and the pixel electrode twice, and using only one gray in the entire manufacturing process. Degree mask technology reduces costs and improves yield. The conventional pixel electrode and the glass substrate have two layers of a gate insulating layer and a passivation layer. The pixel electrode of the array substrate fabricated by the method according to the embodiment of the present invention is directly on the gate insulating layer, so the array substrate structure is favorable for improving. Transmittance. The production method includes the following steps:

S3: forming a passivation layer pattern and a pixel electrode pattern by a mask process on the substrate after the step S2, contacting the pixel electrode pattern with the source/drain pattern, and covering the gate insulating layer .

(2) The method of fabricating an array substrate according to (1), wherein the step S1 comprises: forming a gate metal film on the transparent insulating substrate;

(3) The method of fabricating an array substrate according to (1) or (2), wherein the step S2 includes Includes:

Forming a gate insulating layer film, an active layer film, and a source/drain metal film on the substrate forming the pattern including the gate electrode and the gate line, and coating a photoresist on the source/drain metal film;

曝光 Exposing and developing the photoresist with a two-tone mask, leaving the photoresist corresponding to the source region and the drain region and the photoresist corresponding to the channel region, and the thickness of the photoresist corresponding to the channel region is smaller than the source The thickness of the photoresist corresponding to the polar region and the drain region;

The method of fabricating an array substrate according to any one of (1) to (3), wherein the step S3 comprises:

Forming a pixel electrode metal film, coating a second photoresist on the pixel electrode metal film, and planarizing the second photoresist, remaining corresponding to the gate, source/drain The first photoresist of the passivation layer, the second photoresist thickness d above the first photoresist, and the second portion corresponding to the partial drain region and the pixel electrode region The thickness of the photoresist;

The remaining first photoresist and the second photoresist are stripped to form a pixel electrode pattern. (5) The method of fabricating an array substrate according to (4), wherein the second photoresist is a photoresist having a viscosity in the range of 2 to 4 mPas.

(6) The method of fabricating an array substrate according to (5), wherein the substrate is rotated The fluidized photoresist is planarized.

(7) an array substrate comprising: a gate line formed on an insulating substrate, a gate insulating layer, a data line, and a pixel unit formed between the gate line and the data line, the pixel unit including a thin film transistor and a pixel electrode The gate insulating layer is located above the gate line and the gate of the thin film transistor, wherein the pixel electrode is located above the gate insulating layer and is connected to a drain of the thin film transistor.

(8) The array substrate according to (7), wherein the array substrate further includes a passivation layer formed over the source/drain and the data line.

(9) A display device comprising the array substrate according to (7) or (8).

The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.

Claims

claims

1. An array substrate manufacturing method, including the following steps:

S1: Form a pattern including gate electrodes and gate lines on an insulating substrate;

S2: Form a gate insulating layer, active layer pattern, source/drain pattern and data line pattern on the substrate after step S1;

S3: Form a passivation layer pattern and a pixel electrode pattern on the substrate after step S2 through a mask process, so that the pixel electrode pattern is in contact with the source/drain pattern and covers the gate insulating layer .

2. The array substrate manufacturing method according to claim 1, wherein the step S1 includes: forming a gate metal film on the transparent insulating substrate;

Coating photoresist on the gate metal film, and retaining the photoresist in the gate pattern area by exposing and developing the photoresist;

The exposed gate metal film is etched away and the remaining photoresist is peeled off to form a pattern including gate electrodes and gate lines.

3. The array substrate manufacturing method according to claim 1 or 2, wherein the step S2 includes:

Form a gate insulating layer film, an active layer film and a source/drain metal film in sequence on the substrate forming a pattern including a gate electrode and a gate line, and coat the source/drain metal film with photoresist;

Use a two-tone mask to expose and develop the photoresist, retaining the photoresist corresponding to the source and drain regions and the photoresist corresponding to the channel region, and the thickness of the photoresist corresponding to the channel region is smaller than that of the source The thickness of the photoresist corresponding to the electrode region and drain region;

Etch away the exposed source/drain metal film and active layer film, remove the photoresist corresponding to the channel area through ashing treatment, and etch the source/drain metal film to form a channel;

The remaining photoresist is peeled off to form the gate insulation layer, active layer pattern, source/drain pattern and data line pattern.

4. The array substrate manufacturing method according to any one of claims 1 to 3, wherein the step S3 includes:

Form a passivation layer film on the substrate forming the gate insulating layer, active layer pattern, source/drain pattern and data line pattern, and coat the first photoresist on the passivation layer film; The first photoresist is exposed and developed to form an area where the photoresist is completely retained and an area where the photoresist is not retained at all. The area where the photoresist is not retained at all corresponds to part of the drain region and the pixel electrode area. The photolithography The area where the glue is completely retained corresponds to the area other than the area where the photoresist is not retained at all;

The passivation layer film in the area where the photoresist is not retained is removed through an etching process to expose part of the drain electrode and pixel electrode area;

Continue to form a pixel electrode metal film, coat a second photoresist on the pixel electrode metal film, and perform a planarization process on the second photoresist, leaving the corresponding parts of the gate and source/drain electrodes. , the first photoresist of the passivation layer, the thickness d of the second photoresist above the first photoresist, the thickness d of the second photoresist corresponding to the partial drain region and the pixel electrode region. Photoresist thickness;

The second photoresist is ashed to expose the pixel electrode metal layer above the first photoresist, and the second photolithography of the part of the drain region and the pixel electrode region is retained. glue; remove the pixel electrode metal layer above the first photoresist through an etching process;

The remaining first photoresist and the second photoresist are peeled off to form a pixel electrode pattern.

5. The array substrate manufacturing method according to claim 4, wherein the second photoresist is a photoresist with a viscosity in the range of 2 to 4 MPas.

6. The method for manufacturing an array substrate according to claim 5, wherein the fluid photoresist is planarized by rotating the substrate.

7. An array substrate, including a gate line, a gate insulating layer, a data line formed on an insulating substrate, and a pixel unit formed between the gate line and the data line, the pixel unit including a thin film transistor and a pixel electrode, The gate insulating layer is located on the gate line and the gate electrode of the thin film transistor, wherein the pixel electrode is located on the gate insulating layer and connected to the drain electrode of the thin film transistor.

8. The array substrate of claim 7, wherein the array substrate further includes a passivation layer formed on the source/drain electrode and the data line.

9. A display device comprising the array substrate according to claim 7 or 8.