CN102768990A - Array substrate, and manufacturing method and display device of array substrate - Google Patents

Array substrate, and manufacturing method and display device of array substrate Download PDF

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Publication number
CN102768990A
CN102768990A CN2012102655973A CN201210265597A CN102768990A CN 102768990 A CN102768990 A CN 102768990A CN 2012102655973 A CN2012102655973 A CN 2012102655973A CN 201210265597 A CN201210265597 A CN 201210265597A CN 102768990 A CN102768990 A CN 102768990A
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Prior art keywords
photoresist
pixel electrode
source
grid
substrate
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CN2012102655973A
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CN102768990B (en
Inventor
曹占锋
童晓阳
姚琪
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to CN201210265597.3A priority Critical patent/CN102768990B/en
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Priority to PCT/CN2012/086776 priority patent/WO2014015628A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process

Abstract

The invention discloses a manufacturing method for an array substrate and relates to the technical field of display. The manufacturing method comprises the following steps: S1, forming a figure comprising a grid electrode and a grid line on an insulated substrate; S2, forming a grid insulation layer, an active layer figure, a source/drain figure and a data line figure on the substrate after the step S1; and S3, forming a passivation layer figure and a pixel electrode figure on the substrate after the step S2 through masking for one time, and enabling the pixel electrode figure to be in contact with the source/drain figure and to cover the grid insulation layer. The invention also discloses an array substrate and a display device. According to the manufacturing method for the array substrate, the mask technology is used for three times only, and the gray-scale mask technology is used for one time only, so that the cost is reduced, and the yield is increased; and the pixel electrode of the array substrate manufactured by the manufacturing method is directly located on the grid insulation layer, so that the array substrate structure is beneficial for improving the transmittance.

Description

Array base palte and preparation method thereof, display unit
Technical field
The present invention relates to the Display Technique field, particularly a kind of array base palte and preparation method thereof, display unit.
Background technology
Along with the use of liquid crystal more and more widely, so the production of liquid crystal panel competition also is growing more intense, the reduction of cost is most important for liquid crystal is produced.Present most TFT panel manufacture craft is 4mask or 5mask technology (masking process); Promptly need just can reach requirement through 4 times or 5 exposure imagings; And spend maximum in the manufacture craft of TFT at present; What the required time was the longest is exactly the exposure of developing, so the number of times that reduces mask has significance for the reduction of cost.Traditional 3mask technology generally will be used twice gray scale mask technology, and reduces the gray scale mask technology to enhancing productivity and the product yields has certain help.
Summary of the invention
The technical problem that (one) will solve
The technical problem that the present invention will solve is: how to reduce the technology cost that array base palte is made.
(2) technical scheme
For solving the problems of the technologies described above, the invention provides a kind of array base palte manufacture method, may further comprise the steps:
S1: on insulated substrate, form the figure that comprises grid and grid line;
S2: on through the substrate after the step S1, form gate insulation layer, active layer figure, source/drain electrode figure and data wire figure;
S3: on through the substrate after the step S2, form passivation layer figure and pixel electrode figure, said pixel electrode figure is contacted with said source/drain electrode figure, and cover on the said gate insulation layer through a mask.
Wherein, said step S1 specifically comprises:
On said transparent insulation substrate, form one deck grid metallic film;
On said grid metallic film, apply photoresist, and keep the regional photoresist of gate patterns through exposure, development to photoresist;
Etch away the grid metallic film that exposes and peel off remaining photoresist, form the figure that comprises grid and grid line.
Wherein, said step S2 specifically comprises:
Comprise in formation on the substrate of figure of grid and grid line forming gate insulation layer film, active layer film and source-drain electrode metallic film successively, and on said source-drain electrode metallic film, apply photoresist;
Adopt the duotone mask plate that photoresist is carried out exposure imaging, keep corresponding photoresist in source region and drain region and the corresponding photoresist of channel region, and the thickness of the photoresist of channel region correspondence is less than the corresponding photoresist in source region and drain region;
Etch away the source-drain electrode metallic film and the active layer film that expose, remove the corresponding photoresist of said channel region, and metallic film formation raceway groove is leaked in the etching source through ashing treatment;
Peel off remaining photoresist and form gate insulation layer, active layer figure, source/drain electrode figure and data wire figure.
Wherein, said step S3 specifically comprises:
On the substrate that forms gate insulation layer, active layer figure, source/drain electrode figure and data wire figure, form the passivation layer film, and on said passivation layer film, apply first photoresist;
First photoresist is made public, develops; Form complete reserve area of photoresist and photoresist reserve area not fully; Said photoresist is not reserve area counterpart drain region and pixel electrode area fully, and the corresponding said photoresist of the complete reserve area of said photoresist is the zone beyond the reserve area not fully;
Through etching procedure with said photoresist fully not the said passivation layer film in the reserve area remove, to expose part drain electrode and pixel electrode area;
Continue to form the pixel electrode metallic film; And on said pixel electrode metallic film, apply second photoresist; And said second photoresist carried out planarization; Corresponding said grid, source/drain electrode, passivation layer top keep said first photoresist, and the second photoresist thickness of said first photoresist top is less than the thickness of said second photoresist on correspondence said part drain region and the said pixel electrode area;
Said second photoresist is carried out ashing treatment, expose the pixel electrode metal level of said first photoresist top, and keep said second photoresist of said part drain region and said pixel electrode area;
Remove the pixel electrode metal level of said first photoresist top through etching technics;
Peel off said first photoresist and said second photoresist of reservation, to form the pixel electrode figure.
Wherein, said second photoresist is the photoresist of viscosity in 2 ~ 4mpas scope.
Wherein, the mode through rotary plate makes the said mobile photoresist planarization that has.
The present invention also provides a kind of array base palte; Comprise grid line, gate insulation layer, the data wire that is formed on the insulated substrate and be formed on the pixel cell between said grid line and the data wire; Said pixel cell comprises thin-film transistor and pixel electrode; Said gate insulation layer is positioned on the grid of said grid line and said thin-film transistor, and said pixel electrode is positioned on the said gate insulation layer, and is connected with the drain electrode of said thin-film transistor.
Wherein, said array base palte also comprises the passivation layer that is formed on said source/drain electrode and the said data wire.
The present invention also provides a kind of display unit, comprises above-mentioned array base palte.
(3) beneficial effect
Array base palte manufacture method of the present invention is through being merged into passivation layer and twice mask of pixel electrode once; Reach the purpose of only using three mask just can process array base palte; Simultaneously in entire making process, only use the gray scale mask technology one time, reduced cost, improved yields.Have gate insulator and passivation layer two-layer between traditional pixel electrode and glass substrate, the pixel electrode of the array base palte that the inventive method is made is located immediately on the gate insulator, and therefore this array base-plate structure helps improving transmitance.
Description of drawings
Fig. 1 is the schematic cross-section that forms the substrate behind grid and the grid line in the array base palte manufacture method of the embodiment of the invention through mask and etching for the first time;
Fig. 2 is the schematic cross-section of the substrate after depositing gate insulation layer film, active layer film and source-drain electrode metallic film successively on the substrate basis of Fig. 1;
Fig. 3 is the schematic cross-section of the substrate after the process mask second time and etching form gate insulation layer film, active layer, source/drain electrode and data wire on the substrate basis of Fig. 2;
Fig. 4 is a deposit passivation layer film on the basis of the substrate of Fig. 3, and the schematic cross-section of the substrate after applying first photoresist on the passivation layer film;
Fig. 5 is the schematic cross-section of the substrate after forming the passivation layer figure through mask and etching for the third time on the basis of the substrate of Fig. 4;
Fig. 6 is a pixel deposition electrode metal film on the basis of the substrate of Fig. 5, and the schematic cross-section of the substrate after applying its planarization second photoresist on the pixel electrode metallic film;
Fig. 7 is the schematic cross-section that melts the substrate behind second photoresist in pixel electrode area and pixel electrode figure and source/the drain electrode figure contact area at ash on the basis of the substrate of Fig. 6;
Fig. 8 is the schematic cross-section of the substrate after etching away the pixel electrode metallic film that exposes on the basis of the substrate of Fig. 7;
Fig. 9 is the schematic cross-section of the final array base palte that forms after peeling off remaining first photoresist and second photoresist on the basis of the substrate of Fig. 8;
Figure 10 is the floor map of the array base palte of the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment, specific embodiments of the invention describes in further detail.Following examples are used to explain the present invention, but are not used for limiting scope of the present invention.
Embodiment 1
The array base palte manufacture method flow process that present embodiment provides is following:
Step 1; On glass substrate 1, form one deck gate metal film (can adopt modes such as sputter, deposition or spin coating to form), on the grid metallic film, apply photoresist, and the exposure imaging of photoresist is kept the photoresist of gate patterns zone A through mask plate; Etch away the grid metallic film that exposes and peel off remaining photoresist; As shown in Figure 1, form grid 2 and grid line (not shown grid line also forms public electrode usually).
Step 2; On the substrate that forms grid 2 and grid line, form (can adopt modes such as sputter, deposition or spin coating to form) gate insulation layer film, active layer film and source-drain electrode metallic film successively; As shown in Figure 2; Concrete through plasma enhanced chemical vapor deposition method (PECVD) deposition gate insulator layer film and active layer film, re-use sputtering sedimentation source-drain electrode metallic film.And on the source-drain electrode metallic film, apply photoresist.Adopt duotone mask plate (tone mask plate or partly transfer mask plate) that photoresist is carried out exposure imaging; Keep corresponding photoresist of source region B and drain region C and the corresponding photoresist of channel region D, and the thickness of the photoresist of channel region D correspondence is less than source region B and the corresponding photoresist of drain region C.Etch away the active layer film and the source-drain electrode metallic film that expose, remove the corresponding photoresist of said channel region D through ashing treatment, and etching forms raceway groove.Peel off remaining photoresist and form gate insulation layer 3, active layer 4, source/drain electrode 5 and data wire (not shown), as shown in Figure 3.
Step 3 only forms (can adopt modes such as sputter, deposition or spin coating to form) passivation layer and pixel electrode through a mask on the substrate that forms gate insulation layer 3, active layer 4, source/drain electrode 5 and data wire, concrete steps are following:
Step 3.1, as shown in Figure 4, on the substrate that forms gate insulation layer 3, active layer 4, source/drain electrode 5 and data wire, pass through PECVD deposit passivation layer film, and on said passivation layer film, apply first photoresist 100.Adopt mask plate that first photoresist 100 is made public, develops; Form complete reserve area of photoresist and photoresist reserve area not fully; As shown in Figure 5; Photoresist not reserve area counterpart drain region F (drain electrode contact with pixel electrode zone) and pixel electrode area G fully wherein, the said photoresist of the complete reserve area correspondence of photoresist be not reserve area zone in addition, i.e. passivation layer graphics field E fully.Etch away the passivation layer film that part drain region F and pixel electrode area G expose, as shown in Figure 5, make the drain electrode of part drain region F and the gate insulation layer 3 of pixel electrode area G come out like this.Also keep first photoresist 100 of falling that do not develop simultaneously after etching away the passivation layer film that exposes.
Step 3.2; Substrate after process step 3.1; Be to adopt sputtering sedimentation to plate one deck pixel electrode metallic film on the substrate shown in Figure 5, and on the pixel electrode metallic film, to apply second photoresist, 200, the second photoresists 200 be flowability photoresist preferably; Its viscosity can make 200 planarizations of second photoresist through rotation in 2 ~ 4mpas scope.Substrate after 200 planarizations of second photoresist is as shown in Figure 6; Because the hierarchical structure of the substrate of step 3.1 back (Fig. 5); After the planarization, second photoresist, 200 thickness above first photoresist 100 that keeps are less than the thickness of second photoresist 200 on counterpart drain region F and the pixel electrode area G.
Step 3.3; Second photoresist 200 is carried out ashing treatment; Because second photoresist 200 at the thickness of part drain region F and the pixel electrode area G thickness greater than second photoresist 200 above first photoresist 100, therefore can make after the ashing can reserve part drain region F and second photoresist 200 of pixel electrode area G, ash melts second photoresist 200 of first photoresist, 100 tops; The pixel electrode metallic film of first photoresist, 100 tops is come out; As shown in Figure 7, and the pixel electrode metallic film that exposes of etching, as shown in Figure 8 after the etching.
Step 3.4 is peeled off first photoresist 100 and second photoresist 200 that remain, to form passivation layer 6 and pixel electrode 7, finally forms array base palte, and is as shown in Figure 9.
When making passivation layer and pixel electrode in step 3, above-mentioned manufacturing process only used one time mask; Reduced mask one time with respect to prior art; Together with the mask in step 1 and the step 2, totally three mask, and gray scale mask technology or partly transfer mask technique once in 2 in steps only; Reduce cost, improved yields.
Embodiment 2
As Fig. 9 and 10 (Fig. 9 be Figure 10 along A-A to profile) shown in; Be the array base palte made according to embodiment 1 described method, this array base palte comprises: comprise grid line 8, gate insulation layer 3, the data wire 9 that is formed on the glass substrate 1 and be formed on grid line 8 and data wire 9 between pixel cell.Pixel cell comprises thin-film transistor and pixel electrode 7.Thin-film transistor also comprises grid 2, gate insulation layer 3, active layer 4, source/drain electrode 5.Gate insulation layer 3 is positioned on grid line 8 and the grid 2, and pixel electrode 7 directly is covered on the gate insulation layer 3, and is connected with the source/drain electrode 5 of thin-film transistor.Because pixel electrode 7 directly is covered on the gate insulation layer 3, with respect to gate insulator and passivation layer double-layer structure are arranged between traditional pixel electrode and glass substrate, helps improving transmitance.
Embodiment 3
The present invention also provides a kind of display unit, and this display unit comprises the array base palte of the foregoing description 2.This display unit can be any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, LCD TV, LCD, DPF, mobile phone, panel computer.
Above execution mode only is used to explain the present invention; And be not limitation of the present invention; The those of ordinary skill in relevant technologies field under the situation that does not break away from the spirit and scope of the present invention, can also be made various variations and modification; Therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.

Claims (9)

1. an array base palte manufacture method is characterized in that, may further comprise the steps:
S1: on insulated substrate, form the figure that comprises grid and grid line;
S2: on through the substrate after the step S1, form gate insulation layer, active layer figure, source/drain electrode figure and data wire figure;
S3: on through the substrate after the step S2, form passivation layer figure and pixel electrode figure, said pixel electrode figure is contacted with said source/drain electrode figure, and cover on the said gate insulation layer through a mask.
2. array base palte manufacture method as claimed in claim 1 is characterized in that, said step S1 specifically comprises:
On said transparent insulation substrate, form one deck grid metallic film;
On said grid metallic film, apply photoresist, and keep the regional photoresist of gate patterns through exposure, development to photoresist;
Etch away the grid metallic film that exposes and peel off remaining photoresist, form the figure that comprises grid and grid line.
3. array base palte manufacture method as claimed in claim 1 is characterized in that, said step S2 specifically comprises:
Comprise in formation on the substrate of figure of grid and grid line forming gate insulation layer film, active layer film and source-drain electrode metallic film successively, and on said source-drain electrode metallic film, apply photoresist;
Adopt the duotone mask plate that photoresist is carried out exposure imaging, keep corresponding photoresist in source region and drain region and the corresponding photoresist of channel region, and the thickness of the photoresist of channel region correspondence is less than the corresponding photoresist in source region and drain region;
Etch away the source-drain electrode metallic film and the active layer film that expose, remove the corresponding photoresist of said channel region, and metallic film formation raceway groove is leaked in the etching source through ashing treatment;
Peel off remaining photoresist and form gate insulation layer, active layer figure, source/drain electrode figure and data wire figure.
4. array base palte manufacture method as claimed in claim 1 is characterized in that, said step S3 specifically comprises:
On the substrate that forms gate insulation layer, active layer figure, source/drain electrode figure and data wire figure, form the passivation layer film, and on said passivation layer film, apply first photoresist;
First photoresist is made public, develops; Form complete reserve area of photoresist and photoresist reserve area not fully; Said photoresist is not reserve area counterpart drain region and pixel electrode area fully, and the corresponding said photoresist of the complete reserve area of said photoresist is the zone beyond the reserve area not fully;
Through etching procedure with said photoresist fully not the said passivation layer film in the reserve area remove, to expose part drain electrode and pixel electrode area;
Continue to form the pixel electrode metallic film; And on said pixel electrode metallic film, apply second photoresist; And said second photoresist carried out planarization; Corresponding said grid, source/drain electrode, passivation layer top keep said first photoresist, and the second photoresist thickness of said first photoresist top is less than the thickness of said second photoresist on correspondence said part drain region and the said pixel electrode area;
Said second photoresist is carried out ashing treatment, expose the pixel electrode metal level of said first photoresist top, and keep said second photoresist of said part drain region and said pixel electrode area;
Remove the pixel electrode metal level of said first photoresist top through etching technics;
Peel off said first photoresist and said second photoresist of reservation, to form the pixel electrode figure.
5. array base palte manufacture method as claimed in claim 4 is characterized in that, said second photoresist is the photoresist of viscosity in 2 ~ 4mpas scope.
6. array base palte manufacture method as claimed in claim 5 is characterized in that, the mode through rotary plate makes the said mobile photoresist planarization that has.
7. array base palte; Comprise grid line, gate insulation layer, the data wire that is formed on the insulated substrate and be formed on the pixel cell between said grid line and the data wire; Said pixel cell comprises thin-film transistor and pixel electrode, and said gate insulation layer is positioned on the grid of said grid line and said thin-film transistor, it is characterized in that; Said pixel electrode is positioned on the said gate insulation layer, and is connected with the drain electrode of said thin-film transistor.
8. array base palte as claimed in claim 1 is characterized in that, said array base palte also comprises the passivation layer that is formed on said source/drain electrode and the said data wire.
9. a display unit is characterized in that, comprises like claim 7 or 8 described array base paltes.
CN201210265597.3A 2012-07-27 2012-07-27 Array substrate, and manufacturing method and display device of array substrate Active CN102768990B (en)

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CN109445193A (en) * 2018-02-13 2019-03-08 京东方科技集团股份有限公司 A kind of display panel of horizontal electric field type, its production method and display device
US11126042B2 (en) 2018-02-13 2021-09-21 Beijing Boe Display Technology Co., Ltd. Horizontal electric field type display panel, method of manufacturing the same, and display device

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