CN102768990B - Array substrate, and manufacturing method and display device of array substrate - Google Patents

Array substrate, and manufacturing method and display device of array substrate Download PDF

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Publication number
CN102768990B
CN102768990B CN201210265597.3A CN201210265597A CN102768990B CN 102768990 B CN102768990 B CN 102768990B CN 201210265597 A CN201210265597 A CN 201210265597A CN 102768990 B CN102768990 B CN 102768990B
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CN
China
Prior art keywords
photoresist
described
pixel electrode
source
grid
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CN201210265597.3A
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Chinese (zh)
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CN102768990A (en
Inventor
曹占锋
童晓阳
姚琪
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京东方科技集团股份有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1288Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F2001/136231Active matrix addressed cells for reducing the number of lithographic steps
    • G02F2001/136236Active matrix addressed cells for reducing the number of lithographic steps using a gray or half tone lithographic process

Abstract

The invention discloses a manufacturing method for an array substrate and relates to the technical field of display. The manufacturing method comprises the following steps: S1, forming a figure comprising a grid electrode and a grid line on an insulated substrate; S2, forming a grid insulation layer, an active layer figure, a source/drain figure and a data line figure on the substrate after the step S1; and S3, forming a passivation layer figure and a pixel electrode figure on the substrate after the step S2 through masking for one time, and enabling the pixel electrode figure to be in contact with the source/drain figure and to cover the grid insulation layer. The invention also discloses an array substrate and a display device. According to the manufacturing method for the array substrate, the mask technology is used for three times only, and the gray-scale mask technology is used for one time only, so that the cost is reduced, and the yield is increased; and the pixel electrode of the array substrate manufactured by the manufacturing method is directly located on the grid insulation layer, so that the array substrate structure is beneficial for improving the transmittance.

Description

Array base palte and preparation method thereof, display unit

Technical field

The present invention relates to Display Technique field, particularly a kind of array base palte and preparation method thereof, display unit.

Background technology

Along with the use of liquid crystal is more and more extensive, therefore the production of liquid crystal panel competition is also growing more intense, and the reduction of cost is most important for Liquid crystal production.Current most TFT panel manufacture craft is 4mask or 5mask technology (masking process), need just can reach requirement by 4 times or 5 exposure imagings, and in the manufacture craft of TFT, spend maximum at present, what the required time was the longest is exactly the exposure of developing, and the number of times that therefore reduces mask is important in inhibiting for the reduction of cost.Traditional 3mask technique generally will be used twice technique of gray-scale mask, has certain help and reduce technique of gray-scale mask to enhancing productivity with product yields.

Summary of the invention

(1) technical problem that will solve

The technical problem to be solved in the present invention is: how to reduce the process costs that array base palte is made.

(2) technical scheme

For solving the problems of the technologies described above, the invention provides a kind of array substrate manufacturing method, comprise the following steps:

S1: form the figure that comprises grid and grid line on insulated substrate;

S2: form gate insulation layer, active layer figure, source/drain electrode figure and data wire figure on the substrate through after step S1;

S3: form passivation layer figure and pixel electrode figure by a mask on the substrate through after step S2, described pixel electrode figure is contacted with described source/drain electrode figure, and cover on described gate insulation layer.

Wherein, described step S1 specifically comprises:

In described transparent insulation substrate, form one deck grid metallic film;

On described grid metallic film, apply photoresist, and by the photoresist in the exposure to photoresist, the reservation gate patterns region of developing;

Etch away the grid metallic film exposing and peel off remaining photoresist, forming the figure that comprises grid and grid line.

Wherein, described step S2 specifically comprises:

Comprise in formation on the substrate of figure of grid and grid line and form successively gate insulation layer film, active layer film and source-drain electrode metallic film, and apply photoresist on described source-drain electrode metallic film;

Adopt duotone mask plate to carry out exposure imaging to photoresist, retain source region and corresponding photoresist and photoresist corresponding to channel region in drain region, and the thickness of photoresist corresponding to channel region is less than photoresist corresponding to source region and drain region;

Etch away the source-drain electrode metallic film and the active layer film that expose, remove through ashing processing the photoresist that described channel region is corresponding, and metallic film formation raceway groove is leaked in etching source;

Peel off remaining photoresist and form gate insulation layer, active layer figure, source/drain electrode figure and data wire figure.

Wherein, described step S3 specifically comprises:

On the substrate that forms gate insulation layer, active layer figure, source/drain electrode figure and data wire figure, form passivation layer film, and apply the first photoresist on described passivation layer film;

The first photoresist is exposed, developed, form the complete reserve area of photoresist and photoresist reserve area not completely, described photoresist not reserve area corresponding part drain region and pixel electrode area completely, the corresponding described photoresist of the complete reserve area of the described photoresist region beyond reserve area not completely;

By etching procedure by described photoresist completely not the described passivation layer film in reserve area remove, to expose part drain electrode and pixel electrode area;

Continue to form pixel electrode metallic film, and apply the second photoresist on described pixel electrode metallic film, and described the second photoresist is carried out to planarization, corresponding described grid, source/drain electrode, passivation layer top retain described the first photoresist, and the second photoresist thickness of described the first photoresist top is less than the thickness of described the second photoresist in corresponding described part drain region and described pixel electrode area;

Described the second photoresist is carried out to ashing processing, expose the pixel electrode metal level of described the first photoresist top, and retain described second photoresist of described part drain region and described pixel electrode area;

Remove the pixel electrode metal level of described the first photoresist top by etching technics;

Peel off described the first photoresist and described second photoresist of reservation, to form pixel electrode figure.

Wherein, described the second photoresist is the photoresist of viscosity within the scope of 2 ~ 4mpas.

Wherein, there is the photoresist planarization of mobility described in making by the mode of rotary plate.

The present invention also provides a kind of array base palte, comprise grid line, gate insulation layer, the data wire being formed on insulated substrate and be formed on the pixel cell between described grid line and data wire, described pixel cell comprises thin-film transistor and pixel electrode, described gate insulation layer is positioned on the grid of described grid line and described thin-film transistor, described pixel electrode is positioned on described gate insulation layer, and is connected with the drain electrode of described thin-film transistor.

Wherein, described array base palte also comprises the passivation layer being formed on described source/drain electrode and described data wire.

The present invention also provides a kind of display unit, comprises above-mentioned array base palte.

(3) beneficial effect

Array substrate manufacturing method of the present invention is by being merged into passivation layer and twice mask of pixel electrode once, reach the object that only uses three mask just can make array base palte, in whole manufacturing process, only use technique of gray-scale mask one time, reduced cost, improved yields simultaneously.Between traditional pixel electrode and glass substrate, have gate insulator and passivation layer two-layer, the pixel electrode of the array base palte that the inventive method is made is located immediately on gate insulator, and therefore this array base-plate structure is conducive to improve transmitance.

Accompanying drawing explanation

Fig. 1 is the schematic cross-section that forms the substrate after grid and grid line in the array substrate manufacturing method of the embodiment of the present invention through mask etching for the first time;

Fig. 2 is the schematic cross-section that deposits successively the substrate after gate insulation layer film, active layer film and source-drain electrode metallic film on the substrate basis of Fig. 1;

Fig. 3 is the schematic cross-section that forms the substrate after gate insulation layer film, active layer, source/drain electrode and data wire on the substrate basis of Fig. 2 through mask for the second time etching;

Fig. 4 is deposit passivation layer film on the basis of the substrate of Fig. 3, and on passivation layer film, applies the schematic cross-section of the substrate after the first photoresist;

Fig. 5 is the schematic cross-section that forms the substrate after passivation layer figure on the basis of the substrate of Fig. 4 through mask for the third time etching;

Fig. 6 is pixel deposition electrode metal film on the basis of the substrate of Fig. 5, and on pixel electrode metallic film, applies the schematic cross-section of the substrate after its planarization second photoresist;

Fig. 7 is the schematic cross-section that ash melts the substrate after the second photoresist except pixel electrode area and pixel electrode figure and source/drain electrode figure contact area on the basis of the substrate of Fig. 6;

Fig. 8 is the schematic cross-section that etches away the substrate after the pixel electrode metallic film exposing on the basis of the substrate of Fig. 7;

Fig. 9 is the schematic cross-section that peels off the array base palte finally forming after remaining the first photoresist and the second photoresist on the basis of the substrate of Fig. 8;

Figure 10 is the floor map of the array base palte of the embodiment of the present invention.

Embodiment

Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples are used for illustrating the present invention, but are not used for limiting the scope of the invention.

Embodiment 1

The array substrate manufacturing method flow process that the present embodiment provides is as follows:

Step 1; on glass substrate 1, form one deck gate metal film (can adopt the modes such as sputter, deposition or spin coating to form); on grid metallic film, apply photoresist; and by mask plate, the exposure imaging of photoresist is retained the photoresist of gate patterns region A; etch away the grid metallic film exposing and peel off remaining photoresist; as shown in Figure 1, form grid 2 and grid line (not shown grid line also forms public electrode conventionally).

Step 2, on the substrate that forms grid 2 and grid line, form successively (can adopt the modes such as sputter, deposition or spin coating to form) gate insulation layer film, active layer film and source-drain electrode metallic film, as shown in Figure 2, concrete by plasma enhanced chemical vapor deposition method (PECVD) deposition gate insulator layer film and active layer film, re-use sputtering sedimentation source-drain electrode metallic film.And apply photoresist on source-drain electrode metallic film.Adopt duotone mask plate (tone mask plate or partly adjust mask plate) to carry out exposure imaging to photoresist, retain source region B and corresponding photoresist and photoresist corresponding to channel region D of drain region C, and the thickness of photoresist corresponding to channel region D is less than source region B and photoresist corresponding to drain region C.Etch away the active layer film and the source-drain electrode metallic film that expose, remove photoresist corresponding to described channel region D through ashing processing, and etching forms raceway groove.Peel off remaining photoresist and form gate insulation layer 3, active layer 4, source/drain electrode 5 and data wire (not shown), as shown in Figure 3.

Step 3 only forms (can adopt the modes such as sputter, deposition or spin coating to form) passivation layer and pixel electrode by a mask on the substrate that forms gate insulation layer 3, active layer 4, source/drain electrode 5 and data wire, and concrete steps are as follows:

Step 3.1 as shown in Figure 4, is passed through PECVD deposit passivation layer film, and on described passivation layer film, is applied the first photoresist 100 on the substrate that forms gate insulation layer 3, active layer 4, source/drain electrode 5 and data wire.Adopt mask plate that the first photoresist 100 is exposed, developed, form the complete reserve area of photoresist and photoresist reserve area not completely, as shown in Figure 5, wherein photoresist not reserve area corresponding part drain region F (drain electrode contact with pixel electrode region) and pixel electrode area G completely, the corresponding described photoresist of the complete reserve area of the photoresist region beyond reserve area not completely, i.e. passivation layer graphics field E.Etch away the passivation layer film that part drain region F and pixel electrode area G expose, as shown in Figure 5, make like this drain electrode of part drain region F and the gate insulation layer 3 of pixel electrode area G come out.After etching away the passivation layer film exposing, also retain first photoresist 100 of falling that do not develop simultaneously.

Step 3.2, through the substrate after step 3.1, be on the substrate shown in Fig. 5, to adopt sputtering sedimentation to plate one deck pixel electrode metallic film, and on pixel electrode metallic film, apply the second photoresist 200, the second photoresist 200 is the good photoresist of mobility, its viscosity, within the scope of 2 ~ 4mpas, can make the second photoresist 200 planarizations by rotation.Substrate after the second photoresist 200 planarizations as shown in Figure 6, due to step 3.1 hierarchical structure of the substrate of (Fig. 5) afterwards, after planarization, the second photoresist 200 thickness above the first photoresist 100 retaining are less than the thickness of the second photoresist 200 on corresponding part drain region F and pixel electrode area G.

Step 3.3, the second photoresist 200 is carried out to ashing processing, because the second photoresist 200 is greater than the thickness of the second photoresist 200 above the first photoresist 100 at the thickness of part drain region F and pixel electrode area G, therefore can make after ashing can reserve part drain region F and the second photoresist 200 of pixel electrode area G, ash melts the second photoresist 200 of the first photoresist 100 tops, the pixel electrode metallic film of the first photoresist 100 tops is come out, as shown in Figure 7, and the pixel electrode metallic film that exposes of etching, after etching as shown in Figure 8.

Step 3.4, peels off the first photoresist 100 and the second photoresist 200 that remain, to form passivation layer 6 and pixel electrode 7, finally forms array base palte, as shown in Figure 9.

When making passivation layer and pixel electrode in step 3, above-mentioned manufacturing process only uses mask one time, reduce mask one time with respect to prior art, together with the mask in step 1 and step 2, totally three mask, and only technique of gray-scale mask or partly adjust mask technique once in 2 in steps, reduce cost, improved yields.

Embodiment 2

As Fig. 9 and 10 (Fig. 9 be Figure 10 along A-A to profile) as shown in, for the array base palte that method according to described in embodiment 1 is made, this array base palte comprises: comprise grid line 8, gate insulation layer 3, the data wire 9 being formed on glass substrate 1 and be formed on grid line 8 and data wire 9 between pixel cell.Pixel cell comprises thin-film transistor and pixel electrode 7.Thin-film transistor also comprises grid 2, gate insulation layer 3, active layer 4, source/drain electrode 5.Gate insulation layer 3 is positioned on grid line 8 and grid 2, and pixel electrode 7 is directly covered on gate insulation layer 3, and is connected with the source/drain electrode 5 of thin-film transistor.Because pixel electrode 7 is directly covered on gate insulation layer 3, with respect to having gate insulator and passivation layer double-layer structure between traditional pixel electrode and glass substrate, be conducive to improve transmitance.

Embodiment 3

The present invention also provides a kind of display unit, and this display unit comprises the array base palte of above-described embodiment 2.This display unit can be: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, LCD TV, liquid crystal display, DPF, mobile phone, panel computer.

Above execution mode is only for illustrating the present invention; and be not limitation of the present invention; the those of ordinary skill in relevant technologies field; without departing from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.

Claims (5)

1. an array substrate manufacturing method, is characterized in that, comprises the following steps:
S1: form the figure that comprises grid and grid line on insulated substrate;
S2: form gate insulation layer, active layer figure, source/drain electrode figure and data wire figure on the substrate through after step S1;
S3: form passivation layer figure and pixel electrode figure by a mask on the substrate through after step S2, described pixel electrode figure is contacted with described source/drain electrode figure, and cover on described gate insulation layer;
Wherein, described step S3 specifically comprises:
On the substrate that forms gate insulation layer, active layer figure, source/drain electrode figure and data wire figure, form passivation layer film, and apply the first photoresist on described passivation layer film;
The first photoresist is exposed, developed, form the complete reserve area of photoresist and photoresist reserve area not completely, described photoresist not reserve area corresponding part drain region and pixel electrode area completely, the corresponding described photoresist of the complete reserve area of the described photoresist region beyond reserve area not completely;
By etching procedure by described photoresist completely not the described passivation layer film in reserve area remove, to expose part drain electrode and pixel electrode area;
Continue to form pixel electrode metallic film, and apply the second photoresist on described pixel electrode metallic film, and described the second photoresist is carried out to planarization, corresponding described grid, source/drain electrode, passivation layer top retain described the first photoresist, and the second photoresist thickness of described the first photoresist top is less than the thickness of described the second photoresist in corresponding described part drain region and described pixel electrode area;
Described the second photoresist is carried out to ashing processing, expose the pixel electrode metal level of described the first photoresist top, and retain described second photoresist of described part drain region and described pixel electrode area;
Remove the pixel electrode metal level of described the first photoresist top by etching technics;
Peel off described the first photoresist and described second photoresist of reservation, to form pixel electrode figure.
2. array substrate manufacturing method as claimed in claim 1, is characterized in that, described step S1 specifically comprises:
On described insulated substrate, form one deck grid metallic film;
On described grid metallic film, apply photoresist, and by the photoresist in the exposure to photoresist, the reservation gate patterns region of developing;
Etch away the grid metallic film exposing and peel off remaining photoresist, forming the figure that comprises grid and grid line.
3. array substrate manufacturing method as claimed in claim 1, is characterized in that, described step S2 specifically comprises:
Comprise in formation on the substrate of figure of grid and grid line and form successively gate insulation layer film, active layer film and source-drain electrode metallic film, and apply photoresist on described source-drain electrode metallic film;
Adopt duotone mask plate to carry out exposure imaging to photoresist, retain source region and corresponding photoresist and photoresist corresponding to channel region in drain region, and the thickness of photoresist corresponding to channel region is less than photoresist corresponding to source region and drain region;
Etch away the source-drain electrode metallic film and the active layer film that expose, remove through ashing processing the photoresist that described channel region is corresponding, and metallic film formation raceway groove is leaked in etching source;
Peel off remaining photoresist and form gate insulation layer, active layer figure, source/drain electrode figure and data wire figure.
4. array substrate manufacturing method as claimed in claim 1, is characterized in that, described the second photoresist is the photoresist of viscosity within the scope of 2~4mpas.
5. array substrate manufacturing method as claimed in claim 4, is characterized in that, makes described the second photoresist planarization by the mode of rotary plate.
CN201210265597.3A 2012-07-27 2012-07-27 Array substrate, and manufacturing method and display device of array substrate CN102768990B (en)

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PCT/CN2012/086776 WO2014015628A1 (en) 2012-07-27 2012-12-17 Array substrate, method for manufacturing same, and display device

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CN102768990B (en) * 2012-07-27 2014-06-25 京东方科技集团股份有限公司 Array substrate, and manufacturing method and display device of array substrate
CN103034049A (en) * 2012-12-13 2013-04-10 京东方科技集团股份有限公司 Method for manufacturing metal wire and array substrate
CN103779232B (en) * 2014-01-28 2016-08-17 北京京东方光电科技有限公司 A kind of manufacture method of thin film transistor (TFT)
CN105206553A (en) * 2015-08-28 2015-12-30 京东方科技集团股份有限公司 Etching device, etching method of electric conduction layer and preparation method of array substrate
CN105914183B (en) 2016-06-22 2019-04-30 深圳市华星光电技术有限公司 The manufacturing method of TFT substrate
CN106847930A (en) * 2017-04-01 2017-06-13 京东方科技集团股份有限公司 Thin film transistor (TFT), array base palte and preparation method

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