WO2013143321A1

WO2013143321A1 - Array substrate and manufacturing method thereof, and display device

Info

Publication number: WO2013143321A1
Application number: PCT/CN2012/086403
Authority: WO
Inventors: 徐传祥; 薛建设; 孙雯雯
Original assignee: 京东方科技集团股份有限公司
Priority date: 2012-03-31
Filing date: 2012-12-12
Publication date: 2013-10-03
Also published as: CN102629608B; CN102629608A

Abstract

An array substrate and a manufacturing method thereof, and a display device. The array substrate comprises a substrate (101), and a thin film transistor, a scan line (111), a data line (112) and a pixel electrode (110) that are formed on the substrate (101). A gate (102) and a source (105) in the thin film transistor are respectively connected to the scan line (111) and the data line (112); and a drain (106) of the thin film transistor is connected to the pixel electrode (110). The array substrate further comprises a black matrix (108). The black matrix (108) is correspondingly arranged with the thin film transistor, the scan line (111) and the data line (112). The black matrix (108) is arranged on the array substrate and is correspondingly arranged with the thin film transistor, the data line (112) and the scan line (111), so that deviation occurring between the black matrix (108) and the thin film transistor of the array substrate, the data line (112) and the scan line (111) is avoided, and the light leakage phenomenon caused by the deviation is solved. Meanwhile, the reduction of the area of the black matrix is facilitated, the opening rate of a display panel is increased, and the brightness of the display panel is improved.

Description

Array substrate, manufacturing method thereof and display device

The present disclosure relates to the field of display technologies, and in particular, to an array substrate, a method of manufacturing the same, and a display device. Background technique

In the field of production of Thin Film Transistor Liquid Crystal Display (TFT-LCD), the aperture ratio of a liquid crystal panel is an important product index. The data lines, scanning lines, and thin film transistors in the liquid crystal panel are usually blocked by a black matrix disposed in the color filter layer, and the black matrix region is not transparent. The aperture ratio of the liquid crystal panel refers to the ratio between the area of the portion through which the light passes and the area of the entire liquid crystal panel. The higher the aperture ratio, the more efficient the light passes. Moreover, the high aperture ratio of the liquid crystal panel is important for improving the clarity, brightness, and energy saving of the liquid crystal panel.

A conventional liquid crystal panel generally includes an array substrate, a color filter substrate, and a liquid crystal layer, and the liquid crystal layer is mounted between the array substrate and the color filter substrate. The color filter substrate comprises a transparent substrate, a black matrix, a color film layer and a common electrode, and the array substrate comprises a substrate, a scan line, a data line, a thin film transistor and a pixel electrode. After the array substrate and the color filter substrate are packaged, the black matrix of the color filter substrate is disposed corresponding to the thin film transistor, the scan line and the data line of the array substrate to block the position of the thin film transistor, the scan line and the data line of the array substrate. Light leaks. However, due to the limitation of equipment precision and process conditions in actual production, the black matrix of the color film substrate and the thin film transistor, the scanning line, and the data line of the array substrate are difficult to accurately correspond, or when the liquid crystal panel is used, the impact of the external force is also It may cause the black matrix of the color filter substrate to deviate from the thin film transistor, the scan line, and the data line of the array substrate, which may cause light leakage. In the prior art, defects in light leakage at the position of the thin film transistor, the scanning line, and the data line on the array substrate can be avoided by increasing the area of the black matrix. However, increasing the area of the black matrix causes the aperture ratio of the liquid crystal panel to decrease, and the display luminance of the liquid crystal panel is low.

Moreover, the display panel such as the OLED display panel or the electronic paper display panel also includes the array substrate of the similar structure described above. When these display panels need to be provided with a black matrix on another substrate disposed opposite to the array substrate, there is also a problem caused by the black matrix mismatch described above. Summary of the invention

An embodiment of the present disclosure provides an array substrate including a substrate, and a thin film transistor, a scan line, a data line, and a pixel electrode formed on the substrate, wherein a gate and a source of the thin film transistor are respectively The scan line is connected to the data line, and the drain of the thin film transistor is connected to the pixel electrode. The array substrate further includes: a black matrix, the black matrix and the thin film transistor, the scan line and the data line Corresponding settings.

In one example, the black matrix and the pixel electrode are staggered and arranged in a complementary manner.

The black matrix is formed over the thin film transistor, the scan line or the data line.

The black matrix is formed under the thin film transistor, the scan line or the data line.

In one example, the array substrate further includes a common electrode, wherein the common electrode is located above or below the pixel electrode, and the upper portion of the common electrode and the pixel electrode is in a slit shape. This is an ADS type array substrate.

In one example, a black matrix can be disposed on the passivation layer. The black matrix is disposed between the passivation layer and the substrate.

The present disclosure also provides a display device including the above array substrate.

The present disclosure also provides a method for fabricating an array substrate, comprising: preparing a thin film transistor, a scan line, a data line, and a pixel electrode on a substrate, wherein the manufacturing method further includes:

A black matrix is prepared over the substrate, and the black matrix is disposed corresponding to the scan line, the data line, and the thin film transistor.

Wherein the preparing the black matrix above the substrate comprises:

Step 1. Depositing a black matrix layer and a photoresist layer on a substrate on which a gate electrode, a gate insulating layer, an active layer, a source/drain electrode, and a data line are formed; wherein, the black matrix layer and the photoresist layer a photoresist material having the same photo-sensing property;

Step 2: patterning the substrate of the step 1 by using a gray tone mask or a halftone mask to obtain via holes, and then ashing to remove the photoresist and the black matrix layer on the pixel electrode region while being on the substrate Retaining a predetermined thickness of the photoresist layer in the remaining positions; and

Step 3. Deposit a transparent conductive layer on the substrate on which the step 2 is completed, and peel off the remaining photoresist layer and the transparent conductive layer thereon by a lift off process to form a pattern of the pixel electrode and expose the black matrix.

In one example, the step 2 includes:

Step 21, using the gray tone mask or the halftone mask to face the black matrix layer and the photoresist layer Exposure and development processes are performed to form a photoresist semi-reserved area, a photoresist complete removal area, and a photoresist completely reserved area, wherein the photoresist semi-reserved area corresponds to the pixel electrode area, and the photoresist complete removal area corresponds to the via hole. a region, a photoresist completely reserved region corresponding to the black matrix layer region, the photoresist in the photoresist semi-reserved region is completely removed and the black matrix layer is retained, and the photoresist completely removes the photoresist and the black matrix in the region Completely removed;

Step 22, etching a passivation layer of the complete removal region of the photoresist to form a pattern of via holes; and step 23, performing ashing treatment on the substrate of the completion step 22, and controlling the ashing processing time to remove the pixel electrode region The black matrix layer simultaneously retains a predetermined thickness of the photoresist layer at the remaining positions of the substrate.

In one example, the black matrix layer and the photoresist layer are each formed of a negative photoresist material. In one example, the method of manufacturing the array substrate further includes:

A common electrode is formed on the substrate on which the step 3 is completed, and the common electrode has a slit shape. The array substrate and the display device provided by the present disclosure avoid the blackness disposed on the color filter substrate in the conventional display device by disposing the black matrix on the array substrate and correspondingly setting the black matrix with the thin film transistor, the scan line and the data line. The deviation between the matrix and the thin film transistor, the data line and the scanning line on the array substrate solves the light leakage phenomenon caused by the above deviation, and also reduces the area of the black matrix, and increases the aperture ratio of the display panel such as the liquid crystal panel. , Improve the brightness of display panels such as LCD panels.

The manufacturing method of the array substrate provided by the present disclosure can be prepared by using a mask process of three times, and the black matrix array substrate is disposed, and the black matrix is matched with the thin film transistor, the scan line and the data line, which not only avoids the setting in the conventional display device. Light leakage caused by deviation between the black matrix on the color filter substrate and the thin film transistor, the data line and the scanning line on the array substrate, which is advantageous for reducing the area of the black matrix, increasing the aperture ratio of the display panel such as the liquid crystal panel, and improving The brightness of the display panel such as the liquid crystal panel also reduces the manufacturing process steps, improves the utilization rate of the exposure machine that restricts the production efficiency, and reduces the production cost. DRAWINGS

In order to more clearly illustrate the technical solutions of the present disclosure or the prior art, the following description of the technical solutions provided in the present disclosure or the drawings used in the prior art description will be briefly introduced. Obviously, the drawings in the following description It is merely an illustration of some specific embodiments of the technical solutions of the present disclosure, and it is also possible for a person of ordinary skill in the art to perform creative work without Other figures are obtained from these figures.

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings to be used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present disclosure, and other drawings can be obtained from those skilled in the art without any creative work.

1 is a top plan view of an embodiment of an array substrate of the present disclosure;

Figure 2 is a cross-sectional view taken along line A-A of Figure 1;

3 is a schematic structural view of an embodiment of a liquid crystal panel of the present disclosure;

4 is a flow chart of an embodiment of a method of fabricating an array substrate of the present disclosure;

5 to 11 are schematic views showing the structure of the device obtained at each stage of a manufacturing method of the array substrate of the present disclosure. detailed description

The technical solutions in the embodiments of the present disclosure are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present disclosure. It is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present disclosure without departing from the inventive scope are the scope of the disclosure.

An embodiment of the present disclosure provides an array substrate, including a substrate, and a thin film transistor, a scan line, a data line, and a pixel electrode formed on the substrate. The gate and the source of the thin film transistor are respectively connected to the scan line and the data line, and the thin film transistor is connected. The drain is connected to the pixel electrode. The array substrate further includes: a black matrix disposed corresponding to the thin film transistor, the scan line, and the data line. The corresponding settings mainly refer to the black matrix covering the thin film transistor, the scan line and the data line. Hereinafter, the array substrate structure of the embodiment of the present disclosure will be specifically described in a typical embodiment.

1 is a plan view of an embodiment of an array substrate according to the present disclosure, and FIG. 2 is a cross-sectional view taken along line AA of FIG. As shown in FIG. 1 and FIG. 2, the array substrate in this embodiment includes a substrate 101, a pixel electrode 110, a scan line 111 and a data line 112, and a thin film transistor including a gate electrode 102, a gate insulating layer 103, and an active layer. 104a, source 105 and drain 106. Specifically, a gate electrode 102, a gate insulating layer 103, an active layer 104a, a source electrode 105, a drain electrode 106, a pixel electrode 110, a scan line 111, and a data line 112 are prepared on the substrate 101; wherein the gate insulating layer 103 covers On the gate electrode 102, the active layer 104a is disposed on the gate insulating layer 103, and the ohmic contact layer 104b may be selectively formed between the active layer 104a and the source 105/drain 106 such that the active layer 104a passes the ohmic Contact layer 104b Connected to the source 105 and the drain 106, respectively, the pixel electrode 110 is connected to the drain 106 through the via 109. The source 105 and the drain 106 may be covered with a protective passivation layer 107, the gate 102 is connected to the scan line 111, and the source 105 is connected to the data line 112. In the array substrate of the present embodiment, a passivation layer 107 above the source 105 and the drain 106 is further covered with a black matrix 108, which is disposed corresponding to the thin film transistor, the scan line 111 and the data line 112. Considering the need to connect the pixel electrodes, the via region of the thin film transistor does not cover the black matrix.

As shown in FIG. 2, the black matrix 108 and the pixel electrode 110 in this embodiment are disposed on the top layer of the array substrate, and the black matrix 108 is located on the adjacent sides of the pixel electrode 110. The projection of the black matrix 108 on the substrate 101 will completely cover the projection of the thin film transistor, the scan line 111 and the data line 112 on the substrate 101, and the black matrix 108 is disposed complementary to the pixel electrode 110, that is, the black matrix 108 and the pixel electrode. The projection patterns on the plane of the substrate 101 are complementary or approximately complementary so that the black matrix 108 can block light leakage in an area other than the pixel electrode 110 without interfering with light transmission of the pixel electrode 110. When the light is incident perpendicular to the substrate 101, the light will exit from the transparent pixel electrode 110, and the light passing through the thin film transistor, the scanning line 111 and the data line 112 will be blocked by the black matrix 108, thereby ensuring that the light is emitted only from the pixel electrode 110. .

As shown in Fig. 1, the I region corresponds to the pixel electrode 110 of the array substrate, the II region corresponds to the via 109 in the passivation layer 107, and the III region corresponds to the black matrix 108 of the array substrate.

In practical applications, the black matrix 108 may be disposed at any position on the substrate 101, that is, the black matrix 108 may be located above the thin film transistor, the scan line or the data line, or may be located in the thin film transistor, the scan Below the line or data line, it is only necessary to ensure that the projection of the black matrix 108 on the substrate 101 will completely cover the projection of the thin film transistor, the scan line 111 and the data line 112 on the substrate 101, avoiding the black matrix 108 and the thin film transistor, the scan line 111 and data line 112 are deviated. Of course, considering the need to connect the pixel electrodes, the via region of the thin film transistor may not cover the black matrix; since the drain metal formed at the bottom of the via hole also has a light blocking effect, the shading effect at the via hole is not affected.

The above embodiment describes a conventional TN mode array substrate. Further, the black matrix arrangement of the present disclosure may also be implemented in an electric field of a mode such as ADS, that is, the array substrate may further include a common electrode, wherein the common electrode is located above or below the pixel electrode, The upper side of the common electrode and the pixel electrode is in the shape of a slit.

Embodiments of the present disclosure also provide a display device using the above array substrate. The display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, and a number Any product or component with a display function such as a photo frame, mobile phone, or tablet. The following is an example of a liquid crystal panel.

3 is a schematic structural view of an embodiment of a liquid crystal panel of the present disclosure. As shown in FIG. 3, the liquid crystal panel of the present embodiment includes an array substrate 10, a color filter substrate 20, and a liquid crystal layer 30, wherein the array substrate 10 uses any of the above array substrates, the black matrix 108 of the array substrate 10, and a thin film transistor, The scan line 111 and the data line 112 are correspondingly arranged. In this embodiment, the array substrate 10 is configured with the structure shown in FIGS. 1 and 2. Since the black matrix layer for preventing light leakage is already disposed on the array substrate 10, black is not required in the color filter substrate 30 in this embodiment. matrix.

In the liquid crystal panel of the embodiment, the black matrix is disposed on the array substrate, and the black matrix is disposed corresponding to the thin film transistor, the scan line and the data line, thereby avoiding the black matrix and the array substrate disposed on the color filter substrate in the conventional display device. The deviation between the thin film transistor, the data line and the scanning line solves the light leakage phenomenon caused by the above deviation, and also helps to reduce the area of the black matrix, increase the aperture ratio of the liquid crystal panel, and improve the brightness of the liquid crystal panel.

The display device provided by the embodiment of the present disclosure, because the black matrix on the array substrate is disposed corresponding to the thin film transistor, the scan line and the data line, avoiding the black matrix being disposed on the color filter substrate in the conventional display device, due to the color film substrate and the array The alignment of the substrate is inaccurate, causing the black matrix to deviate from the thin film transistor, the scan line and the data line on the array substrate, preventing light leakage caused by the above deviation, and also reducing the area of the black matrix, increasing the liquid crystal panel, etc. The aperture ratio of the display panel increases the brightness of the display panel such as the liquid crystal panel.

The present disclosure also provides a method of fabricating an array substrate. The method includes preparing a thin film transistor, a scan line, a data line, a pixel electrode, and a passivation layer on a substrate. The method further includes preparing a black matrix on the array substrate, the black matrix is disposed corresponding to the thin film transistor, the scan line and the data line, and the black matrix may be located on the top layer of the array substrate or at any position between the substrate and the passivation layer. Just make sure that the projection of the black matrix on the substrate completely covers the projection of the thin film transistor, scan lines and data lines on the substrate. When light enters the array substrate, the light at the position of the thin film transistor, scan line, and data line of the array substrate is blocked by the black matrix, so there is no light output. In the liquid crystal panel prepared by using the array substrate, light output can be prevented from passing through the position of the thin film transistor, the scanning line and the data line of the array substrate, thereby solving the light leakage phenomenon of the liquid crystal panel.

4 is a flow chart of an embodiment of a method for fabricating an array substrate of the present disclosure, and FIGS. 5 to 11 are schematic structural views of devices obtained at various stages of a method for fabricating an array substrate of the present disclosure. As shown in FIG. 4, the manufacturing method of the array substrate of this embodiment specifically includes the following steps. Step 401: Prepare a gate on the substrate.

In this step, as shown in FIG. 5 and referring to FIGS. 1 and 2, a metal layer and a photoresist layer are deposited on the substrate 101, and then the gate electrode 102, the scan line 111 and the common electrode are obtained through a mask process (in the figure). Not shown), the mask process includes a photolithography process of exposing and developing the photoresist to form a photoresist pattern of the gate electrode 102, the scan line and the common electrode in the photoresist layer, and then using the photoresist The pattern is used as an etch layer to etch the metal layer to obtain the gate 102, the scan lines, and the common electrode, and then proceeds to step 402.

Step 402, preparing a gate insulating layer, an active layer, a source electrode, and a drain electrode on the substrate on which the above steps are completed.

In this step, as shown in FIG. 6 and referring to FIGS. 1 and 2, a gate insulating layer 103, a semiconductor material layer, a metal layer and a photoresist layer are sequentially deposited on the device for performing the above step 401, and then the photoresist layer is performed. Photolithography to obtain a photoresist pattern, and then etching the semiconductor material layer and the metal layer using the photoresist pattern as a shielding layer to obtain an active layer 104a from the semiconductor material layer, and obtaining a source 105 and a drain from the metal layer. The electrode 106 and the data line 112, wherein the semiconductor material layer can be deposited from a semiconductor material such as a-Si, p-Si, IGZO (In-Ga-Zn-O). In practical applications, in order to increase the ohmic contact of the active layer 140a with the source 105 and the drain 106, ion implantation may be performed on the semiconductor material layer after the deposition of the semiconductor material layer to obtain the ohmic contact layer 104b.

After the gate insulating layer 103, the active layer 104a, the source electrode 105, and the drain electrode 106 are formed on the substrate 101, the process proceeds to step 403.

Step 403, preparing a passivation layer, a black matrix, and a pixel electrode on the substrate on which the above steps are completed. In this step, as shown in FIG. 7, a passivation layer 107, a black matrix 108, and a photoresist layer 119 are sequentially deposited on the device for performing the above steps, wherein the black matrix layer 108 and the photoresist layer 119 have the same Photosensitive material of the photoresist material; preferably, the black matrix 108 and the photoresist layer 119 are both negative photoresist materials, and the unexposed negative photoresist can be removed by the developer.

As shown in Figure 8 and referring to Figure 1, the photoresist layer is covered with a gray mask or a halftone mask.

119 is exposed, the I region on the substrate 101 corresponds to a half-exposure region of the gray tone mask or the halftone mask, the II region corresponds to the unexposed region of the gray tone mask or the halftone mask, and the III region corresponds to the gray The fully exposed area of the mask or halftone mask, after the exposed black matrix 108 and photoresist layer 119 are developed, the photoresist layer 119 on the 1 region is removed but the black matrix layer of the region is removed. 108 is retained, the photoresist layer 119 and the black matrix layer 108 on the II region are completely removed, and the photoresist layer 119 and the black matrix 108 on the III region are retained, thereby obtaining a photoresist layer pattern and black. Matrix layer pattern.

As shown in Fig. 9, the passivation layer 107 is etched using the photoresist layer pattern and the black matrix layer pattern obtained in Fig. 8 as a mask layer to obtain a pattern of via holes 109.

As shown in FIG. 10, the photoresist 119 and the black matrix 108 on the substrate in FIG. 9 are subjected to ashing processing to control the time of the ashing process, and the black matrix 108 on the I region is completely removed, and the III region is simultaneously The photoresist layer 119 is partially removed so that a certain thickness of the photoresist layer 119 remains on the III region.

As shown in Fig. 11, a layer of transparent conductive material 120 is deposited on the device shown in Fig. 10 to prepare a pixel electrode. The transparent conductive material layer 120 may be, for example, indium tin oxide (ITO) or the like. Since the thickness of the black matrix 108 and the photoresist layer 119 on the III region is large, the top of the photoresist layer 119 on the III region is longer from the bottom of the via 109, so a transparent conductive material having a smaller thickness is deposited. At the time of layer 120, the transparent conductive material layer 120 is broken at the sidewall of the via hole 109 near the III region, resulting in the transparent conductive material layer on the I region and the transparent conductive material layer on the III region being independent of each other; The lift off process strips the photoresist layer 119 by stripping off the photoresist layer 119 and the transparent conductive material layer 120 over the photoresist layer 119, and the stripping solution is The black matrix 108 has no peeling effect. In this embodiment, when the photoresist layer 119 on the III region is stripped by the stripping solution, since the transparent conductive material layers on the I region and the III region are independent of each other, the transparent conductive material layer on the photoresist layer 119 on the III region. It will also be separated from the array substrate with the photoresist layer 119, thereby exposing the black matrix 108, and the transparent conductive material layer deposited on the I region forms the pixel electrode 110, thereby obtaining an array substrate including the black matrix 108, the array substrate As shown in Figure 1 or 2.

The above process steps enable the fabrication of a typical TN mode array substrate.

In one example, after the above steps are completed, the method further includes: forming a common electrode on the substrate on which the above steps are completed, the common electrode being slit-shaped. This forms a typical ADS mode array substrate structure. It will be understood by those skilled in the art that the step of forming the common electrode of the ADS may further include the step of forming an insulating layer, which is no different from the prior art. Of course, the step of forming the common electrode can also be arranged between certain steps of the above various steps according to the actual design to form different types of ADS structures.

In a practical application, the black matrix may be disposed at any position between the substrate and the passivation layer, as long as the dielectric constant of the black matrix is ensured to meet the electrical requirements of the array substrate, and details are not described herein.

In this embodiment, a black matrix array substrate can be prepared by three mask processes. (For the TN mode, the ADS mode needs to increase the masking process accordingly.) The black matrix is set corresponding to the thin film transistor, the scanning line and the data line, which not only avoids the black matrix and the array substrate disposed on the color film substrate in the conventional display device. The leakage phenomenon caused by the deviation between the thin film transistor, the data line and the scanning line is beneficial to reducing the area of the black matrix, increasing the aperture ratio of the liquid crystal panel, improving the brightness of the display panel such as the liquid crystal panel, and reducing the preparation. The process steps increase the utilization rate of the exposure machine that restricts the production efficiency and reduce the production cost.

The above embodiments are merely illustrative of the present invention and are not to be construed as limiting the scope of the invention, and various modifications and changes can be made without departing from the spirit and scope of the invention. Equivalent technical solutions are also within the scope of the invention, and the scope of the invention is defined by the claims.

Claims

Claim

An array substrate comprising: a substrate, and a thin film transistor, a scan line, a data line, and a pixel electrode formed on the substrate, wherein a gate and a source of the thin film transistor are respectively connected to the scan line and the data line The drain of the thin film transistor is connected to the pixel electrode, and the array substrate further includes:

a black matrix, the black matrix being disposed corresponding to the thin film transistor, the scan line, and the data line.

The array substrate according to claim 1, wherein the black matrix and the pixel electrode are provided complementarily.

The array substrate according to claim 1 or 2, wherein the black matrix is formed over the thin film transistor, the scan line or the data line.

The array substrate according to any one of claims 1 to 3, wherein the black matrix is formed under the thin film transistor, the scan line or the data line.

The array substrate according to any one of claims 1 to 4, wherein the array substrate further comprises a common electrode, wherein the common electrode is located above or below the pixel electrode, and the common electrode The upper one of the pixel electrodes is in the shape of a slit.

A display device comprising the array substrate according to any one of claims 1 to 5.

7. A method of fabricating an array substrate, comprising: preparing a thin film transistor, a scan line, a data line, and a pixel electrode on a substrate, further comprising:

The method of manufacturing an array substrate according to claim 7, wherein the preparing a black matrix above the substrate comprises:

Step 1. Depositing a black matrix layer and a photoresist layer on a substrate on which a gate electrode, a gate insulating layer, an active layer, a source/drain, and a data line are formed; wherein, the black matrix layer and the photoresist layer a photoresist material having the same photo-sensing property;

Step 2: patterning the substrate of the step 1 by using a gray tone mask or a halftone mask to obtain via holes, and then ashing to remove the photoresist and the black matrix layer on the pixel electrode region while being on the substrate Retaining a photoresist layer of a predetermined thickness in the remaining positions;

Step 3. Deposit a transparent conductive layer on the substrate on which the step 2 is completed, and lift off the ground. The process strips away the remaining photoresist layer and the transparent conductive layer thereon, forming a pattern of pixel electrodes and exposing the black matrix.

The method of manufacturing an array substrate according to claim 8, wherein the step 2 comprises:

Step 21: exposing and developing the black matrix layer and the photoresist layer by using a gray tone mask or a halftone mask to form a photoresist semi-reserved area, a photoresist complete removal area, and a photoresist a complete retention area, wherein the photoresist semi-reserved area corresponds to the pixel electrode area, the photoresist complete removal area corresponds to the via area, the photoresist completely reserved area corresponds to the black matrix layer area, and the photoresist semi-reserved area is light The photoresist is completely removed and the black matrix layer remains, and the photoresist and the black matrix in the photoresist completely removed region are completely removed;

Step 22, etching the passivation layer of the photoresist completely removed region to form a pattern of via holes; Step 23, performing ashing treatment on the substrate completing step 22, and controlling the ashing processing time to remove black on the pixel electrode region The matrix layer, and a photoresist layer of a predetermined thickness is retained at the remaining positions of the substrate.

The method of manufacturing an array substrate according to claim 8, wherein the black matrix layer and the photoresist layer are each formed of a negative photoresist material.

The method of manufacturing an array substrate according to claim 8, further comprising: forming a common electrode on the substrate on which the step 3 is completed, wherein the common electrode is in a slit shape.