WO2013185454A1 - Substrat de réseau, son procédé de fabrication et dispositif d'affichage - Google Patents

Substrat de réseau, son procédé de fabrication et dispositif d'affichage Download PDF

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Publication number
WO2013185454A1
WO2013185454A1 PCT/CN2012/086309 CN2012086309W WO2013185454A1 WO 2013185454 A1 WO2013185454 A1 WO 2013185454A1 CN 2012086309 W CN2012086309 W CN 2012086309W WO 2013185454 A1 WO2013185454 A1 WO 2013185454A1
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WO
WIPO (PCT)
Prior art keywords
area
layer
data line
electrode
gate
Prior art date
Application number
PCT/CN2012/086309
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English (en)
Chinese (zh)
Inventor
黄炜赟
玄明花
高永益
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication of WO2013185454A1 publication Critical patent/WO2013185454A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
  • Advanced Super-Dimensional Field Switching which forms a multi-dimensional electric field by the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer, so that the inside of the liquid crystal cell All the aligned liquid crystal molecules between the slit electrodes and directly above the electrodes can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • Advanced super-dimensional field switching technology can improve the picture quality of TFT-LCD (Thin Film Transistor-Liquid Crystal Display) products with high resolution, high transmittance, low power consumption, wide viewing angle and high Opening ratio, low chromatic aberration, and no push mura.
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • ADS liquid crystal displays Compared with other liquid crystal displays, ADS liquid crystal displays have the advantage of expanding the viewing angle, and occupy an important position in the current flat panel display market.
  • the array substrate and its manufacturing process determine the performance and price of the product.
  • the array substrate is usually fabricated with a mask process of 6 times. Yes, gate mask, semiconductor active layer mask, source drain mask, first indium tin oxide (1 st ITO ) mask, passivation layer mask, second indium tin oxide (2 nd ITO ) mask.
  • Embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a display device. By reducing the number of mask processes, manufacturing costs are reduced, process flow is simplified, and production efficiency is improved.
  • a method of fabricating an array substrate including
  • Forming on the substrate including a gate line, a gate, a gate insulating layer, a semiconductor active layer, a data line, a source Pole and drain patterns;
  • a pixel electrode formed by the first transparent conductive film and connected to the drain, and a data line formed by the first transparent conductive film in the data line region is attached a layer, the pixel electrode region, the data line region, the source region, and the drain region covering the pixel electrode, the data line additional layer, the source, and the drain formed by the insulating film
  • the edge of the pixel electrode is located within the coverage of the passivation layer.
  • the manufacturing method may further deposit a second transparent conductive film on the passivation layer, and form a common electrode having slits by a patterning process.
  • an array substrate including:
  • a pixel electrode formed in the pixel electrode region; wherein the data line additional layer is in the same layer as the pixel electrode and has the same material; formed in the data a line additional layer and a passivation layer on the pixel electrode; wherein an edge of the pixel electrode is located within a coverage of the passivation layer.
  • the array substrate may further include a common electrode formed on the passivation layer.
  • the data line additional layer, the pixel electrode, and the passivation layer can be obtained by a single patterning process using a common mask template.
  • a display device including the array substrate described above.
  • the pixel electrode and the pattern are formed by one patterning process.
  • a passivation layer, and the edge of the etched pixel electrode is located within the range of the passivation layer, which can be in the array compared to the prior art method of fabricating the pixel electrode and the passivation layer by two mask processes.
  • the number of mask processes is reduced during the fabrication of the substrate, thereby reducing manufacturing costs, simplifying the process flow, and improving production efficiency.
  • FIG. 1 is a schematic diagram showing a partial structure of an array substrate according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram showing a partial structure of another array substrate according to an embodiment of the present invention
  • FIG. 3 to FIG. 8 are provided according to an embodiment of the present invention. Schematic diagram of the structure of the array substrate in the process of manufacturing an array substrate;
  • FIG. 9 is a schematic diagram of another array substrate according to an embodiment of the present invention.
  • FIG. 10 to FIG. 16 are schematic diagrams showing the structure of an array substrate in another method of fabricating an array substrate according to an embodiment of the present invention. detailed description
  • Sl l forming a pattern including a gate line, a gate, a gate insulating layer, a semiconductor active layer, a data line, a source, and a drain on the substrate.
  • the step S11 can be specifically implemented by, for example, the following two methods, but is not limited thereto:
  • the first method may include the following steps:
  • the structure of the formed array substrate (partial structure of the array substrate) is as shown in FIG. 1:
  • a gate insulating layer 24 is formed on the gate line, the gate electrode 201, and the substrate 20.
  • the second method may include the following steps:
  • the structure of the formed array substrate (partial structure of the array substrate) is as shown in FIG. 2:
  • a semiconductor thin film is deposited on the substrate 20, and a pattern including the semiconductor active layer 34 is formed by one patterning process.
  • a first gate insulating layer 38 is formed on the semiconductor active layer 34, and a first via 351 and a second via 352 are formed on the first gate insulating layer 38 by one patterning process.
  • the first via 351 and the second via 352 are respectively located at both ends of the semiconductor active layer 34, and the semiconductor active layer 34 is exposed.
  • the semiconductor active layer 34 outside the coverage of the gate electrode 201 is converted into the doped semiconductor active layer 36 by an ion implantation process.
  • a second gate insulating layer 37 is formed on the gate line and the gate electrode 201, and a third via hole 353 and a fourth via hole 354 are formed on the second gate insulating layer 37 by one patterning process.
  • the third via 353 corresponds to the first via 351 and exposes the first via 351; the fourth via 354 corresponds to the second via 352, and the second via is exposed 352.
  • the via holes are formed by two etchings on the two gate insulating layers, or may be formed by one etching after the second gate insulating layer 37 is formed.
  • a TFT array substrate in which the semiconductor active layer is under the gate is formed. Further, the gate electrode 201, the source electrode 22, the drain electrode 23, the semiconductor active layer 34, and the doped semiconductor active layer 36 constitute a TFT.
  • the first transparent conductive film 25 and the insulating film 26 are deposited on the gate insulating layer 24, the semiconductor active layer 34, the data line 21, the source 22, and the drain 23, respectively.
  • the material of the insulating film 26 may be silicon nitride, and the first transparent conductive film may be an indium tin oxide film having a thickness of 400A.
  • the edge of the pixel electrode is located within the coverage of the passivation layer, which means that the pixel electrode is completely covered by the passivation layer, and the edge thereof is completely retracted into the edge of the passivation layer.
  • This structure can be realized by over-engraving the first transparent conductive film (the film layer forming the pixel electrode). This can effectively prevent the subsequent formation of the common electrode from being short-circuited with the pixel electrode, resulting in a defect.
  • the edge of the additional layer of the data line after the etching process is also located within the coverage of the passivation layer. This can effectively prevent the subsequently formed common electrode from being short-circuited with the data line through the additional layer of the data line, resulting in a defect.
  • the thickness of the second transparent conductive film is greater than the thickness of the first transparent conductive film, i.e., the thickness of the pixel electrode is smaller than the thickness of the common electrode.
  • the data line additional layer is disposed above the data line, the resistance on the data line can be effectively reduced, and the product quality is improved; and, in the data pad area (Pad area), the data line is attached.
  • the layer can function to protect the data lines (specifically, the data line leads).
  • the thickness of the pixel electrode is smaller than the thickness of the common electrode, so as to ensure that the first transparent conductive film has a thickness of 400 A and the second transparent conductive film has a thickness of 800 A.
  • Step S13 can be obtained by the following method, as shown in FIG. 4 to FIG. 8.
  • a photoresist 27 is coated on the insulating film 26, and after exposure, development, forming a corresponding data line region, a pixel electrode region, a source region, and a drain region on the insulating film.
  • a photoresist retention region 271, and a photoresist completely removed region exposing the insulating film. That is, a normal mask (monotone mask) is used at this time, instead of a two-tone mask such as a halftone mask or a gray mask.
  • the insulating film 26 of the photoresist completely removed region 271 is etched away by a first etching process, and is formed to include the pixel electrode region, the data line 21 region, The source 22 region and the drain 23 region cover the passivation layer 261 of the first transparent conductive film 25.
  • the exposed first transparent conductive film 251 is etched away by a second etching process to form a data line additional layer 252 located in the data line region and a pixel electrode 253 located in the pixel electrode region.
  • the edge of the pixel electrode 253 is located within the coverage of the passivation layer 261.
  • the etching process is to control the etching time so that the edge of the pixel electrode 253 is located within the coverage of the passivation layer 261, thereby ensuring that the pixel electrode 253 and the common electrode formed later are not shorted together, thereby ensuring product quality.
  • a common mask is used to implement the patterning process.
  • the step can also be implemented by other methods, such as using a two-color mask, which is not described herein.
  • a common electrode 28 having slits is formed on the passivation layer 261 by a patterning process.
  • the above steps S12 and S13 are described by taking the structure of the semiconductor active layer above the gate as an example, and the finally obtained array substrate is as shown in FIG.
  • the structure of the semiconductor active layer under the gate can also be realized by the same fabrication method as described above, and the structure of the finally formed array substrate is as shown in FIG.
  • the method for manufacturing an array substrate provided by the embodiment of the present invention, after sequentially depositing the first transparent conductive film and the insulating film, forming a pixel electrode and a patterned passivation layer by one patterning process, and etching the processed pixel electrode
  • the edge is located within the range of the passivation layer.
  • step S1 la3 the existing manufacturing process can be used, first in the gate A semiconductor thin film is deposited on the edge layer 24, and the semiconductor active layer 34 is formed by one patterning process; a metal thin film is deposited, and a pattern including the data line 21, the source 22, and the drain 23 is formed by one patterning process.
  • This step Sla3 is completed using two patterning processes.
  • the semiconductor active layer of the step S1 la3, the data line, the source and the drain may also be formed by one patterning process, which may be specifically obtained by the following method, as shown in FIG. ⁇ Figure 16,
  • the photoresist 332 of the photoresist semi-reserved area 332 is removed by ashing, and a portion of the second metal film 321 is exposed, as shown in FIG.
  • the photoresist of the photoresist completely remaining region 331 is stripped off to obtain a pattern including the semiconductor active layer 31, the data line 21, the source 22, and the drain 23, as shown in FIG.
  • the mask is reduced once, so that only four mask processes are used in the process of manufacturing the array substrate, thereby Further reduce manufacturing costs, simplify process flow, and increase production efficiency.
  • the array substrate provided by the embodiment of the present invention includes:
  • a substrate 20 a gate line, a gate electrode 201, a gate insulating layer, a semiconductor active layer, a data line 21, a source 22, and a drain 23 formed on the substrate 20; and conductive data formed over the data line 21 a line additional layer 252, a pixel electrode 253 formed in the pixel electrode region; wherein the data line additional layer 252 is in the same layer and the same material as the pixel electrode 253; formed on the data line additional layer 252 and the pixel electrode 253 a passivation layer 261 thereon, wherein an edge of the pixel electrode 253 is located Within the coverage of the passivation layer 261; a common electrode 28 formed on the passivation layer 261.
  • the data line additional layer 252, the pixel electrode 253, and the passivation layer 261 can be processed by one patterning process using a common mask.
  • the gate line, the gate electrode 201, the gate insulating layer, the semiconductor active layer, the data line 21, the source 22, and the drain 23 formed on the substrate 20 may have a specific structure as shown in FIG. a gate line (not shown) formed on the substrate, a gate electrode 201; a gate insulating layer 24 formed on the substrate 20, the gate line, and the gate electrode 201; formed in the gate insulating layer a semiconductor active layer 31 on the layer 24; a source 22, a drain 23 formed on the semiconductor active layer 31, and a data line 21 formed on the gate insulating layer 24; further, as shown in FIG.
  • the structure may also be a semiconductor active layer 34 and a doped semiconductor active layer 36 formed on the substrate 20; wherein the doped semiconductor active layer 36 is located on both sides of the semiconductor active layer 34.
  • a first gate insulating layer 38 formed on the substrate 20, the semiconductor active layer 34, and the doped semiconductor active layer 36; a gate line formed on the first gate insulating layer 38 (Fig.
  • the gate 201 formed on the gate line (not shown), a second insulating layer 37 on the pole 201; a data line 21, a source 22, and a drain 23 formed on the second gate insulating layer 37; wherein the source 22 passes through the fifth via 35 and the The doped semiconductor active layer 36 on the side of the semiconductor active layer 34 is connected, and the drain 23 passes through the sixth via 35 and the doped semiconductor active layer 36 on the other side of the semiconductor active layer. connection.
  • the fifth via 35 is composed of a second via 352 and a fourth via 354, and the sixth via 35 is composed of a first via 351 and a third via 353.
  • the resistance on the data line can be effectively reduced, and the product quality can be improved.
  • the pixel electrode and the patterned passivation layer are formed by one patterning process, and the edge of the pixel electrode after the etching process is located.
  • a data line additional layer is formed over the data line.
  • the thickness of the pixel electrode is smaller than the thickness of the common electrode, so that the fault of the common electrode and the passivation layer is not damaged, and the product quality is further ensured.
  • the pixel electrode may be an indium tin oxide film having a thickness of 400 A
  • the common electrode may have a thickness of 800A indium tin oxide film.
  • the array substrate according to an embodiment of the present invention may also not form a common electrode, such as an array substrate of a liquid crystal display device for a vertical electric field mode.
  • the array substrate according to the present invention can be applied not only to a liquid crystal display panel but also to an organic light emitting display (OLED) or the like.
  • the embodiment of the invention further provides a display device comprising any one of the above array substrates.
  • the display device may be: a liquid crystal panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc., any product or component having a display function.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

L'invention concerne un substrat de réseau, son procédé de fabrication et un dispositif d'affichage. Le procédé de fabrication du substrat de réseau comprend : le dépôt séquentiel d'un premier film mince conducteur transparent (25) et d'un film mince isolant (26) sur une couche d'isolation de grille (24), une couche active de semi-conducteur (34), une ligne de données (21), une source (22) et un drain (23) ; la formation, à travers un procédé de formation de motif, d'une électrode de pixel (253) qui est située dans une région d'électrode de pixel, formée du premier film mince conducteur transparent, et raccordée au drain, une couche supplémentaire de ligne de données (252) qui est située dans une région de ligne de données et formée du premier film mince conducteur transparent, et une couche de passivation (261) qui est située dans la région d'électrode de pixel, la région de ligne de données, une région de source et une région de drain, couvre l'électrode de pixel, la couche supplémentaire de ligne de données, la source et le drain, et est formée du film mince isolant. Le bord de l'électrode de pixel est situé sous la couverture de la couche de passivation.
PCT/CN2012/086309 2012-06-13 2012-12-10 Substrat de réseau, son procédé de fabrication et dispositif d'affichage WO2013185454A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201210195627.8A CN102723309B (zh) 2012-06-13 2012-06-13 一种阵列基板及其制造方法和显示装置
CN201210195627.8 2012-06-13

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CN102723309B (zh) * 2012-06-13 2014-07-02 京东方科技集团股份有限公司 一种阵列基板及其制造方法和显示装置
CN103579104A (zh) * 2012-08-02 2014-02-12 北京京东方光电科技有限公司 阵列基板及其制备方法、显示装置
CN104617040A (zh) * 2015-02-05 2015-05-13 京东方科技集团股份有限公司 一种阵列基板的制作方法、显示基板及显示装置
CN105826328B (zh) * 2016-05-03 2019-03-05 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN106229347B (zh) * 2016-08-24 2019-06-07 武汉华星光电技术有限公司 一种低温多晶硅薄膜晶体管及其制造方法
CN108847408A (zh) * 2018-06-04 2018-11-20 深圳市华星光电技术有限公司 一种tft阵列基板的制造方法及tft阵列基板

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