CN110176429B - Manufacturing method of array substrate, array substrate and display panel - Google Patents
Manufacturing method of array substrate, array substrate and display panel Download PDFInfo
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- CN110176429B CN110176429B CN201910275091.2A CN201910275091A CN110176429B CN 110176429 B CN110176429 B CN 110176429B CN 201910275091 A CN201910275091 A CN 201910275091A CN 110176429 B CN110176429 B CN 110176429B
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- 239000000758 substrate Substances 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 39
- 238000000059 patterning Methods 0.000 claims abstract description 33
- 238000000151 deposition Methods 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 7
- 230000000694 effects Effects 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 238000010586 diagram Methods 0.000 description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- Condensed Matter Physics & Semiconductors (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract
The application discloses a manufacturing method of an array substrate, the array substrate and a display panel, which comprise the following steps: forming a first metal layer and a first insulating layer on a substrate; depositing and patterning an active layer to generate a first active layer and a second active layer; patterning a first insulating layer by using a mask plate of a second insulating layer, wherein a via hole pattern is correspondingly arranged on the mask plate of the second insulating layer, and a second active layer is formed at the position of the mask plate of the second insulating layer, which corresponds to the via hole pattern; depositing and patterning a second metal layer, and forming a channel corresponding to the position of the first active layer; depositing a second insulating layer, and patterning the insulating layer by using a mask plate of the second insulating layer to form a via hole; and depositing and patterning the transparent electrode layer to enable the transparent electrode layer to be connected with the second metal layer through the through hole, and using the mask plate of the second insulating layer twice to achieve the effect of saving cost and save the manufacturing process.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a manufacturing method of an array substrate, and a display panel.
Background
Display panels have been rapidly developed and widely used in recent years. In a TFT-LCD (Thin Film Transistor-Liquid Crystal Display) on the mainstream market, the TFT-LCD includes an array substrate and a color Film substrate, a Thin Film Transistor is formed on the array substrate, the Thin Film Transistor controls the on/off of a pixel electrode, and when the Thin Film Transistor is turned on, the pixel electrode generates a voltage to deflect Liquid Crystal molecules, so as to Display a picture.
In the manufacturing process of the array substrate, since a part of the first metal layer in the non-display region may be exposed and connected to an external circuit, the gate insulating layer on the first metal layer in the corresponding region needs to be etched away, and a mask plate generally needs to be added, which brings higher cost.
Disclosure of Invention
The present application provides a manufacturing method of an array substrate, an array substrate and a display panel, so as to reduce cost.
The application discloses a manufacturing method of an array substrate, which comprises the following steps:
forming a first metal layer and a first insulating layer on a substrate;
depositing and patterning an active layer to generate a first active layer and a second active layer;
patterning the first insulating layer by using a mask plate of the second insulating layer;
depositing and patterning a second metal layer, and forming a channel corresponding to the position of the first active layer;
depositing a second insulating layer, and patterning the second insulating layer by using a mask plate of the second insulating layer to form a through hole;
depositing and patterning the transparent electrode layer to enable the transparent electrode layer to be connected with the second metal layer through the through hole;
the mask plate of the second insulating layer is correspondingly provided with via hole patterns, and the second active layer is formed at the position, corresponding to the via hole patterns, of the mask plate of the second insulating layer.
Optionally, in the step of patterning the first insulating layer by using the mask plate of the second insulating layer, a step of etching the first insulating layer in the binding region is further included.
Optionally, the width of the second active layer is greater than or equal to the width of the via hole.
Optionally, after the step of patterning the first insulating layer using the mask plate of the second insulating layer, a step of etching the second active layer is further included.
The application also discloses an array substrate, which is characterized by comprising: a substrate, and a first metal layer, a first insulating layer, an active layer, a second metal layer, a second insulating layer and a transparent electrode layer sequentially formed on the substrate, wherein the active layer includes: the transparent electrode layer is electrically connected with the second metal layer through the through hole, and the second active layer is arranged at the position corresponding to the through hole.
Optionally, the first active layer and the second active layer are not communicated with each other.
Optionally, the array substrate includes a display area and a non-display area, the non-display area includes a binding area, the first metal layer includes a gate and a first electrode layer, the gate is correspondingly disposed at the position of the channel, the first electrode layer is disposed at the position of the corresponding binding area, and the first electrode layer is exposed.
Optionally, the width of the second active layer is greater than or equal to the width of the via hole.
Optionally, the thickness of the second active layer is smaller than the thickness of the first active layer.
The application also discloses a display panel which comprises the array substrate.
In the scheme, the second active layer is formed at the position, corresponding to the via hole pattern, of the mask plate of the second insulating layer, when the mask plate of the second insulating layer is used for exposing and developing the first insulating layer, the second active layer can be exposed at the position corresponding to the via hole pattern, the first insulating layer which corresponds to a non-display area and needs to be etched can also be exposed, the first insulating layer is etched at the moment, the second active layer is not etched, the first insulating layer at the position of the via hole pattern of the mask plate of the second insulating layer is prevented from being etched through protection of the second active layer, and by utilizing the mask plate of the original second insulating layer, in the whole array substrate manufacturing process, the mask plate of the second insulating layer is used twice, so that the effect of saving the cost is achieved, and meanwhile, the manufacturing process is saved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
fig. 1 is a schematic step diagram illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram illustrating a step of another method for fabricating an array substrate according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram illustrating fabrication of an array substrate according to an embodiment of the present application;
fig. 4 is a schematic step diagram illustrating a method for fabricating an array substrate according to another embodiment of the present disclosure;
fig. 5 is a schematic view of an array substrate according to an embodiment of the present application;
fig. 6 is a schematic diagram of a display panel according to an embodiment of the present application.
10, a display panel; 100. an array substrate; 110. a substrate; 120. a first metal layer; 121. a gate electrode; 122. a first electrode layer; 130. a first insulating layer; 131. a gate insulating layer; 140. an active layer; 141. a first active layer; 142. a second active layer; 150. a second metal layer; 151. a source electrode; 152. a drain electrode; 153. a channel; 160. a second insulating layer; 161. a via hole; 162. an insulating layer; 170. a transparent electrode layer; 200. a display area; 210. a non-display area; 211. a binding region.
Detailed Description
It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.
Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.
Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
The present application is described in detail below with reference to the figures and alternative embodiments.
As shown in fig. 1, as an embodiment of the present application, a method for manufacturing an array substrate is disclosed, which includes the steps of:
s10: depositing a first metal layer on a substrate, and depositing a first insulating layer after patterning the first metal layer;
s20: depositing an active layer, and generating a first active layer and a second active layer after patterning the active layer;
s30: patterning the first insulating layer by using a mask plate of the second insulating layer for the first time;
s40: depositing a second metal layer, patterning the second metal layer, and forming a channel at a position corresponding to the first active layer;
s50: depositing a second insulating layer, and patterning the second insulating layer by using the mask plate of the second insulating layer for the second time to form a through hole;
s60: depositing a transparent electrode layer, and patterning the transparent electrode layer to enable the transparent electrode layer to be connected with the second metal layer through the through hole;
the mask plate of the second insulating layer is correspondingly provided with via hole patterns, and the second active layer is formed at the position of the mask plate of the second insulating layer, which corresponds to the via hole patterns; the second active layer protects the first insulating layer at a position corresponding to the via pattern.
In the manufacturing process of the array substrate, because a part of the first metal layer in the non-display area may be exposed and connected with an external circuit, the first insulating layer on the first metal layer in the corresponding area needs to be etched. The general second insulating layer is also required to be etched in the non-display area corresponding to the area where the first metal layer needs to be exposed, so that the first insulating layer can be etched by utilizing the second insulating layer mask plate. In the scheme, the second active layer is formed at the position, corresponding to the via hole pattern, of the mask plate of the second insulating layer, when the mask plate of the second insulating layer is used for exposing and developing the first insulating layer, the second active layer can be exposed at the position corresponding to the via hole pattern, the first insulating layer which corresponds to a non-display area and needs to be etched can also be exposed, the first insulating layer is etched at the moment, the second active layer is not etched, the first insulating layer at the position of the via hole pattern of the mask plate of the second insulating layer is prevented from being etched through protection of the second active layer, and by utilizing the mask plate of the original second insulating layer, in the whole array substrate manufacturing process, the mask plate of the second insulating layer is used twice, so that the effect of saving the cost is achieved, and meanwhile, the manufacturing process is saved.
The first metal layer of the binding region of the non-display region is often required to be exposed to bind the chip or the circuit board; then, in step S3, the mask of the second insulating layer is patterned to correspond to the bonding region, so that the first insulating layer in the bonding region can be etched away by exposing and developing the mask of the second insulating layer, and the first metal layer in the corresponding region is exposed.
As shown in fig. 2, specifically, when the mask plate of the second insulating layer is used to perform exposure development on the first insulating layer, the method includes the following steps:
s301: depositing photoresist;
s302: exposing and developing the photoresist through a mask plate of the second insulating layer;
s303: and stripping the photoresist.
In step S302, the photoresist corresponding to the position of the via pattern is removed to form a photoresist gap, the position corresponding to the photoresist gap is a bare second active layer, the photoresist corresponding to the bonding region is also removed, and the corresponding bonding region is a bare first insulating layer; due to the existence of the photoresist, the first insulating layer below the photoresist is not etched, the first insulating layer corresponding to the protection of the second active layer is not etched, and only the first insulating layer corresponding to the binding region is etched;
specifically, as shown in fig. 3, the width of the second active layer is greater than or equal to the width of the photoresist gap, so that the second active layer can cover the first insulating layer at the photoresist gap, and the first insulating layer can be effectively prevented from being etched. Of course, the width of the second active layer may be greater than or equal to the width of the via.
In another embodiment, after the step of patterning the first insulating layer using the mask of the second insulating layer, the method further includes a step of etching the second active layer, and the second active layer is etched away to prevent the second active layer from affecting the leakage characteristics of the TFT switch.
As shown in fig. 4, as another specific embodiment of the present application, a method for manufacturing an array substrate is disclosed, which includes the steps of:
s11: depositing a first metal layer on a substrate, and forming a gate and the first metal layer of a binding region after patterning the first metal layer;
s21: depositing a gate insulating layer without patterning the gate insulating layer;
s31: depositing an active layer, and generating a first active layer and a second active layer after patterning the active layer; the first active layer and the second active layer are manufactured in the same process, and the same process does not need to be added with any additional process, so that the cost is reduced, and the time of the manufacture process is shortened; specifically, the material of the active layer may be IGZO (indium gallium zinc oxide), amorphous silicon, polycrystalline silicon, or the like;
s41: patterning the gate insulating layer by using a mask plate of the insulating layer for the first time, wherein via hole patterns are correspondingly arranged on the mask plate of the insulating layer, and the second active layer is formed at the position, corresponding to the via hole patterns, of the mask plate of the insulating layer; the second active layer protects the gate insulating layer corresponding to the position of the via hole pattern; and etching off the gate insulating layer of the bonding region to expose the first metal layer of the corresponding region.
S51: depositing a second metal layer, patterning the second metal layer to form a source electrode and a drain electrode, and forming a channel corresponding to the position of the first active layer;
s61: depositing an insulating layer, and patterning the insulating layer by using a mask plate of the insulating layer for the second time to form a via hole;
s71: and depositing a transparent electrode layer, and patterning the transparent electrode layer to enable the transparent electrode layer to be connected with the drain electrode through the through hole.
The gate insulating layer is a first insulating layer, and the insulating layer is a second insulating layer, but the second insulating layer may also be a flat layer or other insulating layers.
As another embodiment of the present application, as illustrated in fig. 5 to 6, a display panel 10 is disclosed, which includes an array substrate 100. The array substrate 100 may be manufactured by the above method, and the array substrate 100 includes: a substrate 110, and a first metal layer 120, a first insulating layer 130, an active layer 140, a second metal layer 150, a second insulating layer 160, and a transparent electrode layer 170 sequentially formed on the substrate, wherein the active layer 140 includes: the second metal layer 150 includes a source 151 and a drain 152, a channel 153 is formed between the source 151 and the drain 152, a via 161 is formed on the second insulating layer 160, the via 161 is used for electrically connecting the transparent electrode layer 170 and the second metal layer 120, the first active layer 141 corresponds to the channel 153, and the second active layer 142 corresponds to the via 161.
Specifically, the array substrate 100 includes a display region 200 and a non-display region 210, the non-display region 210 includes a binding region 211, the first metal layer 120 includes a gate 141 and a first electrode layer 122, the gate 141 is correspondingly disposed at the position of the channel 153, the first electrode layer 122 is disposed at the position of the binding region 211, and the first electrode layer 122 is exposed at the binding region 211.
Of course, the first active layer 141 and the second active layer 142 are not connected to each other. The first active layer 141 and the second active layer 142 are not communicated with each other, so that the second active layer 142 does not affect the leakage characteristics of the first active layer 141, although it is also possible that the first active layer 141 and the second active layer 142 are communicated with each other.
Specifically, the first active layer 141 and the second active layer 412 are located on the same layer and can be formed in the same process, and no additional process is added, which does not increase the cost; of course, the first active layer 141 and the second active layer 142 may not be located in the same layer, and the materials of the first active layer 141 and the second active layer 142 may be different through different processes; for example, the material of the active layer may be: IGZO (indium gallium zinc oxide), amorphous silicon, polycrystalline silicon and the like, the corresponding first active layer may be IGZO, the second active layer may not be IGZO, and the second active layer may be formed in the same process when the material of the second active layer is the same as that of the first active layer, so that the process is saved and the cost is reduced.
Specifically, the thickness of the second active layer 142 is smaller than that of the first active layer 141, and the second active layer can be manufactured by the same process of a semi-transparent mask plate or by different processes; so as to prevent the second metal layer 150 above the second active layer 142 from being too thin and causing high impedance when the via hole is connected to the transparent electrode layer, which may cause low brightness or non-uniform display of the display panel.
The width of the second active layer 142 may be greater than or equal to the width of the via 161, and during the etching process, the second active layer 142 is greater than or equal to the width of the via 161, so that the first insulating layer 130 under the second active layer 142 can be protected from being etched. Of course, the width of the second active layer 142 cannot be too large, and within twice the width of the via 161, too large a width of the second active layer 142 is too close to the first active layer, which may affect the semiconductor effect of the first active layer, and thus the leakage characteristic of the TFT.
It should be noted that, the limitations of each step in the present disclosure are not considered to limit the order of the steps without affecting the implementation of the specific embodiments, and the steps written in the foregoing may be executed first, or executed later, or even executed simultaneously, and as long as the present disclosure can be implemented, all the steps should be considered as belonging to the protection scope of the present application.
The technical solution of the present application can be widely applied to various display panels, such as a Twisted Nematic (TN) display panel, an In-Plane Switching (IPS) display panel, a Vertical Alignment (VA) display panel, and a Multi-Domain Vertical Alignment (MVA) display panel, and of course, other types of display panels, such as an Organic Light-Emitting Diode (OLED) display panel, can also be applied to the above solution.
The foregoing is a more detailed description of the present application in connection with specific embodiments thereof, and it is not intended that the present application be limited to the specific embodiments thereof. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.
Claims (4)
1. The manufacturing method of the array substrate is characterized by comprising the following steps:
providing a substrate;
forming a first metal layer and a first insulating layer on a substrate;
depositing and patterning an active layer to generate a first active layer and a second active layer;
patterning the first insulating layer by using a mask plate of the second insulating layer;
depositing and patterning a second metal layer, and forming a channel corresponding to the position of the first active layer;
depositing a second insulating layer, and patterning the second insulating layer by using a mask plate of the second insulating layer to form a through hole;
depositing and patterning the transparent electrode layer to enable the transparent electrode layer to be connected with the second metal layer through the through hole;
the mask plate of the second insulating layer is correspondingly provided with via hole patterns, and the second active layer is formed at the position, corresponding to the via hole patterns, of the mask plate of the second insulating layer.
2. The method of claim 1, wherein the patterning of the first insulating layer using the mask of the second insulating layer comprises etching the first insulating layer in the bonding region.
3. The method for manufacturing the array substrate according to claim 1, wherein the width of the second active layer is greater than or equal to the width of the via hole.
4. The method of claim 1, further comprising a step of etching the second active layer after the step of patterning the first insulating layer using the mask of the second insulating layer.
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| CN111106149B (en) * | 2019-12-04 | 2022-07-12 | 武汉华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
| CN113012566A (en) * | 2019-12-19 | 2021-06-22 | 群创光电股份有限公司 | Flexible display device and manufacturing method thereof |
| CN112885847B (en) * | 2021-01-27 | 2023-02-07 | Tcl华星光电技术有限公司 | Display panel and preparation method thereof |
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| CN110176429A (en) | 2019-08-27 |
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