KR101878188B1 - Liquide Crystal Display device having a spacer and a bump pattern, and method for fabricating the same - Google Patents

Abstract

There is provided a liquid crystal display device and a manufacturing method thereof capable of reducing manufacturing time and manufacturing cost. The liquid crystal display device according to the technical idea of the present invention may include a bump pattern positioned on the upper surface of the pixel electrode. In the method of manufacturing a liquid crystal display device according to the technical idea of the present invention, a pixel electrode and a bump pattern can be formed by a single mask pattern.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device including a spacer and a bump pattern,

The present invention relates to a liquid crystal display device including a spacer and a bump pattern for maintaining a gap between liquid crystal layers, and a manufacturing method thereof.

2. Description of the Related Art Generally, electronic devices such as a monitor, a TV, a notebook, a digital camera, and the like include a display device for implementing an image. For example, the display device may include a liquid crystal display device and an organic light emitting display device.

The liquid crystal display device may include a display panel including a liquid crystal and a backlight unit for supplying light to the display panel. For example, the display panel may include a lower array having thin film transistors formed on a lower substrate, an upper array having color filters formed on the upper substrate, and a liquid crystal layer disposed between the lower array and the upper array.

The liquid crystal display may further include a spacer for maintaining a gap between the liquid crystal layers. Since the spacer can be moved by a force externally applied, the liquid crystal display device may further include a bump pattern overlapping the spacer, in order to prevent the orientation film and the like from being damaged by movement of the spacer. For example, the upper array of the liquid crystal display may include a spacer, and the lower array of the liquid crystal display may include a bump pattern overlapping the spacer.

However, in the liquid crystal display device including the spacer and the bump pattern, an etching process using a separate mask pattern is performed in order to form a bump pattern, thereby increasing manufacturing time and manufacturing cost. In addition, the etching process using the mask pattern may cause defects due to misalignment of the mask pattern or the like. Therefore, the liquid crystal display device including the spacer and the bump pattern has a problem that the defect occurrence rate is increased by the process of forming the bump pattern .

SUMMARY OF THE INVENTION The present invention provides a liquid crystal display device and a method of manufacturing the same that can simplify the process of forming a bump pattern.

Another object of the present invention is to provide a liquid crystal display device capable of forming a bump pattern without an etching process using a separate mask pattern and a method of manufacturing the same.

The problems to be solved by the present invention are not limited to the above-mentioned problems. Tasks not mentioned here will be apparent to the ordinarily skilled artisan from the description below.

According to an aspect of the present invention, there is provided a liquid crystal display comprising: a pixel electrode disposed on a lower substrate; A bump pattern positioned on an upper surface of the pixel electrode; And a spacer located on the upper substrate facing the lower substrate and overlapping the bump pattern.

The bump pattern may directly contact the upper surface of the pixel electrode.

And a side surface of the bump pattern may be positioned on the upper surface of the pixel electrode.

The bump pattern may have a bar shape extending in one direction on the upper surface of the pixel electrode.

The liquid crystal display may further include a thin film transistor disposed between the lower substrate and the pixel electrode. The bump pattern may overlap with the thin film transistor.

The liquid crystal display may further include a planarization layer disposed between the thin film transistor and the pixel electrode. The bump pattern may overlap a pixel contact hole that exposes a certain region of the thin film transistor through the planarization film.

The liquid crystal display device includes color filters positioned between the upper substrate and the spacers; And a black matrix positioned between the color filters. The bump pattern may overlap the black matrix.

The horizontal width of the spacer may be smaller than the horizontal width of the black matrix and the horizontal width of the bump pattern.

According to an aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, including: forming a pixel electrode material layer on a lower substrate; Forming an electrode mask pattern including an open area, a first electrode masking area and a second electrode masking area thinner than the first electrode masking area on the pixel electrode using a halftone mask; Forming a pixel electrode by etching the pixel electrode material layer using the electrode mask pattern as an etching mask; And forming the bump pattern on the upper surface of the pixel electrode by removing the second electrode masking region of the electrode mask pattern.

The step of forming the bump pattern may include ashing the electrode mask pattern.

The method of manufacturing a liquid crystal display device includes forming a thin film transistor on the lower substrate; Forming a planarization film on the thin film transistor; And forming a pixel contact hole through the planarization film to expose a first region of the thin film transistor. The pixel electrode material layer may be formed to extend along the surface of the pixel contact hole. The bump pattern may be formed to overlap with the thin film transistor.

The forming of the electrode mask pattern may include forming a first electrode masking region overlapping the pixel contact hole.

The forming of the pixel contact holes may include forming a common electrode material layer on the planarization layer, forming an open region, a first contact masking region, and a first contact masking region on the common electrode material layer using a halftone mask, Forming a first contact mask pattern including a second contact masking region that is thinner than the first contact masking region and etching the common electrode material layer and the planarizing film using the first contact mask pattern as an etching mask, Forming a via hole overlapping the first contact mask pattern; removing the second contact masking area of the first contact mask pattern to expose a certain region of the common electrode material pattern formed by etching the common electrode material layer; Forming a second contact mask pattern on the common electrode material pattern; It may include the step, step and step for removing a predetermined region of the upper protective film to form an upper protective layer which extends along the surface of the via hole on the common electrode to form a common electrode. The second region of the thin film transistor may include the first region of the thin film transistor.

The forming of the second contact mask pattern may include ashing the first contact mask pattern.

The second contact mask pattern may expose the common electrode material pattern located near the via hole.

In the liquid crystal display device and the method of manufacturing the same according to the technical idea of the present invention, the pixel electrode and the bump pattern may be formed in a single mask pattern. Accordingly, in the liquid crystal display device and the manufacturing method thereof according to the technical idea of the present invention, an increase in manufacturing time and manufacturing cost by the bump pattern forming process can be prevented. Further, in the liquid crystal display device and the manufacturing method thereof according to the technical idea of the present invention, it is possible to prevent an increase in the defect occurrence rate due to the step of forming the bump pattern. Therefore, the productivity can be improved in the liquid crystal display device and the manufacturing method thereof according to the technical idea of the present invention.

BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a schematic view showing a plane of a lower array of a display panel of a liquid crystal display according to an embodiment of the present invention; FIG.
2 is an enlarged view of the P region in Fig.
3 is a cross-sectional view of a display panel of a liquid crystal display device taken along lines I-I ', II-II', and III-III 'of FIG.
4 to 6 are views showing a liquid crystal display device according to another embodiment of the present invention, respectively.
7A to 7K are views sequentially illustrating a method of manufacturing a liquid crystal display device according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

In the drawings, the same reference numerals denote the same components throughout the specification. In the drawings, the lengths and the thicknesses of layers or regions may be exaggerated for convenience. In addition, when the first component is described as being on the second component, it is preferable that the first component is located on the upper side in direct contact with the second component, And the third component is located between the second components.

Here, the terms first, second, etc. are used for describing various components and are used for the purpose of distinguishing one component from another component. However, the first component and the second component may be arbitrarily named according to the convenience of the person skilled in the art without departing from the technical idea of the present invention.

It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. For example, an element represented in singular form includes a plurality of elements unless the context clearly dictates a singular number. Also, in the specification of the present invention, the terms such as " comprises "or" having ", and the like, designate the presence of stated features, integers, steps, operations, elements, But do not preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

In addition, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the meaning in the context of the related art and, unless expressly defined in the specification of the present invention, are intended to mean either an ideal or an overly formal meaning It is not interpreted.

(Example)

BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a schematic view showing a plane of a lower array of a display panel of a liquid crystal display according to an embodiment of the present invention; FIG. 2 is an enlarged view of the P region in Fig. 3 is a cross-sectional view of a display panel of a liquid crystal display device taken along lines I-I ', II-II', and III-III 'of FIG.

1 to 3, a display panel of a liquid crystal display according to an exemplary embodiment of the present invention includes a lower array 100, an upper array 200, and a plurality of upper and lower arrays 100, 200, And a liquid crystal layer 300 formed on the substrate. A backlight unit may be located on the outer surface of the lower array 100 or the upper array 200.

The lower array 100 may include a gate line GL and a data line DL intersecting the gate line GL. The lower array 100 may further include a gate pad GP for applying a signal to the gate line GL. The lower array 100 may further include a data pad DP for applying a signal to the data line DL.

The gate pad GP and the data pad DP may have a laminated structure. For example, the gate pad GP may include a lower gate pad electrode 131 and an upper gate pad electrode 181 located on the lower gate pad electrode 131. For example, the data pad DP may include a lower data pad electrode 132 and an upper data pad electrode 182 located on the lower data pad electrode 132.

The lower array 100 may further include a thin film transistor 120 positioned in a pixel area PA defined by the gate line GL and the data line DL. The thin film transistor 120 may be supported by the lower substrate 110. The lower substrate 110 may include an insulating material. For example, the lower substrate 110 may comprise glass or plastic.

The thin film transistor 120 includes a gate electrode 121, a gate insulating film 122 located on the gate electrode 121, a semiconductor pattern 123 located on the gate insulating film 122, a semiconductor pattern 123 A source electrode 124 connected to one side of the semiconductor pattern 123 and a drain electrode 125 connected to the other side of the semiconductor pattern 123. The drain electrode 125 may be spaced apart from the source electrode 124.

The gate electrode 121 may be located near the lower substrate 110. The gate electrode 121 may include a conductive material. For example, the gate electrode 121 may include a metal. The gate electrode 121 may include the same material as the gate line DL. The gate electrode 121 may include the same material as the lower gate pad electrode 131. For example, the gate electrode 121, the gate line DL, and the lower gate pad electrode 131 may be formed at the same time.

The gate electrode 121 may be covered with the gate insulating layer 122. The gate insulating layer 122 may cover the gate line DL and the lower gate pad electrode 131. The gate insulating layer 122 may include an insulating material. The semiconductor pattern 123 may overlap at least a certain region of the gate electrode 121. The semiconductor pattern 123 may be electrically insulated from the gate electrode 121 by the gate insulating layer 122.

The semiconductor pattern 123 may include a semiconductor material. For example, the semiconductor pattern 123 may include amorphous silicon or polycrystalline silicon. For example, the semiconductor pattern 123 may be an oxide semiconductor such as IGZO.

The source electrode 124 and the drain electrode 125 may include a conductive material. For example, the source electrode 124 and the drain electrode 125 may comprise a metal. The gate electrode 121 may include a material different from the source electrode 124 and the drain electrode 125. The drain electrode 125 may include the same material as the source electrode 124. For example, the drain electrode 125 may be formed simultaneously with the source electrode 124.

The source electrode 124 and the drain electrode 125 may include the same material as the data line DL. The source electrode 124 and the drain electrode 125 may include the same material as the lower data pad electrode 132. For example, the source electrode 124, the drain electrode 125, the data line DL, and the lower data pad electrode 132 may be formed at the same time. The data line DL and the lower data pad electrode 132 may be located on the gate insulating layer 122.

The liquid crystal display device according to the embodiment of the present invention is described as including the semiconductor pattern 123 in which the thin film transistor 120 is located on the gate insulating film 122 covering the gate electrode 121. [ However, the liquid crystal display device according to another embodiment of the present invention may include the thin film transistor 120 in which the gate insulating layer 122 and the gate electrode 121 are sequentially stacked on the semiconductor pattern 123.

The liquid crystal display according to the embodiment of the present invention is described as the thin film transistor 120 directly contacting the lower substrate 110. However, the liquid crystal display according to another embodiment of the present invention may further include a buffer layer positioned between the lower substrate 110 and the thin film transistor 120. [ The buffer layer may include an insulating material. For example, the buffer layer may comprise silicon oxide.

The lower protective layer 140 may be located on the thin film transistor 120. The lower protective layer 140 may extend along the gate insulating layer 122. For example, the lower gate pad electrode 131 and the lower data pad electrode 132 may be covered with the lower protective layer 140. The lower protective film 140 may include an insulating material. For example, the lower protective film 140 may include silicon nitride and / or silicon oxide.

The planarization layer 150 may be located on the lower protective layer 140. The planarization layer 150 may remove a level difference caused by the gate line GL, the data line DL, and the TFT 120. For example, the upper surface of the planarization layer 150 may be parallel to the upper surface of the lower substrate 100. The lower gate pad electrode 131 and the lower data pad electrode 132 may not be covered with the planarization layer 150. The planarization layer 150 may include an insulating material. For example, the planarization layer 150 may include an organic insulating material such as photo-acryl.

The planarization layer 150 may include a via hole CH located on the thin film transistor 120. For example, the via hole CH of the planarization layer 150 may overlap a certain region of the drain electrode 125 of the thin film transistor 120.

A common electrode 163, an upper protective layer 170, and a pixel electrode 183 may be sequentially stacked on the planarization layer 150. The upper protective layer 170 and the pixel electrode 183 may extend along the surface of the via hole CH. A liquid crystal display according to an embodiment of the present invention includes a pixel contact hole (not shown) that exposes a certain region of the thin film transistor 120 in the via hole CH through the planarization layer 150 and the upper protective layer 170 170TH). For example, the pixel electrode 183 may be electrically connected to the drain electrode 125 of the thin film transistor 120 through the pixel contact hole 170TH.

The common electrode 163 and the pixel electrode 183 may include a conductive material. For example, the common electrode 163 and the pixel electrode 183 may include a transparent conductive material such as ITO and IZO. The upper protective layer 170 may include an insulating material. For example, the upper protective layer 170 may include silicon nitride and / or silicon oxide. The pixel electrode 183 may be electrically insulated from the common electrode 163 by the upper protective layer 170.

The liquid crystal display device according to the embodiment of the present invention is characterized in that the common electrode 163 is in the plate shape including an opening portion through which the via hole CH is exposed and the pixel electrode 183 is formed on the common electrode 163, Bar. ≪ / RTI > However, in the liquid crystal display according to another embodiment of the present invention, the common electrode 163 may include a slit bar, and the pixel electrode 183 may be a plate.

The liquid crystal display device according to the embodiment of the present invention is described as being formed by stacking the common electrode 163 and the pixel electrode 183. However, in the liquid crystal display device according to another embodiment of the present invention, the common electrode 163 and the pixel electrode 183 may be located on the same layer. For example, the liquid crystal display device according to another embodiment of the present invention may include an IPS type display panel.

A bump pattern 190 may be positioned on the upper surface of the pixel electrode 183. For example, the bump pattern 190 may directly contact the upper surface of the pixel electrode 183. The bump pattern 190 may not overlap the common electrode 163. [ The bump pattern 190 may overlap with the thin film transistor 120. For example, the bump pattern 190 may overlap with the pixel contact hole 170TH.

The horizontal width W1 of the bump pattern 190 may be greater than the horizontal width of the pixel contact hole 170TH. For example, the bump pattern 190 may include a side surface that is vertically aligned with the side surface of the pixel electrode 183. The bump pattern 190 may extend to the inside of the pixel contact hole 170TH. For example, the pixel contact hole 170 TH may be filled with the pixel electrode 183 and the bump pattern 190.

The bump pattern 190 may include an insulating material. For example, the bump pattern 190 may comprise an organic material. The bump pattern 190 may include the same material as the planarization layer 150. The bump pattern 190 may include a photosensitive material. For example, the bump pattern 190 may include a photoresist (PR) material.

In the liquid crystal display device according to the embodiment of the present invention, the bump pattern 190 may overlap with the thin film transistor 120. For example, in the liquid crystal display device according to the embodiment of the present invention, the bump pattern 190 can overlap with the pixel contact hole 170TH. Accordingly, in the liquid crystal display device according to the embodiment of the present invention, the area of the display area due to the bump pattern 190 can be prevented from decreasing. Further, in the liquid crystal display device according to the embodiment of the present invention, the area of the non-display region located between the adjacent display regions by the thin film transistor 120 and the bump pattern 190 can be reduced. Therefore, in the liquid crystal display device according to the embodiment of the present invention, the image quality and sharpness of the image can be improved.

The liquid crystal display device according to the embodiment of the present invention may further include a lower alignment layer positioned on the surface of the lower array 100 including the bump pattern 190. For example, the lower alignment layer may extend along the surface of the upper protective layer 170, the pixel electrode 183, and the bump pattern 190. The lower alignment layer may include polyimide (PI).

The upper array 200 may be located on the upper protective layer 170, the pixel electrode 183 and the bump pattern 190 of the lower array 100. For example, the upper array 200 may include an upper substrate 210, color filters 220, a black matrix 230, and spacers 250.

The upper substrate 210 may support the color filters 220, the black matrix 230, and the spacers 250. The upper substrate 210 may include an insulating material. For example, the upper substrate 210 may comprise glass or plastic.

The color filters 220 may be positioned on the surface of the upper substrate 210 toward the lower array 100. Different colors may be implemented by the color filters 220 in adjacent pixel areas PA of the lower array 100. For example, adjacent color filters 220 may comprise different materials.

The black matrix 230 can prevent color mixture and light leakage in the adjacent pixel region PA. The black matrix 230 may be located between the color filters 220. For example, the black matrix 230 may overlap a boundary between neighboring pixel regions PA of the lower array 100. For example,

The black matrix 230 may be positioned on the thin film transistor 120. The bump pattern 190 may overlap the black matrix 230. Accordingly, in the liquid crystal display device according to the embodiment of the present invention, the area of the non-display area located between adjacent display areas by the bump pattern 190 and the black matrix 230 can be reduced. Therefore, in the liquid crystal display device according to the embodiment of the present invention, the image quality and sharpness of the implemented image can be improved.

The spacer 250 may be positioned on the bump pattern 190. For example, the lower surface of the spacer 250 may be in direct contact with the upper surface of the bump pattern 190. The gap between the liquid crystal layer 300 located between the lower array 100 and the upper array 200 is maintained by the bump pattern 190 and the spacer 250 in the liquid crystal display device according to the embodiment of the present invention . Accordingly, in the liquid crystal display device according to the embodiment of the present invention, the movement of the spacer 250 can prevent damage to the lower alignment layer located on the display area.

The spacer 250 may overlap the black matrix 230. For example, the spacer 250 may be positioned between the bump pattern 190 and the black matrix 230. The horizontal width W3 of the end of the spacer 250 located closer to the upper substrate 210 may be smaller than the horizontal width W4 of the black matrix 230. [ The horizontal width W2 of the end of the spacer 250 located closer to the lower substrate 110 may be smaller than the horizontal width W1 of the bump pattern 190. [ The horizontal width W1 of the bump pattern 190 may be greater than the horizontal width W3 of the end portion of the spacer 250 that is located closer to the upper substrate 210. [ Accordingly, in the liquid crystal display device according to the embodiment of the present invention, the area of the non-display area located between adjacent display areas can be reduced. Therefore, in the liquid crystal display device according to the embodiment of the present invention, the image quality and sharpness of the implemented image can be improved.

The liquid crystal display device according to the embodiment of the present invention may further include an upper cover film 240 covering the surface of the color filters 220 toward the lower array 100. The upper cover film 240 may include an insulating material. The spacer 250 may be positioned on the upper cover film 240.

The liquid crystal display device according to the embodiment of the present invention is described as the side surface of the bump pattern 190 being continuous with the side surface of the pixel electrode 183. However, as shown in FIG. 4, the liquid crystal display according to another embodiment of the present invention may have a side surface of the bump pattern 190 on the upper surface of the pixel electrode 183.

The liquid crystal display device according to the embodiment of the present invention is described as the case where the bump pattern 190 overlaps the pixel contact hole 170TH. However, as shown in FIG. 5, in the liquid crystal display according to another embodiment of the present invention, the bump pattern 190 may be spaced apart from the pixel contact hole 170TH.

The liquid crystal display device according to the embodiment of the present invention is shown and described as having the bump pattern 190 in a circular shape. However, in the liquid crystal display device according to another embodiment of the present invention, the bump pattern 190 may have a polygonal shape. 6, a liquid crystal display device according to another embodiment of the present invention includes a bump pattern 190 formed on a top surface of a pixel electrode 183 in a bar shape extending in one direction. . For example, a liquid crystal display device according to another embodiment of the present invention may include a pixel contact hole 170TH or a bump pattern 190 crossing a via hole CH.

7A to 7K are views sequentially illustrating a method of manufacturing a liquid crystal display device according to an embodiment of the present invention.

A method of manufacturing a liquid crystal display device according to an embodiment of the present invention will be described with reference to Figs. 1 to 3 and 7a to 7k. 1 and 7A, a method of manufacturing a liquid crystal display according to an embodiment of the present invention includes forming a thin film transistor 120, a lower gate pad electrode 131, a gate line GL on a lower substrate 110, , A lower data pad electrode 132, and a data line (DL).

The thin film transistor 120 may include a gate electrode 121, a gate insulating film 122, a semiconductor pattern 123, a source electrode 124, and a drain electrode 125. For example, the step of forming the thin film transistor 120 may include forming a gate electrode 121 on the lower substrate 110, forming a gate insulating film 122 on the gate electrode 121, A step of forming a semiconductor pattern 123 on the gate insulating layer 122 and a step of forming a source electrode 124 and a drain electrode 125 on the semiconductor pattern 123. [ The source electrode 124 and the drain electrode 125 may be spaced apart from each other.

A method of manufacturing a liquid crystal display device according to an embodiment of the present invention is described as forming a thin film transistor 120 in which a semiconductor pattern 123 is located on a gate insulating film 122 covering a gate electrode 121. However, in the method of manufacturing a liquid crystal display device according to another embodiment of the present invention, a thin film transistor 120 may be formed on a semiconductor pattern 123, in which a gate insulating film 122 and a gate electrode 121 are sequentially stacked .

A method of manufacturing a liquid crystal display device according to an embodiment of the present invention will be described in which a thin film transistor 120 is formed on a lower substrate 110. However, the method of manufacturing a liquid crystal display according to another embodiment of the present invention includes forming a buffer layer of an insulating material on a lower substrate 110 and forming the thin film transistor 120 on the buffer layer .

The lower gate pad electrode 131 may be formed simultaneously with the gate line GL. The gate line GL may be formed simultaneously with the gate electrode 121 of the thin film transistor 120. For example, a method of manufacturing a liquid crystal display device according to an embodiment of the present invention includes forming a gate material layer on a lower substrate 110 with a conductive material, and patterning the gate material layer to form gate electrodes 121, And forming the gate line GL and the lower gate pad electrode 131 at the same time.

The lower data pad electrode 132 may be formed simultaneously with the data line DL. The data line DL may be formed simultaneously with the source electrode 124 and the drain electrode 125 of the thin film transistor 120. For example, a method of manufacturing a liquid crystal display device according to an embodiment of the present invention includes forming a data material layer on a gate insulating layer 122 and a semiconductor pattern 123 as a conductive material, and patterning the data material layer Forming the source electrode 124, the drain electrode 125, the data line DL, and the lower data pad electrode 132 at the same time. In the method of manufacturing a liquid crystal display device according to an embodiment of the present invention, the lower data pad electrode 132 and the data line GL may be formed on the gate insulating layer 122.

1 and 7B, a method of manufacturing a liquid crystal display according to an embodiment of the present invention includes forming a lower protective film 140 (not shown) on the thin film transistor 120, the data line DL and the lower data pad electrode 132, Forming a planarization layer 150 on the lower protective layer 140 and forming a common electrode material layer 161 on the planarization layer 150. Referring to FIG.

The lower protective layer 140 may be formed to cover the surfaces of the thin film transistor 120, the data line DL, and the lower data pad electrode 132. The lower protective layer 140 may have a predetermined thickness. The lower protective layer 140 may be formed of an insulating material.

The planarization layer 150 may be removed by removing the steps of the lower gate pad electrode 131, the gate electrode GL, the lower data pad electrode 132, the data line DL, . The planarization layer 150 may be formed of an insulating material. The planarization layer 150 may be formed of a material different from that of the lower protective layer 140. For example, the planarization layer 150 may be formed of an organic insulating material such as photo-acryl.

The common electrode material layer 160 may have a predetermined thickness. The common electrode material layer 160 may include a conductive material. For example, the common electrode material layer 160 may be formed of a transparent conductive material such as ITO and IZO.

1 and 7C, a method of manufacturing a liquid crystal display according to an exemplary embodiment of the present invention includes forming a first contact mask pattern 10 on the common electrode material layer 160 using a halftone mask . ≪ / RTI >

The first contact mask pattern 10 may include an open region 11, a first contact masking region 12, and a second contact masking region 13. The second contact masking region 13 may be thinner than the first contact masking region 12.

The first contact masking region 12 and the second contact masking region 13 may be formed on the pixel region PA. The first contact mask pattern 10 may expose the common electrode material layer 160 covering the lower gate pad electrode 131 and the lower data pad electrode 132. For example, within the pixel region PA, the second contact masking region 13 may be located between the open region 11 and the first contact masking region 12.

The open region 11 of the first contact mask pattern 10 may overlap a certain region of the thin film transistor 120 in the pixel region PA. For example, the step of forming the first contact mask pattern 10 may include forming the open region 11 overlapping with the drain electrode 125 of the thin film transistor 120.

Referring to FIGS. 1 and 7D, a method of manufacturing a liquid crystal display device according to an embodiment of the present invention may include forming a via hole CH using the first contact mask pattern 10.

The forming of the via hole CH may include etching the common electrode material layer 161 and the planarization layer 150 using the first contact mask pattern 10 as an etching mask. The forming of the via hole CH may include forming the common electrode material pattern 162 by etching the common electrode material layer 161.

The step of forming the via hole CH may include exposing the lower protective layer 140 located on a certain region of the thin film transistor 120. For example, a portion of the lower protective layer 140 located on the drain electrode 125 of the thin film transistor 120 may be exposed by the via hole CH. The lower protective layer 140 covering the lower gate pad electrode 131 and the lower protective layer 140 covering the lower data pad electrode 132 may be exposed by the process of forming the via hole CH.

Referring to FIGS. 1 and 7E, a method of manufacturing a liquid crystal display device according to an embodiment of the present invention includes: forming a first contact mask pattern 10, And forming a contact mask pattern 20.

The second contact mask pattern 20 may include an open region 21 and a contact masking region 22. The open region 21 of the second contact mask pattern 20 may be formed at the same position as the open region 11 and the second contact masking region 13 of the first contact mask pattern 10 have. The contact masking region 22 of the second contact mask pattern 20 may be formed at the same position as the first contact masking region 12 of the first contact mask pattern 10.

The forming of the second contact mask pattern 20 may include removing the second contact masking area 13 of the first contact mask pattern 10. For example, the process of forming the second contact mask pattern 20 may include ashing the first contact mask pattern 10. A certain region of the common electrode material pattern 162 located close to the via hole CH may be exposed by the second contact mask pattern 20.

Referring to FIGS. 1 and 7f, a method of manufacturing a liquid crystal display according to an embodiment of the present invention includes forming the common electrode 163 using the second contact mask pattern 20, (20). ≪ / RTI >

The step of forming the common electrode 163 may include etching the common electrode material pattern 162 using the second contact mask pattern 20 as an etching mask. The common electrode 163 may be spaced apart from the preliminary contact hole CH.

The method of fabricating a liquid crystal display device according to an exemplary embodiment of the present invention may include forming the via hole CH of the planarization layer 150 and forming the common electrode 163 in a single mask pattern. Accordingly, in the liquid crystal display device according to the embodiment of the present invention, the number of mask patterns used in the manufacturing process can be reduced. Therefore, in the method of manufacturing a liquid crystal display device according to the embodiment of the present invention, manufacturing time and manufacturing cost can be reduced. In addition, in the method of manufacturing a liquid crystal display device according to the embodiment of the present invention, the defect occurrence rate due to misalignment of the mask pattern can be reduced.

Referring to FIGS. 1 and 7G, a method of manufacturing a liquid crystal display according to an exemplary embodiment of the present invention includes forming a top protective layer 170 on the common electrode 163, A pad contact hole 170GH, a data pad contact hole 170DH, and a pixel contact hole 170TH.

The upper protective layer 170 may be formed to extend along the surface of the via hole CH. The upper protective layer 170 may have a predetermined thickness. The upper protective layer 170 may be formed of an insulating material.

The step of forming the gate pad contact hole 170GH may include exposing at least a part of the upper surface of the lower gate pad electrode 131. For example, the step of forming the gate pad contact hole 170GH may include removing a predetermined region of the upper protective film 170 located on the lower gate pad electrode 131, Removing the lower protective film 140 exposed by the lower protective film 140 and removing the gate insulating film 122 exposed by the lower protective film 140.

The step of forming the data pad contact hole 170DH may include exposing at least a part of the upper surface of the lower data pad electrode 132. For example, the step of forming the data pad contact hole 170DH may include removing a predetermined region of the upper protective film 170 located on the lower data pad electrode 132, And removing the lower protective film 140 exposed by the lower protective film 140.

The step of forming the pixel contact hole 170 TH may include exposing a certain region of the thin film transistor 120. For example, the step of forming the pixel contact hole 170TH may include removing a predetermined region of the upper protective film 170 located on the thin film transistor 120, And removing the lower protective film 140.

The pixel contact hole 170TH may be formed to include a region overlapping the via hole CH. For example, the pixel contact hole 170TH may be formed in the via hole CH. The pixel contact hole 170TH may have a smaller area than the via hole CH. The step of forming the pixel contact hole 170TH may include exposing a part of a predetermined region of the thin film transistor 120 overlapping the via hole CH.

The pixel contact hole 170TH may be formed simultaneously with the gate pad contact hole 170GH. The gate pad contact hole 170GH may be formed simultaneously with the data pad contact hole 170DH. For example, a method of manufacturing a liquid crystal display according to an embodiment of the present invention includes forming a lower gate pad electrode 131, a lower data pad electrode 132, and a drain electrode (not shown) of a thin film transistor 120 on a top protective layer 170 Etching the upper protective layer 170 by using the mask pattern as an etch mask and forming the lower protective layer 140 exposed by the upper protective layer 170. [ And the gate insulating layer 122 in this order.

Referring to FIGS. 1 and 7H, a method of manufacturing a liquid crystal display according to an embodiment of the present invention includes forming the gate pad contact hole 170GH, the data pad contact hole 170DH, and the pixel contact hole 170TH, And forming a pixel electrode material layer 180 on the lower substrate 110.

The pixel electrode material layer 180 may be formed to extend along the surface of the gate pad contact hole 170GH. For example, the pixel electrode material layer 180 may be connected to the lower gate pad electrode 131 through the gate pad contact hole 170GH.

The pixel electrode material layer 180 may be formed to extend along the surface of the data pad contact hole 170DH. For example, the pixel electrode material layer 180 may be connected to the lower data pad electrode 132 through the data pad contact hole 170DH.

The pixel electrode material layer 180 may be formed to extend along the surface of the pixel contact hole 170TH. For example, the pixel electrode material layer 180 may be connected to the drain electrode 125 of the thin film transistor 120 through the pixel contact hole 170TH.

The pixel electrode material layer 180 may have a predetermined thickness. The pixel electrode material layer 180 may be formed of a conductive material. For example, the pixel electrode material layer 180 may be formed of a transparent conductive material such as ITO and IZO.

1 and 7i, a manufacturing method of a liquid crystal display device according to an embodiment of the present invention includes forming an electrode mask pattern 30 on the pixel electrode material layer 180 using a halftone mask can do.

The electrode mask pattern 30 may include an open region 31, a first electrode masking region 32, and a second electrode masking region 33. The second electrode masking region 33 may be thinner than the first electrode masking region 32.

The second electrode masking region 33 of the electrode mask pattern 30 may be formed on the lower gate pad electrode 131 and the lower data pad electrode 132. The step of forming the electrode mask pattern 30 may include forming a second electrode masking region 33 overlapping the gate contact hole 170GH and the data contact hole 170DH. The gate contact hole 170GH and the data contact hole 170DH may be filled with the second electrode masking region 33 of the electrode mask pattern 30. [

The electrode mask pattern 30 may be formed to cover a certain region of the thin film transistor 120 exposed by the pixel contact hole 170TH. For example, the step of forming the electrode mask pattern 30 may include forming a first electrode masking region 32 overlapping the pixel contact hole 170TH. The pixel contact hole 170TH may be filled by the first electrode masking region 32. [

Referring to FIGS. 1 and 7J, a method of manufacturing a liquid crystal display according to an embodiment of the present invention includes etching the pixel electrode material layer 180 using the electrode mask pattern 30 as an etching mask, 181, an upper data pad electrode 182, and a pixel electrode 183.

The upper gate pad electrode 181 may be formed on the lower gate pad electrode 131. The upper gate pad electrode 181 may be electrically connected to the lower gate pad electrode 131 through the gate contact hole 170GH. The lower gate pad electrode 131 and the upper gate pad electrode 181 may form a gate pad GP.

The upper data pad electrode 182 may be formed on the lower data pad electrode 132. The upper data pad electrode 182 may be electrically connected to the lower data pad electrode 132 through the data contact hole 170DH. The lower data pad electrode 132 and the upper data pad electrode 182 may form a data pad DP.

The pixel electrode 183 may be formed in the pixel region PA defined by the gate line GL and the data line DL. The pixel electrode 183 may be formed to include a region overlapping the common electrode 163. For example, the step of forming the pixel electrode 183 may include etching the pixel electrode material layer 180 to form a slit bar portion formed on the common electrode 163.

A method of manufacturing a liquid crystal display device according to an embodiment of the present invention is described as forming a common electrode 163 in a plate shape and forming a pixel electrode 183 including a slit bar portion on the common electrode 163 do. However, in the method of manufacturing a liquid crystal display device according to another embodiment of the present invention, a plate-shaped pixel electrode 183 may be formed on the common electrode 163 including a slit bar portion.

The manufacturing method of the liquid crystal display device according to the embodiment of the present invention is described as forming the common electrode 163 and the pixel electrode 183 on different layers. However, in the method of manufacturing a liquid crystal display device according to another embodiment of the present invention, the common electrode 163 and the pixel electrode 183 can be formed on the same layer.

1 and 7K, a method of manufacturing a liquid crystal display according to an embodiment of the present invention includes forming a bump pattern 190 on the upper surface of the pixel electrode 183 using the electrode mask pattern 30 .

The step of forming the bump pattern 190 may include removing the second electrode masking region 33 of the electrode mask pattern 30. For example, the step of forming the bump pattern 190 may include ashing the electrode mask pattern 30.

The gate electrode GL, the data line DL, the data pad DP, the thin film transistor 120, the common electrode 163, the gate electrode GL, the gate electrode GL, The pixel electrode 183 and the bump pattern 190 may constitute the lower array 100.

The method of manufacturing a liquid crystal display device according to an exemplary embodiment of the present invention can perform the step of forming the pixel electrode 183 and the step of forming the bump pattern 190 with a single mask pattern. Accordingly, in the method of manufacturing a liquid crystal display device according to an embodiment of the present invention, the number of mask patterns used in the manufacturing process can be reduced. Therefore, in the method of manufacturing a liquid crystal display device according to the embodiment of the present invention, manufacturing time and manufacturing cost can be reduced. In addition, in the method of manufacturing a liquid crystal display device according to an embodiment of the present invention, a defect occurrence rate due to misalignment of a mask pattern can be reduced.

3, the method of fabricating a liquid crystal display according to an embodiment of the present invention includes the steps of attaching the upper array 200 including the spacers 250 on the lower array 100, And forming a liquid crystal layer 300 between the upper array 100 and the upper array 200.

The step of attaching the upper array 200 may include aligning the upper array 200 such that the spacers 250 are positioned on the bump pattern 190 of the lower array 100. The upper array 200 may include color filters 220 and a black matrix 230 between the upper substrate 210 and the spacers 250. The step of attaching the upper array 200 may include aligning the upper array 200 such that the black matrix 230 is positioned on the bump pattern 190 of the lower array 100.

A method of manufacturing a liquid crystal display device according to an embodiment of the present invention may be such that a bump pattern 190, a spacer 250, and a black matrix 230 overlap each other on the thin film transistor 120. Accordingly, in the method of manufacturing a liquid crystal display device according to an embodiment of the present invention, the area of the non-display area located between the display areas can be minimized. Therefore, in the method of manufacturing a liquid crystal display device according to the embodiment of the present invention, the image quality and sharpness of the image can be improved.

As a result, the manufacturing method of a liquid crystal display device according to an embodiment of the present invention is a method of forming a bump pattern 190 by forming a pixel electrode 183 and a bump pattern 190 in a single mask pattern by using a halftone mask, The process can be simplified. Accordingly, in the method of manufacturing a liquid crystal display device according to the embodiment of the present invention, an increase in manufacturing time and manufacturing cost due to the process of forming the bump pattern 190 can be minimized. In addition, in the method of manufacturing a liquid crystal display device according to the embodiment of the present invention, it is possible to prevent an increase in the defect occurrence rate due to the step of forming the bump pattern 190. Therefore, the productivity of the liquid crystal display device according to the embodiment of the present invention can be improved.

100: lower array 110: lower substrate
120: thin film transistor 150: planarization film
163: common electrode 170: upper protective film
183: pixel electrode 190: bump pattern
200: upper array 210: upper substrate
250: spacer GL: gate line
GP: gate pad DL: data line
DP: Data Pad

Claims (16)

A thin film transistor positioned on a lower substrate;
A planarization layer located on the thin film transistor and including a pixel contact hole exposing a part of the thin film transistor;
A pixel electrode located on the planarization film and extending to the inside of the pixel contact hole;
A bump pattern located on the upper surface of the pixel electrode and overlapping the pixel contact hole; And
And a spacer located on the upper substrate facing the lower substrate and overlapping the bump pattern,
And the pixel contact hole of the planarization film is filled with the pixel electrode and the bump pattern. The method according to claim 1,
Wherein the bump pattern is in direct contact with the upper surface of the pixel electrode. The method according to claim 1,
Wherein the bump pattern includes a side surface that is vertically aligned with a side surface of the pixel electrode. The method according to claim 1,
Wherein the bump pattern has a bar shape extending in one direction on the upper surface of the pixel electrode. The method according to claim 1,
A data pad including a gate pad including a lower gate pad electrode including the same material as the gate electrode of the thin film transistor and a lower data pad electrode including the same material as the source electrode and the drain electrode of the thin film transistor Liquid crystal display device. The method according to claim 1,
Wherein a horizontal width of the bump pattern is larger than a horizontal width of the pixel contact hole. The method according to claim 1,
Color filters positioned between the upper substrate and the spacers; And
Further comprising a black matrix positioned between the color filters,
And the bump pattern overlaps with the black matrix. 8. The method of claim 7,
Wherein a horizontal width of the spacer is smaller than a horizontal width of the black matrix and a horizontal width of the bump pattern. 9. The method of claim 8,
Wherein a horizontal width of an end of the spacer located closer to the bump pattern is smaller than a horizontal width of an end of the spacer located close to the black matrix. The method according to claim 1,
A common electrode disposed between the lower substrate and the pixel electrode; And
And a top protective layer disposed between the common electrode and the pixel electrode. 11. The method of claim 10,
Wherein the common electrode is in the form of a plate. Forming a pixel electrode material layer on the lower substrate;
Forming an electrode mask pattern including an open area, a first electrode masking area and a second electrode masking area thinner than the first electrode masking area on the pixel electrode using a halftone mask;
Forming a pixel electrode by etching the pixel electrode material layer using the electrode mask pattern as an etching mask; And
And removing the second electrode masking region of the electrode mask pattern to form a bump pattern on the upper surface of the pixel electrode. 13. The method of claim 12,
Forming a thin film transistor on the lower substrate;
Forming a planarization film on the thin film transistor; And
Forming a pixel contact hole through the planarization film to expose a first region of the thin film transistor,
Wherein the pixel electrode material layer is formed to extend along a surface of the pixel contact hole,
Wherein the bump pattern is formed to overlap with the thin film transistor. 14. The method of claim 13,
Wherein the forming of the electrode mask pattern includes forming a first electrode masking region overlapping the pixel contact hole. 14. The method of claim 13,
The forming of the pixel contact holes may include forming a common electrode material layer on the planarization layer, forming an open region, a first contact masking region, and a first contact masking region on the common electrode material layer using a halftone mask, Forming a first contact mask pattern including a second contact masking region that is thinner than the first contact masking region and etching the common electrode material layer and the planarizing film using the first contact mask pattern as an etching mask, Forming a via hole overlapping the first contact mask pattern; removing the second contact masking area of the first contact mask pattern to expose a certain region of the common electrode material pattern formed by etching the common electrode material layer; Forming a second contact mask pattern on the common electrode material pattern; Forming a common electrode, but on the common electrode includes the steps of removing a predetermined region of the upper protective film to form an upper protective layer which extends along the surface of the via hole,
And the second region of the thin film transistor includes the first region of the thin film transistor. 16. The method of claim 15,
And the second contact mask pattern exposes the common electrode material pattern located close to the via hole.

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