CN103928469A - TFT array substrate, manufacturing method thereof and display panel - Google Patents
TFT array substrate, manufacturing method thereof and display panel Download PDFInfo
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Abstract
The invention discloses a TFT array substrate with G-VIA through holes, a display panel and a preparation method of the TFT array substrate.
Description
Technical field
The present invention relates to active matrix (Active Matrix) field, relate in particular to a kind of tft array substrate, the manufacture method of this tft array substrate, and the display floater that comprises this tft array substrate.
Background technology
Active-matrix substrate normally arranges thin-film transistor (Thin Film Transistor, TFT) array on a substrate, conventionally also can be referred to as tft array substrate.Tft array substrate is widely used in flat-panel devices, comprise display panels (Liquid Crystal Display, LCD), Electronic Paper, Organic Light Emitting Diode (Organic Light Emitting Diode, OLED) display floater, radioscopic image transducer (X Ray Image Sensor) etc.
The vertical view of the basic structure of tft array substrate 1 as shown in Figure 1, mainly comprises substrate 100, and be arranged on substrate 100 as lower member: many grid lines (gate line) 101; The many source lines (source line or data line) 102 that intersect with grid line 101 insulation; Be arranged at the TFT103 of grid line 101 and source line 102 infalls.
Conventionally tft array substrate 1 also comprises pixel electrode (not shown in figure 1).The region that adjacent grid line 101 and adjacent source line 102 surround is pixel region, and pixel region comprises TFT region and pixel electrode area.This pixel electrode is arranged in pixel electrode area, and TFT is arranged in TFT region.The grid line 101 of TFT103 and this infall and 102 couplings of source line, the grid of TFT103 is electrically connected to grid line 101, and the source electrode of TFT103 is electrically connected to source line 102; In addition, the drain electrode of TFT103 is electrically connected to pixel electrode.
Fig. 2 is the process chart of a kind of tft array substrate of prior art.As shown in Figure 2, the processing step of the tft array substrate of prior art is as follows:
A, provide a substrate 100;
B, on substrate 100, deposit one first conductive layer, this first conductive layer of etching forms the first electrode pattern, comprises grid 1031, the first conductive pattern 1011 of grid line (not shown), TFT;
C, on the basis of step B, deposit first insulating barrier (being gate insulator) 104 of the whole substrate scope of a covering, this first insulating barrier 104 covers these first electrode patterns;
D, on the basis of step C, deposit semi-conductor layer, this semiconductor layer of etching forms the semiconductor figure 1032 of TFT;
E, on the basis of step D, deposit one second insulating barrier (being etching barrier layer) 105, this second insulating barrier 105 of etching forms the first via hole 1051 and the second via hole 1052 in TFT region;
F, on the basis of step e this first insulating barrier 104 of etching and the second insulating barrier 105, in via area, form the 3rd via hole 1053;
G, on the basis of step F, deposit one second conductive layer, this second conductive layer of etching forms the second electrode pattern, the source electrode 1033, drain electrode the 1034, second conductive pattern 1021 that comprise TFT, source electrode 1033 is connected with semiconductor figure 1032 by the first via hole 1051, drain electrode 1034 is connected with semiconductor figure 1032 by the second via hole 1052, and the second conductive pattern 1021 is connected with the first conductive pattern 1011 by the 3rd via hole 1053;
H, on the basis of step G, deposit one the 3rd insulating barrier (being passivation layer) 106, etching the 3rd insulating barrier 106 forms the 4th via hole 1061, in via area, forms the 5th via hole 1062 in TFT region;
I, on the basis of step H, deposit one the 3rd conductive layer, etching the 3rd conductive layer forms third electrode pattern, comprise the pixel electrode 1071 that is positioned at pixel electrode area and the 3rd conductive pattern 1072 that is positioned at via area, pixel electrode 1071 is connected with drain electrode 1034 by the 4th via hole 1061, and the 3rd conductive pattern 1072 is connected with the second conductive pattern 1021 by the 5th via hole 1062.
From the tft array substrate structure of the prior art shown in above-mentioned Fig. 2, can find out, this tft array substrate comprises the 3rd via hole 1053, the 3rd via hole 1053 runs through etching barrier layer 105 and gate insulator 104, the second conductive patterns 1021 are connected with the first conductive pattern 1011 by the 3rd via hole 1053.Conventionally, the 3rd via hole 1053 can be referred to as G-VIA via hole, for by with source-drain electrode with layer the second conductive pattern 1021 with grid with layer the first conductive pattern 1011 be directly connected.So just formed the structure that the second conductive pattern 1021 is just directly connected with the first conductive pattern 1011 by the 3rd via hole 1053.(amorphous oxides gate driver for example, usually uses this structure in AOG) etc. to the gate driver circuit that be directly prepared in tft array substrate, consists of TFT, for example, the grid of certain TFT is connected with the source/drain of another TFT.And this structure in gate driver circuit is passivated layer 106 covering protection, reduced the impact of static on gate driver circuit etc.It should be noted that, the via hole 1053 shown in Fig. 2 is not passivated layer 106 and covers, but is connected with the 3rd conductive pattern 1072, is not therefore G-VIA via hole in gate driver circuit, but the via hole in the binding such as IC or FPC region.
From the processing step of the tft array substrate of the prior art shown in above-mentioned Fig. 2, can find out, prepare the tft array substrate shown in last width figure in Fig. 2, need to pass through steps A-I, adopt 7 road lithographic process steps, processing step is comparatively complicated.
Summary of the invention
Embodiments of the invention technical problem to be solved is that the step of preparation process of the tft array substrate with G-VIA via hole of prior art is complicated.
In order to solve the problems of the technologies described above, embodiments of the invention provide a kind of tft array substrate, comprising: substrate; Be positioned at grid and the first conductive pattern on described substrate; Cover the gate insulator of described grid, the first conductive pattern and substrate; Be positioned on described gate insulator, the first semiconductor figure of described grid top; Cover the second insulating barrier of described the first semiconductor figure and gate insulator, described the second insulating barrier is organic photo material; The first via hole and the second via hole that run through described the second insulating barrier, run through the 3rd via hole of described the second insulating barrier and gate insulator; Be positioned at source electrode, drain electrode and the second conductive pattern on described the second insulating barrier; Described source electrode is electrically connected to described the first semiconductor figure by described the first via hole, described drain electrode is electrically connected to described the first semiconductor figure by described the second via hole, and described the second conductive pattern is electrically connected to described the first conductive pattern by described the 3rd via hole.
Now, described tft array substrate can also comprise: the 3rd insulating barrier that covers described source electrode, drain electrode, the second conductive pattern and the second insulating barrier; The 4th via hole that runs through described the 3rd insulating barrier; Pixel electrode, is electrically connected to described drain/source by described the 4th via hole.
Preferably, described tft array substrate also comprises: be positioned at the second semiconductor figure of same layer with described the first semiconductor figure; The first opening that runs through described the second insulating barrier, is positioned at described the second semiconductor figure top.Wherein, described the first opening integral body is positioned at the scope of described the second semiconductor figure and exposes described the second semiconductor figure.Now, described tft array substrate can also comprise: the 3rd insulating barrier that covers described source electrode, drain electrode, the second conductive pattern and the second insulating barrier; The 4th via hole that runs through described the 3rd insulating barrier; Pixel electrode, is electrically connected to described drain/source by described the 4th via hole; At described the first opening part, described the 3rd insulating barrier and pixel electrode are set in turn on described the second semiconductor figure.
Preferably, described pixel electrode adopts transparent conductive material or metal material.
Preferably, described tft array substrate also comprises the public electrode that is positioned at same layer or different layers with described pixel electrode.
Preferably, described tft array substrate also includes OLED.
Preferably, in above-described embodiment, described the second conductive pattern is connected formed syndeton and is covered by described the 3rd insulating barrier with described the first conductive pattern by described the 3rd via hole.
Preferably, in above-described embodiment, described tft array substrate also comprises: be positioned at the 3rd conductive pattern of same layer with described the first conductive pattern; The 5th via hole that runs through described the second insulating barrier and gate insulator; Be positioned at the 4th conductive pattern of same layer with described the second conductive pattern; Described the 4th conductive pattern is electrically connected to described the 3rd conductive pattern by described the 5th via hole.Now, described tft array substrate can further include the 6th conductive pattern that is positioned at same layer with described pixel electrode; The 6th via hole that runs through described the 3rd insulating barrier; Described the 6th conductive pattern is electrically connected to described the 5th conductive pattern by described the 6th via hole.
Embodiments of the invention also provide a kind of display floater, tft array substrate described above.
Preferably, described display floater is display panels or Electronic Paper or OLED display floater.
Embodiments of the invention also provide a kind of method of preparing above-mentioned tft array substrate, comprising:
S1, provide a substrate; S2, deposition one first conductive layer, the first conductive layer forms the first electrode pattern described in patterning, and described the first electrode pattern comprises grid, the first conductive pattern; S3, deposition one first insulating barrier, cover described the first electrode pattern; S4, deposition semi-conductor layer, semiconductor layer forms the first semiconductor figure described in patterning; The second insulating barrier of S5, deposition one organic photo material, the second insulating barrier forms the first via hole, the second via hole, the second opening that runs through described the second insulating barrier described in patterning; S6, the second insulating barrier of described patterning of take are mask, and the first insulating barrier that the second opening exposes described in etching, exposes described the first conductive pattern, to form the 3rd via hole that runs through described the first insulating barrier and the second insulating barrier; S7, deposition one second conductive layer, described in patterning, the second conductive layer forms the second electrode pattern, described the second electrode pattern comprises source electrode, drain electrode, the second conductive pattern, described source electrode is connected with described the first semiconductor figure by described the first via hole, described drain electrode is connected with described the first semiconductor figure by described the second via hole, and described the second conductive pattern is connected with described the first conductive pattern by described the 3rd via hole.
Preferably, the manufacture method of described tft array substrate also comprises the steps: S8, deposition one the 3rd insulating barrier, and the 3rd insulating barrier forms the 4th via hole described in patterning; S9, deposition one the 3rd conductive layer, the 3rd conductive layer forms third electrode pattern described in patterning, and described third electrode pattern comprises pixel electrode, and described pixel electrode is connected with described source/drain by described the 4th via hole.
Preferably, in the manufacture method of described tft array substrate, the first electrode pattern described in step S2 also comprises the 3rd conductive pattern; In step S5, be also formed with the 3rd opening that runs through described the second insulating barrier; The second insulating barrier of described patterning of also take in step S6 is mask, and the first insulating barrier that the 3rd opening exposes described in etching, exposes described the 3rd conductive pattern, to form the 5th via hole that runs through described the first insulating barrier and the second insulating barrier; The second electrode pattern described in step S7 also comprises the 4th conductive pattern, by described the 5th via hole, is connected with described the 3rd conductive pattern.Now, the manufacture method of described tft array substrate further comprises the steps: S8, deposition one the 3rd insulating barrier, and the 3rd insulating barrier forms the 4th via hole and the 6th via hole described in patterning; S9, deposition one the 3rd conductive layer, described in patterning, the 3rd conductive layer forms third electrode pattern, described third electrode pattern comprises pixel electrode and the 5th conductive pattern, described pixel electrode is connected with described drain electrode by described the 4th via hole, and described the 5th conductive pattern is connected with described the 4th conductive pattern by described the 6th via hole.
In terms of existing technologies, the tft array substrate that embodiments of the invention provide, and the preparation method of the display floater that comprises this tft array substrate, tft array substrate, owing to adopting organic photo material, prepare the etching barrier layer of tft array substrate, adopt simultaneously this etching barrier layer as mask etching go out for connect with source-drain electrode with the second conductive pattern of layer and with the via hole (be G-VIA via hole) of first conductive pattern of grid with layer, simplify processing step, reduced production cost.
Accompanying drawing explanation
Fig. 1 is the vertical view of basic structure of the tft array substrate of prior art;
Fig. 2 is the process chart of a kind of tft array substrate of prior art;
The plan structure schematic diagram of the tft array substrate that Fig. 3 provides for the embodiment of the present invention one;
The sectional structure schematic diagram of the tft array substrate that comprises syndeton G that Fig. 4 provides for the embodiment of the present invention one;
The sectional structure schematic diagram of the tft array substrate that comprises syndeton B that Fig. 5 provides for the embodiment of the present invention one;
The process chart of the tft array substrate that Fig. 6 provides for the embodiment of the present invention two;
The sectional structure schematic diagram of the tft array substrate that comprises syndeton G that Fig. 7 provides for the embodiment of the present invention three;
The sectional structure schematic diagram of the tft array substrate that comprises syndeton B that Fig. 8 provides for the embodiment of the present invention three;
The process chart of the tft array substrate that Fig. 9 provides for the embodiment of the present invention four.
Embodiment
Core concept of the present invention is to prepare in other words the tft array substrate with syndeton G in order to prepare with the tft array substrate of G-VIA via hole, adopt organic photo material to prepare the etching barrier layer of tft array substrate, adopt simultaneously this etching barrier layer as mask etching go out for connect with source-drain electrode with the second conductive pattern of layer and with the via hole (be G-VIA via hole) of first conductive pattern of grid with layer, simplify processing step, reduced production cost.
Embodiment mono-
The plan structure schematic diagram of the tft array substrate that the embodiment of the present invention one provides as shown in Figure 3.As can be seen from Figure 3 the tft array substrate that, the embodiment of the present invention one provides is viewing area (Active Area) and the outer peripheral areas (Non-Active Area) (not shown in Fig. 3) of surrounding this viewing area in plan structure.It mainly comprises substrate 300, and the pel array that is arranged at the viewing area on substrate 300, and pel array comprises as lower member: many grid lines (gate line) 301; The many source lines (source line) 302 that intersect with grid line 301 insulation; Be arranged at the TFT303 of grid line 301 and source line 302 infalls.
Conventionally the pel array of tft array substrate 3 also comprises pixel electrode (not shown in Fig. 3).The region that adjacent grid line 301 and adjacent source line 302 surround is pixel region, and pixel region comprises TFT region and pixel electrode area.This pixel electrode is arranged in pixel electrode area, and TFT is arranged in TFT region, and TFT can only have one (for example, in display panels, Electronic Paper), also can have a plurality of (for example, in OLED display floaters).Take in a pixel region and only have a TFT as switch as example, as shown in Figure 3, the grid line 301 of TFT303 and this infall and 302 couplings of source line, the grid of TFT303 is electrically connected to grid line 301, and the source electrode of TFT303 is electrically connected to source line 302.
It should be noted that, Fig. 3 only shows tft array substrate plan structure provided by the invention, but those skilled in the art can be known according to the common practise of this area, the plan structure of tft array substrate can have multiple different distortion, at this, does not do too much elaboration.
The sectional structure schematic diagram of the tft array substrate that the embodiment of the present invention one provides as shown in Figure 4.As can be seen from Figure 4 the tft array substrate that, the embodiment of the present invention one provides comprises:
Substrate 300;
Be positioned at grid 3031 and the first conductive pattern 3011 on substrate 300;
The first insulating barrier 304 of cover gate 3031, the first conductive pattern 3011 and substrate 300;
Be positioned on the first insulating barrier 304, the first semiconductor figure 3032 of grid 3031 tops;
The second insulating barrier 305, the second insulating barriers 305 that cover the first semiconductor figure 3032 and the first insulating barrier 304 are organic photo material;
The first via hole 3051 and the second via hole 3052 that run through the second insulating barrier 305, run through the 3rd via hole 3053 of the second insulating barrier 305 and the first insulating barrier 304;
Be positioned at source electrode 3033, drain electrode the 3034 and second conductive pattern 3021 on the second insulating barrier;
Source electrode 3033 is electrically connected to the first semiconductor figure 3032 by the first via hole 3051, drain electrode 3034 is electrically connected to the first semiconductor figure 3032 by the second via hole 3052, and the second conductive pattern 3021 is electrically connected to the first conductive pattern 3011 by the 3rd via hole 3053.
Specifically, substrate 300 adopts the transparent materials such as glass, quartz conventionally; Substrate 300 also can by adopt the transparent materials such as glass, quartz and on other structures (as resilient coating etc.) formation.Grid 3031 and the first conductive pattern 3011 are located immediately on the surface of substrate 300 conventionally.The grid 3031 of TFT and the first conductive pattern 3011 and grid line 301 are usually located at same layer, adopt identical material, as metals such as aluminium, therefore can in same processing step, prepare.
The first insulating barrier (being gate insulator) 304 covers whole substrate scope conventionally, and material can be silicon dioxide.
The first semiconductor figure 3032 is generally island, and material can be amorphous silicon, polysilicon, oxide semiconductor etc.
The second insulating barrier (being etching barrier layer) 305 covers whole substrate scope conventionally, and material is organic photo material.The second insulating barrier 305 covers the first semiconductor figures 3032, and source electrode 3033, the drain electrode of in subsequent etching, preparing TFT like this prevent the first semiconductor figure 3032 to cause etching at 3034 o'clock, therefore can be referred to as etching barrier layer.
Source electrode 3033, drain electrode the 3034, second conductive pattern 3021 are usually located at same layer with source line 302, adopt identical material, as metals such as molybdenums, therefore can in same processing step, prepare.Certainly, can be also 3034 for source electrode, 3033 is drain electrode.
The second insulating barrier 305 adopts organic photo material, on the one hand because itself has photobehavior, form therein the first via hole 3051 and the second via hole 3052, and the 3rd via hole 3053 while being arranged in the part (the second opening of embodiment bis-) of the second insulating barrier, only need the steps such as exposure, development, post bake, do not need etch step, technique can be simplified; After being positioned at the part of the second insulating barrier, formation the 3rd via hole 3053 directly carries out etching as mask on the other hand, do not need extra photoetching process just can form the part that the 3rd via hole 3053 is positioned at gate insulator, namely form the 3rd complete via hole 3053, technique can further be simplified.Concrete technology step can be participated in embodiment bis-.
In Fig. 4, also show preferred parts, tft array substrate 3 be also included in whole substrate scope, cover described source electrode, the 3rd insulating barrier (being passivation layer) 306 of drain electrode, the second conductive pattern and the second insulating barrier; The 4th via hole 3061 that runs through passivation layer 306; Pixel electrode 3071, is electrically connected to drain electrode 3034 by the 4th via hole 3061.The material of passivation layer 306 can be silica or silicon nitride.Pixel electrode 3071 can be transparent conductive material, as ITO, IZO etc.; Also can be opaque metal material, as Ag etc.Certainly tft array substrate can also comprise other structures, for example IPS(in plane switching) tft array substrate in display panels comprises the public electrode that is positioned at same layer with pixel electrode 3071; FFS(fringe filed switching) tft array substrate in display panels comprises the public electrode that is positioned at different layers with pixel electrode 3071; OLED(organic light emitting diode) display floater also includes OLED, and the pixel electrode 3071 of tft array substrate is the male or female of Organic Light Emitting Diode.
In addition, in Fig. 4, the second conductive pattern 3021 is directly connected with the first conductive pattern 3011 by the 3rd via hole 3053 in formed syndeton G(Fig. 4 shown in dotted line frame) be passivated layer 306 covering.This syndeton G is formed in the gate driver circuit or the pixel-driving circuit in OLED display floater that is directly prepared in tft array substrate conventionally, because usually need in these circuit, the grid of certain TFT is electrically connected to the source/drain of another TFT.This syndeton G in gate driver circuit is passivated layer 106 covering protection, has reduced the adverse effect of static to gate driver circuit etc.
As preferred embodiment a kind of, the tft array substrate that the embodiment of the present invention one provides is not shown in the syndeton G(Fig. 5 shown in Fig. 4 in via area), can also comprise another kind of syndeton B as shown in Figure 5.As can be seen from Figure 5 the tft array substrate that, the embodiment of the present invention one provides also comprises the 3rd conductive pattern 3012 that is positioned at same layer with the first conductive pattern 3011 in via area; The 5th via hole 3054 that runs through the second insulating barrier 305 and the first insulating barrier 304; Be positioned at the 4th conductive pattern 3022 of same layer with the second conductive pattern 3021; The 4th conductive pattern 3022 is electrically connected to the 3rd conductive pattern 3012 by the 5th via hole 3054.
In addition, tft array substrate also comprises the 6th via hole 3063 that runs through passivation layer 306; The 5th conductive pattern 3072, common and pixel electrode 3071 is positioned at same layer, adopts identical material, can in same processing step, prepare.The 5th conductive pattern 3072 is connected with the 4th conductive pattern 3022 by the 6th via hole 3063.Syndeton B shown in Fig. 5 comprises two via holes 3054 and 3063, and the 3rd conductive pattern the 3012, the 4th connecting in turn arrives electrograph shape 3022 and the 5th conductive pattern 3072.The 5th via hole 3054 and the 6th via hole 3063 can be positioned at same position place (as shown in Figure 5), also can be positioned at diverse location place.Syndeton B is usually located at binding (bonding) region, for being connected with external circuitry (as FPC, IC).Certainly, two via holes 3054 that syndeton B comprises and 3063 can not be positioned at same position place (be the two vertical overlapping) as shown in Figure 5, the 5th via hole 3054 and the 6th via hole 3063 can be positioned at diverse location (be the two not overlapping on vertical, stagger even completely).
Embodiment bis-
The process chart of the tft array substrate that the embodiment of the present invention two provides as shown in Figure 6.The step of preparation process of the tft array substrate that as can be seen from Figure 6, the embodiment of the present invention two provides is as follows:
S1, provide a substrate 300; Wherein, substrate 300 adopts the transparent materials such as glass, quartz conventionally, or by adopt the transparent materials such as glass, quartz and on other structures (as resilient coating etc.) formation.
S2, on substrate 300, deposit one first conductive layer (not shown), this first conductive layer of patterning forms the first electrode pattern, and the first electrode pattern comprises grid 3031, the first conductive pattern 3011 of TFT; Wherein, this first conductive layer can adopt the metals such as aluminium, aluminium molybdenum alloys.The first electrode pattern can also comprise grid line (not shown).Preferably, the first electrode pattern also comprises the 3rd conductive pattern 3012.
S3, on the basis of step S2, deposit first insulating barrier (being gate insulator) 304 of the whole substrate scope of a covering, this first insulating barrier 304 covers these first electrode patterns; Wherein, the first insulating barrier (being gate insulator) 304 can be silicon dioxide.
S4, on the basis of step S3, deposit semi-conductor layer, this semiconductor layer of patterning forms the first semiconductor figure 3032 in TFT region; Wherein, the first semiconductor figure 3032 is generally island, and material can be amorphous silicon, polysilicon, oxide semiconductor etc.
S5, on the basis of step S4, deposit second insulating barrier (being etching barrier layer) 305 of an organic photo material, this second insulating barrier (being etching barrier layer) 305 is exposed, this second insulating barrier 305 of patterning (as develop) in TFT region, form run through this second insulating barrier 305 the first via hole 3051 and the second via hole 3052, in via area, form the second opening 3053a that runs through this second insulating barrier 305.
Preferably, in step S5, also in via area, form the 3rd opening 3054a that runs through this second insulating barrier 305 simultaneously.Conventionally, the second opening 3053a is formed at the gate driver circuit region of tft array substrate or the pixel-driving circuit region of OLED, because usually need in these circuit, the grid of certain TFT is electrically connected to the source/drain of another TFT.In step S5, because the second insulating barrier 305 adopts organic photo material, form therein the first via hole 3051 and the second via hole 3052, and when the second opening 3053a, the 3rd opening 3054a, only need the steps such as exposure, development, post bake, do not need etch step, technique can be simplified.
S6, on the basis of step S5, to take this second insulating barrier 305 be mask, and the first insulating barrier 304 that etching (carving as dry) the second opening 3053a is exposed, to expose this first conductive pattern 3011.So just formed the 3rd via hole 3053 that runs through the first insulating barrier 304 and the second insulating barrier 305.
Preferably, in step S6, also simultaneously take this second insulating barrier 305 is mask, and the first insulating barrier 304 that etching (carving as dry) the 3rd opening 3054a is exposed, to expose the 3rd conductive pattern 3012.So just formed the 5th via hole 3054 that runs through the first insulating barrier 304 and the second insulating barrier 305.
S7, on the basis of step S6, deposit one second conductive layer, this second conductive layer of patterning forms the second electrode pattern, this second electrode pattern comprises source electrode 3033, drain electrode the 3034, second conductive pattern 3021 of TFT, source electrode 3033 is connected with the first semiconductor figure 3032 by the first via hole 3051, drain electrode 3034 is connected with the first semiconductor figure 3032 by the second via hole 3052, and the second conductive pattern 3021 is connected with the first conductive pattern 3011 by the 3rd via hole 3053.Certainly, can be also 3034 for source electrode, 3033 is drain electrode.Like this, the second conductive pattern 3021 is directly connected formed syndeton G by the 3rd via hole 3053 with the first conductive pattern 3011.This syndeton G is formed at gate driver circuit region in tft array substrate or the pixel-driving circuit region of oled panel conventionally.This second electrode pattern can also comprise source line.
Preferably, this second electrode pattern also comprises the 4th conductive pattern 3022, by the 5th via hole 3054, is connected with the 3rd conductive pattern 3012.
Except above-mentioned steps S1-S7, the manufacture method of the tft array substrate that the embodiment of the present invention two provides also comprises the steps:
S8, on the basis of step S7, deposit one the 3rd insulating barrier (being passivation layer) 306, patterning the 3rd insulating barrier 306 forms the 4th via hole 3061 in TFT region; Wherein, the second conductive pattern 3021 is directly connected formed syndeton G and is passivated layer 306 covering with the first conductive pattern 3011 by the 3rd via hole 3053, do not subject to electrostatic damage.
Preferably, step S8 also forms binding (bonding) region that the 6th via hole 3062, the six via holes 3062 run through passivation layer 306 are usually located at external circuitry (as FPC, IC) etc. simultaneously.Wherein, the 6th via hole 3062 and the 5th via hole 3054 can be positioned at same position place (be the two vertical overlapping) as shown in Figure 6, also can be positioned at diverse location (be the two not overlapping on vertical, stagger even completely).
S9, on the basis of step S8, deposit one the 3rd conductive layer, patterning the 3rd conductive layer forms third electrode pattern, and third electrode pattern comprises the pixel electrode 3071 that is positioned at pixel electrode area.Wherein, pixel electrode 3071 is connected with the drain electrode 3034 of TFT by the 4th via hole 3061.
Preferably, third electrode pattern also comprises that the 5th conductive pattern 3072, the five conductive patterns 3072 that are positioned at via area (being specially binding region) are connected with the 4th conductive pattern 3022 by the 6th via hole 3062.The 5th conductive pattern 3072, the 4th conductive pattern 3022, the 3rd conductive pattern 3021 form syndeton B(by the 6th via hole 3062 and the series connection of the 5th via hole 3054 respectively, and in fact a wherein part of syndeton B is identical with syndeton G).In this step, the material of the 3rd conductive layer can be transparent conductive material, as ITO, and IZO etc., now pixel electrode 3071 can be used as the pixel electrode of transmissive liquid crystal display panel, can be also the anode/cathode of oled panel.The material of the 3rd conductive layer can be metal material, as Al, and Ag etc., the pixel electrode of reflecting type liquid crystal display panel, Electronic Paper, can be also the anode/cathode of oled panel.
For display panels, after step S9, comprise preparation oriented layer, become the traditional handicrafts such as box, do not repeat them here.For FFS type display panels, also comprise the conventional procedures of preparing public electrode,, do not repeat them here.
For Electronic Paper, after step S9, comprise traditional handicrafts such as pasting microcapsule layer, do not repeat them here.
For oled panel, after step S9, comprise the traditional handicrafts such as preparation pixel defining layer, organic luminous layer, do not repeat them here.
From the processing step of the tft array substrate shown in above-mentioned Fig. 6, can find out, prepare the tft array substrate that comprises syndeton G shown in last width figure in Fig. 6, need to pass through step S1-S9, adopt 6 road lithographic process steps, processing step is simplified.
Embodiment tri-
The tft array substrate that the tft array substrate that the embodiment of the present invention three provides provides at embodiment mono-has been made improvement, and the part identical with embodiment mono-no longer repeats, and its difference part is described below:
As shown in Figure 7, the sectional structure schematic diagram of the tft array substrate that comprises syndeton B that the embodiment of the present invention three provides as shown in Figure 8 for the sectional structure schematic diagram of the tft array substrate that comprises syndeton G that the embodiment of the present invention three provides.From Fig. 7 and Fig. 8, can find out, on the basis of the tft array substrate embodiment mono-that the embodiment of the present invention three provides, transmission region in pixel arranges one second semiconductor figure 3036, be positioned at same layer with the first semiconductor figure 3032, adopt identical material, therefore can in same processing step, prepare.The second insulating barrier 305 that is positioned at these the second semiconductor figure 3036 tops has the first opening 3055.The first opening 3055 sizes are conventionally slightly less than this second semiconductor figure 3036 and expose the second semiconductor figure 3036 that the second semiconductor figure 3036, the three insulating barriers 306 cover whole the first opening 3055 and come out.
It should be noted that, as shown in Figure 4,5, 6, because the second insulating barrier (being etching barrier layer) 305 common transmitance after overexposure that organic photo material forms is poor, if pixel region is covered by the second insulating barrier 305, the transmitance of light will be very poor, comprises that the light transmittance of the display floater of the tft array substrate that embodiment mono-provides will be very poor.Therefore the tft array substrate that embodiment tri-provides has been removed second insulating barrier 305 of pixel transmission region (being specially the first opening 3055 places), has so just greatly improved light transmittance.But simultaneously owing to being provided with the second semiconductor figure 3036 below the first opening 3055, the first opening 3055 integral body are positioned at the scope of the second semiconductor figure 3036, the first opening 3055 places do not come out the first insulating barrier 304 of below, so just having avoided take the second insulating barrier 305 is mask, during the first insulating barrier 304 that etching (carving as dry) the second opening 3053a and/or the 3rd opening 3054a are exposed, the first insulating barrier 304 of pixel transmission region is also etched away.Concrete processing step is shown in embodiment tetra-.
Preferably, as embodiment tri-, embodiment tetra-also can comprise passivation layer 306 and pixel electrode 3071, and difference is, in embodiment tetra-, at first opening 3055 place's passivation layers 306 and pixel electrode 3071, is set in turn on the second semiconductor figure 3036.
Embodiment tetra-
On the basis of the technological process of the tft array substrate that the technological process of the tft array substrate that the embodiment of the present invention four provides (as shown in Figure 9) provides at embodiment bis-, made improvement, the part identical with embodiment bis-no longer repeats, and its difference part is described below:
S1, provide a substrate 300;
S2, on substrate 300, deposit one first conductive layer, this first conductive layer of patterning forms the first electrode pattern, and the first electrode pattern comprises grid 3031, the first conductive pattern 3011 of grid line (not shown), TFT; Preferably, the first electrode pattern also comprises the 3rd conductive pattern 3012.
S3, on the basis of step S2, deposit first insulating barrier (being gate insulator) 304 of the whole substrate scope of a covering, this first insulating barrier 304 covers these first electrode patterns;
S4, on the basis of step S3, deposit semi-conductor layer, this semiconductor layer of patterning forms the first semiconductor figure 3032, in pixel electrode area (or pixel transmission region), forms the second semiconductor figure 3036 in TFT region;
S5, on the basis of step S4, deposit second insulating barrier (being etching barrier layer) 305 of an organic photo material, this second insulating barrier (being etching barrier layer) 305 is exposed, this second insulating barrier 305 of patterning (as develop) in TFT region, form run through this second insulating barrier 305 the first via hole 3051 and the second via hole 3052, in pixel electrode area, form and run through the first opening 3055 of this second insulating barrier 305, in via area, form the second opening 3053a that runs through this second insulating barrier 305.
Preferably, in step S5, also in via area, form the second opening 3054a that runs through this second insulating barrier 305 simultaneously.
S6, on the basis of step S5, to take this second insulating barrier 305 be mask, and the first insulating barrier 304 that etching (carving as dry) the second opening 3053a is exposed, to expose this first conductive pattern 3011.So just formed the 3rd via hole 3053 that runs through the first insulating barrier 304 and the second insulating barrier 305.Now, because the first opening 3055 belows are provided with the second semiconductor figure 3036, and the etching selection of the second semiconductor figure 3036 and the first insulating barrier 304 is larger, can be used as etching barrier layer, and the first insulating barrier 304 of its below can not be etched.
Preferably, in step S6, also simultaneously take this second insulating barrier 305 is mask, and the first insulating barrier 304 that etching (carving as dry) the second opening 3054a is exposed, to expose the 3rd conductive pattern 3012.So just formed the 5th via hole 3054 that runs through the first insulating barrier 304 and the second insulating barrier 305.
S7, on the basis of step S6, deposit one second conductive layer, this second conductive layer of patterning forms the second electrode pattern, this second electrode pattern comprises source electrode 3033, drain electrode the 3034, second conductive pattern 3021 of TFT, source electrode 3033 is connected with the first semiconductor figure 3032 by the first via hole 3051, drain electrode 3034 is connected with the first semiconductor figure 3032 by the second via hole 3052, and the second conductive pattern 3021 is connected with the first conductive pattern 3011 by the 3rd via hole 3053.Like this, the second conductive pattern 3021 is directly connected formed syndeton G by the 3rd via hole 3053 with the first conductive pattern 3011.
Preferably, step S7 also forms the 4th conductive pattern 3022 simultaneously, by the 5th via hole 3054, is connected with the 3rd conductive pattern 3012.
Except above-mentioned steps S1-S7, the manufacture method of the tft array substrate that the embodiment of the present invention four provides also comprises the steps:
S8, on the basis of step S7, deposit one the 3rd insulating barrier (being passivation layer) 306, patterning the 3rd insulating barrier 306 forms the 4th via hole 3061 in TFT region;
Preferably, step S8 also forms binding (bonding) region that the 6th via hole 3062, the six via holes 3062 run through passivation layer 306 are usually located at external circuitry (as FPC, IC) etc. simultaneously.
S9, on the basis of step S8, deposit one the 3rd conductive layer, patterning the 3rd conductive layer forms third electrode pattern, and third electrode pattern comprises the pixel electrode 3071 that is positioned at pixel electrode area.
Preferably, third electrode pattern also comprises that the 5th conductive pattern 3072, the five conductive patterns 3072 that are positioned at via area (being specially binding region) are connected with the 4th conductive pattern 3021 by the 6th via hole 3062.The 5th conductive pattern 3072, the 4th conductive pattern 3022, the 3rd conductive pattern 3021 form syndeton B(by the 6th via hole 3062 and the series connection of the 5th via hole 3054 respectively, and in fact a wherein part of syndeton B is identical with syndeton G).
From the processing step of the tft array substrate shown in above-mentioned Fig. 9, can find out, prepare the tft array substrate that comprises syndeton G shown in last width figure in Fig. 9, need to pass through step S1-S9, also only adopt 6 road lithographic process steps, processing step is simplified.
Embodiment five
The display floater that the embodiment of the present invention five provides, comprises the tft array substrate described in embodiment mono-or embodiment tri-.This display floater can be display panels, Electronic Paper or OLED display floater.
It should be noted that, in present specification, the implication of " ... on " is can directly contact, also can directly not contact.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (17)
1. a tft array substrate, comprising:
Substrate;
Be positioned at grid and the first conductive pattern on described substrate;
Cover the first insulating barrier of described grid, the first conductive pattern and substrate;
Be positioned on described the first insulating barrier, the first semiconductor figure of described grid top;
Cover the second insulating barrier of described the first semiconductor figure and the first insulating barrier, described the second insulating barrier is organic photo material;
The first via hole and the second via hole that run through described the second insulating barrier, run through the 3rd via hole of described the second insulating barrier and the first insulating barrier;
Be positioned at source electrode, drain electrode and the second conductive pattern on described the second insulating barrier;
Described source electrode is electrically connected to described the first semiconductor figure by described the first via hole, described drain electrode is electrically connected to described the first semiconductor figure by described the second via hole, and described the second conductive pattern is electrically connected to described the first conductive pattern by described the 3rd via hole.
2. tft array substrate according to claim 1, is characterized in that, described tft array substrate also comprises:
Cover the 3rd insulating barrier of described source electrode, drain electrode, the second conductive pattern and the second insulating barrier;
The 4th via hole that runs through described the 3rd insulating barrier;
Pixel electrode, is electrically connected to described drain/source by described the 4th via hole.
3. tft array substrate according to claim 1, is characterized in that, described tft array substrate also comprises:
Be positioned at the second semiconductor figure of same layer with described the first semiconductor figure;
The first opening that runs through described the second insulating barrier, is positioned at described the second semiconductor figure top.
4. tft array substrate according to claim 3, is characterized in that, described the first opening integral body is positioned at the scope of described the second semiconductor figure and exposes described the second semiconductor figure.
5. tft array substrate according to claim 3, is characterized in that, described tft array substrate also comprises:
Cover the 3rd insulating barrier of described source electrode, drain electrode, the second conductive pattern and the second insulating barrier;
The 4th via hole that runs through described the 3rd insulating barrier;
Pixel electrode, is electrically connected to described drain/source by described the 4th via hole;
At described the first opening part, described the 3rd insulating barrier and pixel electrode are set in turn on described the second semiconductor figure.
6. according to the tft array substrate described in claim 2 or 5, it is characterized in that, described pixel electrode adopts transparent conductive material or metal material.
7. according to the tft array substrate described in claim 2 or 5, it is characterized in that, described tft array substrate also comprises the public electrode that is positioned at same layer or different layers with described pixel electrode.
8. according to the tft array substrate described in claim 2 or 5, it is characterized in that, described tft array substrate also includes OLED.
9. according to the tft array substrate described in claim 1-5 any one, it is characterized in that, described the second conductive pattern is connected formed syndeton and is covered by described the 3rd insulating barrier with described the first conductive pattern by described the 3rd via hole.
10. according to the tft array substrate described in claim 1-5 any one, it is characterized in that, described tft array substrate also comprises:
Be positioned at the 3rd conductive pattern of same layer with described the first conductive pattern;
The 5th via hole that runs through described the second insulating barrier and the first insulating barrier;
Be positioned at the 4th conductive pattern of same layer with described the second conductive pattern;
Described the 4th conductive pattern is electrically connected to described the 3rd conductive pattern by described the 5th via hole.
11. according to the tft array substrate described in claim 10 any one, it is characterized in that, described tft array substrate also comprises the 5th conductive pattern that is positioned at same layer with described pixel electrode; The 6th via hole that runs through described the 3rd insulating barrier; Described the 5th conductive pattern is electrically connected to described the 4th conductive pattern by described the 6th via hole.
12. 1 kinds of display floaters, comprise the tft array substrate as described in claim 1-11 any one.
13. described display floaters according to claim 12, is characterized in that, described display floater is display panels or Electronic Paper or OLED display floater.
The manufacture method of 14. 1 kinds of tft array substrates, comprising:
S1, provide a substrate;
S2, deposition one first conductive layer, the first conductive layer forms the first electrode pattern described in patterning, and described the first electrode pattern comprises grid, the first conductive pattern;
S3, deposition one first insulating barrier, cover described the first electrode pattern;
S4, deposition semi-conductor layer, semiconductor layer forms the first semiconductor figure described in patterning;
The second insulating barrier of S5, deposition one organic photo material, the second insulating barrier forms the first via hole, the second via hole, the second opening that runs through described the second insulating barrier described in patterning;
S6, the second insulating barrier of described patterning of take are mask, and the first insulating barrier that the second opening exposes described in etching, exposes described the first conductive pattern, to form the 3rd via hole that runs through described the first insulating barrier and the second insulating barrier;
S7, deposition one second conductive layer, described in patterning, the second conductive layer forms the second electrode pattern, described the second electrode pattern comprises source electrode, drain electrode, the second conductive pattern, described source electrode is connected with described the first semiconductor figure by described the first via hole, described drain electrode is connected with described the first semiconductor figure by described the second via hole, and described the second conductive pattern is connected with described the first conductive pattern by described the 3rd via hole.
The manufacture method of 15. tft array substrates according to claim 14, is characterized in that, the manufacture method of described tft array substrate also comprises the steps:
S8, deposition one the 3rd insulating barrier, the 3rd insulating barrier forms the 4th via hole described in patterning;
S9, deposition one the 3rd conductive layer, the 3rd conductive layer forms third electrode pattern described in patterning, and described third electrode pattern comprises pixel electrode, and described pixel electrode is connected with described source/drain by described the 4th via hole.
The manufacture method of 16. tft array substrates according to claim 14, is characterized in that,
The first electrode pattern described in step S2 also comprises the 3rd conductive pattern;
In step S5, be also formed with the 3rd opening that runs through described the second insulating barrier;
The second insulating barrier of described patterning of also take in step S6 is mask, and the first insulating barrier that the 3rd opening exposes described in etching, exposes described the 3rd conductive pattern, to form the 5th via hole that runs through described the first insulating barrier and the second insulating barrier;
The second electrode pattern described in step S7 also comprises the 4th conductive pattern, by described the 5th via hole, is connected with described the 3rd conductive pattern.
The manufacture method of 17. tft array substrates according to claim 16, is characterized in that, the manufacture method of described tft array substrate also comprises the steps:
S8, deposition one the 3rd insulating barrier, the 3rd insulating barrier forms the 4th via hole and the 6th via hole described in patterning;
S9, deposition one the 3rd conductive layer, described in patterning, the 3rd conductive layer forms third electrode pattern, described third electrode pattern comprises pixel electrode and the 5th conductive pattern, described pixel electrode is connected with described drain electrode by described the 4th via hole, and described the 5th conductive pattern is connected with described the 4th conductive pattern by described the 6th via hole.
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