CN103928469B - TFT array substrate, manufacturing method thereof and display panel - Google Patents
TFT array substrate, manufacturing method thereof and display panel Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 139
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 230000004888 barrier function Effects 0.000 claims description 157
- 239000004065 semiconductor Substances 0.000 claims description 59
- 239000000463 material Substances 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 29
- 230000008021 deposition Effects 0.000 claims description 19
- 238000000059 patterning Methods 0.000 claims description 6
- 239000012780 transparent material Substances 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 3
- 239000007769 metal material Substances 0.000 claims description 3
- 208000034699 Vitreous floaters Diseases 0.000 claims 3
- 238000002360 preparation method Methods 0.000 abstract description 4
- 238000005530 etching Methods 0.000 description 19
- 239000012212 insulator Substances 0.000 description 11
- 238000002161 passivation Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 230000008569 process Effects 0.000 description 8
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000004020 conductor Substances 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 238000002834 transmittance Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 239000010453 quartz Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- -1 aluminum Chemical class 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000009738 saturating Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910001182 Mo alloy Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- ZXTFQUMXDQLMBY-UHFFFAOYSA-N alumane;molybdenum Chemical compound [AlH3].[Mo] ZXTFQUMXDQLMBY-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000003094 microcapsule Substances 0.000 description 1
- 235000016768 molybdenum Nutrition 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
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Abstract
The invention discloses a TFT array substrate with G-VIA through holes, a display panel and a preparation method of the TFT array substrate.
Description
Technical field
The present invention relates to active matrix (Active Matrix) field, particularly relate to a kind of tft array substrate, this TFT battle array
The manufacture method of row substrate, and comprise the display floater of this tft array substrate.
Background technology
Active-matrix substrate is typically to arrange thin film transistor (TFT) (Thin Film Transistor, TFT) on a substrate
Array, generally also can be referred to as tft array substrate.Tft array substrate is widely used in tablet device, including liquid crystal display
Panel (Liquid Crystal Display, LCD), Electronic Paper, Organic Light Emitting Diode (Organic Light Emitting
Diode, OLED) display floater, radioscopic image sensor (X Ray Image Sensor) etc..
The top view of the basic structure of tft array substrate 1 is as it is shown in figure 1, mainly include substrate 100, and is arranged at base
On plate 100 such as lower component: a plurality of grid line (gate line) 101；The a plurality of source line (source intersected with grid line 101 insulation
Line or data line) 102；It is arranged at grid line 101 and the TFT103 of source line 102 infall.
Generally tft array substrate 1 also includes pixel electrode (not shown in figure 1).Adjacent grid line 101 and adjacent source line 102
Area defined is pixel region, and pixel region includes TFT zone and pixel electrode area.This pixel electrode is arranged at pixel
In electrode zone, TFT is arranged in TFT zone.TFT103 couples with grid line 101 and the source line 102 of this infall, i.e. TFT103
Grid electrically connect with grid line 101, the source electrode of TFT103 electrically connects with source line 102；It addition, the drain electrode of TFT103 and pixel electrode
Electrical connection.
Fig. 2 is the process chart of a kind of tft array substrate of prior art.As in figure 2 it is shown, the TFT battle array of prior art
The processing step of row substrate is as follows:
A, provide a substrate 100；
B, on the substrate 100 deposition one first conductive layer, etch this first conductive layer and form the first electrode pattern, including grid
Line (not shown), grid 1031, first conductive pattern 1011 of TFT；
C, on the basis of step B deposit one covering whole substrate scope the first insulating barrier (i.e. gate insulator) 104,
This first insulating barrier 104 covers this first electrode pattern；
D, on the basis of step C deposit semi-conductor layer, etch this semiconductor layer formed TFT semiconductor figure
1032；
E, on the basis of step D, deposit one second insulating barrier (i.e. etching barrier layer) 105, etch this second insulating barrier
105 form the first via 1051 and the second via 1052 in TFT zone；
F, on the basis of step E, etch this first insulating barrier 104 and the second insulating barrier 105, form the in via area
Three vias 1053；
G, on the basis of step F deposit one second conductive layer, etch this second conductive layer and form the second electrode pattern, bag
Including the source electrode 1033 of TFT, drain electrode the 1034, second conductive pattern 1021, source electrode 1033 is by the first via 1051 and quasiconductor figure
Shape 1032 connects, and drain electrode 1034 is connected with semiconductor figure 1032 by the second via 1052, and the second conductive pattern 1021 passes through
3rd via 1053 is connected with the first conductive pattern 1011；
H, on the basis of step G deposit one the 3rd insulating barrier (i.e. passivation layer) 106, etch the 3rd insulating barrier 106 and exist
TFT zone forms the 4th via 1061, forms the 5th via 1062 in via area；
I, on the basis of step H deposit one the 3rd conductive layer, etch the 3rd conductive layer formed the 3rd electrode pattern, bag
Include the pixel electrode 1071 being positioned at pixel electrode area and the 3rd conductive pattern 1072 being positioned at via area, pixel electrode 1071
Being connected with drain electrode 1034 by the 4th via 1061, the 3rd conductive pattern 1072 is by the 5th via 1062 and the second conductive pattern
1021 connect.
From the tft array substrate structure of the prior art shown in above-mentioned Fig. 2 it can be seen that this tft array substrate includes
Three vias 1053, the 3rd via 1053 runs through etching barrier layer 105 and gate insulator 104, and the second conductive pattern 1021 passes through
3rd via 1053 is connected with the first conductive pattern 1011.Generally, the 3rd via 1053 can be referred to as G-VIA via, uses
In being directly connected to the first conductive pattern 1011 of layer with the second conductive pattern 1021 of layer with grid with source-drain electrode.
Material is thus formed the knot that the second conductive pattern 1021 is the most directly connected with the first conductive pattern 1011 by the 3rd via 1053
Structure.The gate driver circuit (such as amorphous oxides gate driver, AOG) be directly prepared in tft array substrate, being made up of TFT
Usually use this structure in Deng, such as, the source/drain of the grid of certain TFT with another TFT is attached.And grid
This structure in drive circuit is passivated layer 106 covering protection, reduces the electrostatic impact on gate driver circuit etc..Need
Bright, the via 1053 shown in Fig. 2 not passivated layer 106 cover, but are connected with the 3rd conductive pattern 1072, therefore
It not G-VIA via in gate driver circuit, but the via in the binding such as IC or FPC region.
From the processing step of the tft array substrate of the prior art shown in above-mentioned Fig. 2 it can be seen that in Fig. 2 to be prepared
Last tft array substrate shown in width figure, needs through step A-I, uses 7 road lithographic process steps, and processing step is more
Complicated.
Summary of the invention
Embodiments of the invention are to be solved be technical problem is that, the tft array substrate of the band G-VIA via of prior art
Step of preparation process complicated.
In order to solve above-mentioned technical problem, The embodiment provides a kind of tft array substrate, including: substrate；Position
Grid on described substrate and the first conductive pattern；Cover described grid, the first conductive pattern and the gate insulator of substrate；
It is positioned at the first semiconductor figure on described gate insulator, above described grid；Cover described first semiconductor figure and grid
Second insulating barrier of pole insulating barrier, described second insulating barrier is organic photosensitive material；Run through the first mistake of described second insulating barrier
Hole and the second via, run through the 3rd via of described second insulating barrier and gate insulator；It is positioned on described second insulating barrier
Source electrode, drain electrode and the second conductive pattern；Described source electrode is electrically connected with described first semiconductor figure by described first via,
Described drain electrode is electrically connected with described first semiconductor figure by described second via, and described second conductive pattern is by described the
Three vias electrically connect with described first conductive pattern.
Now, described tft array substrate can also include: covers described source electrode, drain electrode, the second conductive pattern and second exhausted
3rd insulating barrier of edge layer；Run through the 4th via of described 3rd insulating barrier；Pixel electrode, by described 4th via with described
Drain/source electrically connects.
Preferably, described tft array substrate also includes: is positioned at the second the half of same layer with described first semiconductor figure and leads
Volume graphic；Run through the first opening of described second insulating barrier, be positioned at above described second semiconductor figure.Wherein, described first
Opening is integrally located in the range of described second semiconductor figure and exposes described second semiconductor figure.Now, described TFT
Array base palte can also include: covers the 3rd insulating barrier of described source electrode, drain electrode, the second conductive pattern and the second insulating barrier；Pass through
Wear the 4th via of described 3rd insulating barrier；Pixel electrode, is electrically connected with described drain/source by described 4th via；?
Described first opening part, described 3rd insulating barrier and pixel electrode are set in turn on described second semiconductor figure.
Preferably, described pixel electrode uses transparent conductive material or metal material.
Preferably, described tft array substrate also includes being positioned at the common electrical of same layer or different layers with described pixel electrode
Pole.
Preferably, described tft array substrate also includes Organic Light Emitting Diode.
Preferably, in above-described embodiment, described second conductive pattern is by described 3rd via and described first conductive pattern
Shape connects the attachment structure formed and is covered by described 3rd insulating barrier.
Preferably, in above-described embodiment, described tft array substrate also includes: be positioned at same with described first conductive pattern
3rd conductive pattern of layer；Run through the 5th via of described second insulating barrier and gate insulator；With described second conductive pattern
It is positioned at the 4th conductive pattern of same layer；Described 4th conductive pattern is by described 5th via and described 3rd conductive pattern electricity
Connect.Now, described tft array substrate can further include and is positioned at the 6th conductive pattern of same layer with described pixel electrode
Shape；Run through the 6th via of described 3rd insulating barrier；Described 6th conductive pattern is led with the described 5th by described 6th via
Electrograph shape electrically connects.
Embodiments of the invention additionally provide a kind of display floater, tft array substrate described above.
Preferably, described display floater is display panels or Electronic Paper or OLED display panel.
Embodiments of the invention additionally provide a kind of method preparing above-mentioned tft array substrate, including:
S1, provide a substrate；S2, deposition one first conductive layer, pattern described first conductive layer and form the first electrode figure
Case, described first electrode pattern includes grid, the first conductive pattern；S3, deposition one first insulating barrier, cover described first electrode
Pattern；S4, deposition semi-conductor layer, pattern described semiconductor layer and form the first semiconductor figure；S5, deposit an organic photo
Second insulating barrier of material, patterns described second insulating barrier formation and runs through the first via of described second insulating barrier, the second mistake
Hole, the second opening；S6, with the second insulating barrier of described patterning as mask, etch that described second opening exposed first is exhausted
Edge layer, exposes described first conductive pattern, to form the 3rd via running through described first insulating barrier and the second insulating barrier；
S7, deposition one second conductive layer, pattern described second conductive layer and form the second electrode pattern, and described second electrode pattern includes
Source electrode, drain electrode, the second conductive pattern, described source electrode is connected with described first semiconductor figure by described first via, described
Drain electrode is connected with described first semiconductor figure by described second via, and described second conductive pattern passes through described 3rd via
It is connected with described first conductive pattern.
Preferably, the manufacture method of described tft array substrate also comprises the steps: S8, deposition one the 3rd insulating barrier, figure
Described in case, the 3rd insulating barrier forms the 4th via；S9, deposition one the 3rd conductive layer, pattern described 3rd conductive layer and form the
Three electrode patterns, described 3rd electrode pattern includes pixel electrode, and described pixel electrode is by described 4th via and described source
Pole/drain electrode connects.
Preferably, in the manufacture method of described tft array substrate, described in step S2, the first electrode pattern also includes the 3rd
Conductive pattern；Step S5 is also formed with running through the 3rd opening of described second insulating barrier；Also with described patterning in step S6
The second insulating barrier be mask, etch the first insulating barrier that described 3rd opening is exposed, expose described 3rd conductive pattern,
To form the 5th via running through described first insulating barrier and the second insulating barrier；Described in step S7, the second electrode pattern also includes
4th conductive pattern, is connected with described 3rd conductive pattern by described 5th via.Now, the system of described tft array substrate
The method of making farther includes following steps: S8, deposition one the 3rd insulating barrier, patterns described 3rd insulating barrier and forms the 4th via
With the 6th via；S9, deposition one the 3rd conductive layer, pattern described 3rd conductive layer formed the 3rd electrode pattern, the described 3rd
Electrode pattern includes pixel electrode and the 5th conductive pattern, and described pixel electrode is by described 4th via with described drain electrode even
Connecing, described 5th conductive pattern is connected with described 4th conductive pattern by described 6th via.
In terms of existing technologies, the tft array substrate that embodiments of the invention are provided, and comprise this TFT battle array
The display floater of row substrate, the preparation method of tft array substrate, owing to using organic photosensitive material to prepare tft array substrate
Etching barrier layer, uses this etching barrier layer to go out for connecting with source-drain electrode with the second conductive pattern of layer as mask etching simultaneously
Shape and with grid with the via (i.e. G-VIA via) of the first conductive pattern of layer, simplify processing step, reduce and produce into
This.
Accompanying drawing explanation
Fig. 1 is the top view of the basic structure of the tft array substrate of prior art；
Fig. 2 is the process chart of a kind of tft array substrate of prior art；
The plan structure schematic diagram of the tft array substrate that Fig. 3 provides for the embodiment of the present invention one；
The sectional structure schematic diagram of the tft array substrate including attachment structure G that Fig. 4 provides for the embodiment of the present invention one；
The sectional structure schematic diagram of the tft array substrate including attachment structure B that Fig. 5 provides for the embodiment of the present invention one；
The process chart of the tft array substrate that Fig. 6 provides for the embodiment of the present invention two；
The sectional structure schematic diagram of the tft array substrate including attachment structure G that Fig. 7 provides for the embodiment of the present invention three；
The sectional structure schematic diagram of the tft array substrate including attachment structure B that Fig. 8 provides for the embodiment of the present invention three；
The process chart of the tft array substrate that Fig. 9 provides for the embodiment of the present invention four.
Detailed description of the invention
The core concept of the present invention be in order to prepare the tft array substrate of band G-VIA via prepare in other words band connect knot
The tft array substrate of structure G, uses organic photosensitive material to prepare the etching barrier layer of tft array substrate, uses this etching to hinder simultaneously
Barrier as mask etching go out for connect with source-drain electrode with the second conductive pattern of layer and with grid with the first conductive pattern of layer
The via (i.e. G-VIA via) of shape, simplifies processing step, reduces production cost.
Embodiment one
The plan structure schematic diagram of the tft array substrate that the embodiment of the present invention one provides is as shown in Figure 3.From Fig. 3 permissible
Finding out, viewing area (Active Area) and encirclement should in plan structure for the tft array substrate that the embodiment of the present invention one provides
The outer peripheral areas (Non-Active Area) (not shown in Fig. 3) of viewing area.It mainly includes substrate 300, and is arranged at
The pel array of the viewing area on substrate 300, pel array includes such as lower component: a plurality of grid line (gate line) 301；With
The a plurality of source line (source line) 302 that grid line 301 insulation intersects；It is arranged at grid line 301 and source line 302 infall
TFT303。
The generally pel array of tft array substrate 3 also includes pixel electrode (not shown in Fig. 3).Adjacent grid line 301 and phase
Adjacent source line 302 area defined is pixel region, and pixel region includes TFT zone and pixel electrode area.This pixel electrode
Being arranged in pixel electrode area, TFT is arranged in TFT zone, and TFT can be with only one of which (such as display panels, electronics
In paper), can also have multiple (such as in OLED display panel).In a pixel region only one of which as switch TFT
As a example by, as it is shown on figure 3, TFT303 couples with grid line 301 and the source line 302 of this infall, i.e. the grid of TFT303 and grid line 301
Electrical connection, the source electrode of TFT303 electrically connects with source line 302.
It should be noted that Fig. 3 illustrate only the tft array substrate plan structure that the present invention provides, but this area
Technical staff can be according to the common knowledge of this area, and the plan structure of tft array substrate can have multiple different change
Shape, does not do too much elaboration at this.
The sectional structure schematic diagram of the tft array substrate that the embodiment of the present invention one provides is as shown in Figure 4.From Fig. 4 permissible
Finding out, the tft array substrate that the embodiment of the present invention one provides includes:
Substrate 300；
The grid 3031 being positioned on substrate 300 and the first conductive pattern 3011；
Cover grid the 3031, first conductive pattern 3011 and the first insulating barrier 304 of substrate 300；
It is positioned at the first semiconductor figure 3032 on the first insulating barrier 304, above grid 3031；
Covering the first semiconductor figure 3032 and the second insulating barrier 305 of the first insulating barrier 304, the second insulating barrier 305 is
Organic photosensitive material；
Run through the first via 3051 and the second via 3052 of the second insulating barrier 305, run through the second insulating barrier 305 and first
3rd via 3053 of insulating barrier 304；
Source electrode 3033, drain electrode 3034 and the second conductive pattern 3021 being positioned on the second insulating barrier；
Source electrode 3033 is electrically connected with the first semiconductor figure 3032 by the first via 3051, and drain electrode 3034 is by the second mistake
Hole 3052 electrically connects with the first semiconductor figure 3032, and the second conductive pattern 3021 is by the 3rd via 3053 and the first conductive pattern
Shape 3011 electrically connects.
Specifically, substrate 300 generally uses the transparent material such as glass, quartz；Substrate 300 can also by use glass,
The transparent materials such as quartz and other structures thereon (such as cushion etc.) are constituted.Grid 3031 and the first conductive pattern 3011 are usual
It is located immediately on the surface of substrate 300.The grid 3031 of TFT and the first conductive pattern 3011 and grid line 301 are usually located at same
One layer, use identical material, such as metals such as aluminum, therefore can prepare in same processing step.
First insulating barrier (i.e. gate insulator) 304 generally covers whole substrate scope, and material can be silicon dioxide.
First semiconductor figure 3032 usually island, material can be non-crystalline silicon, polysilicon, oxide semiconductor etc..
Second insulating barrier (i.e. etching barrier layer) 305 generally covers whole substrate scope, and material is organic photosensitive material.The
Two insulating barriers 305 cover the first semiconductor figure 3032, so subsequent etching prepare TFT source electrode 3033, drain 3034 time
Prevent from the first semiconductor figure 3032 is caused etching, therefore can be referred to as etching barrier layer.
Source electrode 3033, drain electrode the 3034, second conductive pattern 3021 are usually located at same layer with source line 302, use identical
Material, such as metals such as molybdenums, therefore can prepare in same processing step.It is of course also possible to be 3034 for source electrode, 3033 is leakage
Pole.
Second insulating barrier 305 uses organic photosensitive material, on the one hand has photobehavior due to itself, is formed wherein
First via 3051 and the second via 3052, and the 3rd via 3053 is positioned at the part of the second insulating barrier (in embodiment two
Second opening) time, it is only necessary to expose, develop, the step such as post bake, it is not necessary to etch step, technique can simplify；The opposing party
Face directly performs etching as mask after formation the 3rd via 3053 is positioned at the part of the second insulating barrier, it is not necessary to extra
Photoetching process just can form the 3rd via 3053 and be positioned at the part of gate insulator, namely forms the 3rd complete via
3053, technique can simplify further.Concrete technology step can participate in embodiment two.
Fig. 4 also show preferred parts, i.e. tft array substrate 3 be additionally included in whole substrate scope, cover described source
3rd insulating barrier (i.e. passivation layer) 306 of pole, drain electrode, the second conductive pattern and the second insulating barrier；Run through the 4th of passivation layer 306 the
Via 3061；Pixel electrode 3071, is electrically connected with drain electrode 3034 by the 4th via 3061.The material of passivation layer 306 can be
Silicon oxide or silicon nitride.Pixel electrode 3071 can be transparent conductive material, such as ITO, IZO etc.；It can also be opaque gold
Belong to material, such as Ag etc..Certainly tft array substrate can also include other structures, such as IPS(in plane switching) liquid
Tft array substrate in LCD panel includes being positioned at the public electrode of same layer with pixel electrode 3071；FFS(fringe
Filed switching) tft array substrate in display panels includes being positioned at the public of different layers with pixel electrode 3071
Electrode；OLED(organic light emitting diode) display floater also includes Organic Light Emitting Diode, tft array base
The pixel electrode 3071 of plate is the male or female of Organic Light Emitting Diode.
It addition, the second conductive pattern 3021 is directly connected with the first conductive pattern 3011 by the 3rd via 3053 in Fig. 4
In the attachment structure G(Fig. 4 formed shown in dotted line frame) it is passivated layer 306 and covers.This attachment structure G is generally formed in directly system
In standby pixel-driving circuit in the gate driver circuit or OLED display panel of tft array substrate, because in these circuit
The source/drain by the grid of certain TFT with another TFT is usually needed to be electrically connected.This in gate driver circuit connects
Access node structure G is passivated layer 106 covering protection, reduces the electrostatic adverse effect to gate driver circuit etc..
As one preferred embodiment, the embodiment of the present invention one provide tft array substrate via area except
Not shown in attachment structure G(Fig. 5 shown in Fig. 4) outside, it is also possible to include another kind of attachment structure B as shown in Figure 5.From figure
It can be seen that the tft array substrate that the embodiment of the present invention one provides also includes and the first conductive pattern 3011 in via area in 5
It is positioned at the 3rd conductive pattern 3012 of same layer；Run through the second insulating barrier 305 and the 5th via 3054 of the first insulating barrier 304；
With the 4th conductive pattern 3022 that the second conductive pattern 3021 is positioned at same layer；4th conductive pattern 3022 is by the 5th via
3054 electrically connect with the 3rd conductive pattern 3012.
It addition, tft array substrate also includes the 6th via 3063 running through passivation layer 306；5th conductive pattern 3072 is logical
Normal and pixel electrode 3071 is positioned at same layer, uses identical material, can prepare in same processing step.5th conductive pattern
Shape 3072 is connected with the 4th conductive pattern 3022 by the 6th via 3063.Attachment structure B shown in Fig. 5 includes two vias
3054 and 3063, and the 3rd conductive pattern the 3012, the 4th being sequentially connected with is to electrograph shape 3022 and the 5th conductive pattern 3072.
5th via 3054 and the 6th via 3063 may be located at same position (as shown in Figure 5), it is also possible to be positioned at various location.
Attachment structure B is usually located at binding (bonding) region, for being connected with external circuitry (such as FPC, IC).Certainly, attachment structure
Two vias 3054 and 3063 that B is comprised can not the most co-located place (i.e. the two vertical overlapping),
5th via 3054 may be located at diverse location with the 6th via 3063, and (i.e. the two is the most overlapping vertical, even completely wrong
Open).
Embodiment two
The process chart of the tft array substrate that the embodiment of the present invention two provides is as shown in Figure 6.From fig. 6 it can be seen that
The step of preparation process of the tft array substrate that the embodiment of the present invention two provides is as follows:
S1, provide a substrate 300；Wherein, substrate 300 generally uses the transparent material such as glass, quartz, or by using glass
The transparent material such as glass, quartz and other structures thereon (such as cushion etc.) are constituted.
S2, on the substrate 300 deposition one first conductive layer (not shown), pattern this first conductive layer and form first
Electrode pattern, the first electrode pattern includes grid 3031, first conductive pattern 3011 of TFT；Wherein, this first conductive layer is permissible
Use the metal such as aluminum, aluminium molybdenum alloys.First electrode pattern can also include grid line (not shown).Preferably, the first electrode
Pattern also includes the 3rd conductive pattern 3012.
S3, on the basis of step S2 deposit one covering whole substrate scope the first insulating barrier (i.e. gate insulator)
304, this first insulating barrier 304 covers this first electrode pattern；Wherein, the first insulating barrier (i.e. gate insulator) 304 can be
Silicon dioxide.
S4, on the basis of step S3, deposit semi-conductor layer, pattern this semiconductor layer and form the first half in TFT zone
Conductor fig 3032；Wherein, the first semiconductor figure 3032 usually island, material can be non-crystalline silicon, polysilicon, oxide
Quasiconductor etc..
S5, on the basis of step S4, deposit second insulating barrier (i.e. etching barrier layer) 305 of an organic photosensitive material, right
This second insulating barrier (i.e. etching barrier layer) 305 is exposed, and patterning (such as development) this second insulating barrier 305 is in TFT zone
Formed run through the first via 3051 of this second insulating barrier 305 and the second via 3052, via area formed run through this second
Second opening 3053a of insulating barrier 305.
Preferably, run through the 3rd opening of this second insulating barrier 305 in step s 5 in via area formation the most simultaneously
3054a.Generally, the second opening 3053a is formed at the gate driving circuit region of tft array substrate or the pixel driver electricity of OLED
Region, road, because usually needing the source/drain by the grid of certain TFT with another TFT to be electrically connected in these circuit.
In step S5, owing to the second insulating barrier 305 uses organic photosensitive material, form the first via 3051 and the second via wherein
3052, and when the second opening 3053a, the 3rd opening 3054a, it is only necessary to expose, develop, the step such as post bake, it is not necessary to
Etch step, technique can simplify.
S6, on the basis of step S5 with this second insulating barrier 305 as mask, etch (such as dry etching) second opening 3053a
The first insulating barrier 304 exposed, to expose this first conductive pattern 3011.Material is thus formed and run through the first insulating barrier
304 and second the 3rd via 3053 of insulating barrier 305.
Preferably, in step s 6 the most simultaneously with this second insulating barrier 305 as mask, etch (such as dry etching) the 3rd opening
The first insulating barrier 304 that 3054a is exposed, to expose the 3rd conductive pattern 3012.Material is thus formed that to run through first exhausted
Edge layer 304 and the 5th via 3054 of the second insulating barrier 305.
S7, on the basis of step S6 deposit one second conductive layer, pattern this second conductive layer and form the second electrode figure
Case, this second electrode pattern includes the source electrode 3033 of TFT, drain electrode the 3034, second conductive pattern 3021, and source electrode 3033 is by first
Via 3051 is connected with the first semiconductor figure 3032, and drain electrode 3034 is by the second via 3052 and the first semiconductor figure 3032
Connecting, the second conductive pattern 3021 is connected with the first conductive pattern 3011 by the 3rd via 3053.It is of course also possible to be 3034
For source electrode, 3033 is drain electrode.So, the second conductive pattern 3021 is directly by the 3rd via 3053 and the first conductive pattern 3011
Connect attachment structure G formed.Gate driving circuit region that this attachment structure G is generally formed in tft array substrate or
The pixel-driving circuit region of oled panel.This second electrode pattern can also include source line.
Preferably, this second electrode pattern also includes the 4th conductive pattern 3022, is led with the 3rd by the 5th via 3054
Electrograph shape 3012 connects.
In addition to above-mentioned steps S1-S7, the manufacture method of the tft array substrate that the embodiment of the present invention two provides also includes
Following steps:
S8, on the basis of step S7 deposit one the 3rd insulating barrier (i.e. passivation layer) 306, pattern the 3rd insulating barrier
306 form the 4th via 3061 in TFT zone；Wherein, the second conductive pattern 3021 is directly by the 3rd via 3053 and first
Attachment structure G that conductive pattern 3011 connection is formed is passivated layer 306 and covers, and does not subject to electrostatic damage.
Preferably, step S8 also concurrently forms the 6th via 3062 running through passivation layer 306, the 6th usual position of via 3062
Binding (bonding) region in external circuitry (such as FPC, IC) etc..Wherein, the 6th via 3062 is permissible with the 5th via 3054
The most co-located place (i.e. the two overlap on vertical), it is also possible to (i.e. the two is on vertical to be positioned at diverse location
The most overlapping, stagger the most completely).
S9, on the basis of step S8 deposit one the 3rd conductive layer, pattern the 3rd conductive layer formed the 3rd electrode figure
Case, the 3rd electrode pattern includes the pixel electrode 3071 being positioned at pixel electrode area.Wherein, pixel electrode 3071 is by the 4th mistake
Hole 3061 is connected with the drain electrode 3034 of TFT.
Preferably, the 3rd electrode pattern also includes the 5th conductive pattern being positioned at via area (specially binding region)
3072, the 5th conductive pattern 3072 is connected with the 4th conductive pattern 3022 by the 6th via 3062.5th conductive pattern 3072,
4th conductive pattern the 3022, the 3rd conductive pattern 3021 is formed even by the 6th via 3062 and the series connection of the 5th via 3054 respectively
A portion of access node structure B(actually attachment structure B is identical with attachment structure G).In this step, the material of the 3rd conductive layer
Can be transparent conductive material, such as ITO, IZO etc., now pixel electrode 3071 can be as the picture of transmissive liquid crystal display panel
Element electrode, it is also possible to for the anode/cathode of oled panel.The material of the 3rd conductive layer can be metal material, such as Al, Ag etc.,
Reflecting type liquid crystal display panel, the pixel electrode of Electronic Paper, it is also possible to for the anode/cathode of oled panel.
For display panels, include after step S9 preparing oriented layer, becoming the traditional handicrafts such as box, at this no longer
Repeat.For FFS type display panels, also include the conventional procedures preparing public electrode, do not repeat them here.
For Electronic Paper, include after step S9 pasting the traditional handicrafts such as microcapsule layer, do not repeat them here.
For oled panel, include after step S9 preparing the traditional handicraft such as pixel defining layer, organic luminous layer,
This repeats no more.
Last width figure from the processing step of the tft array substrate shown in above-mentioned Fig. 6 it can be seen that in Fig. 6 to be prepared
The shown tft array substrate including attachment structure G, needs through step S1-S9, uses 6 road lithographic process steps, and technique walks
Suddenly it is simplified.
Embodiment three
The tft array substrate that the tft array substrate that the embodiment of the present invention three provides provides in embodiment one is made that improvement,
The part identical with embodiment one no longer repeats, and is described below in place of its difference:
Sectional structure schematic diagram such as Fig. 7 institute of the tft array substrate including attachment structure G that the embodiment of the present invention three provides
Showing, the sectional structure schematic diagram of the tft array substrate including attachment structure B that the embodiment of the present invention three provides is as shown in Figure 8.From
It can be seen that on the basis of the tft array substrate embodiment one that provides of the embodiment of the present invention three in Fig. 7 and Fig. 8, saturating in pixel
Light region arranges one second semiconductor figure 3036, is positioned at same layer with the first semiconductor figure 3032, uses identical material,
Therefore can prepare in same processing step.It is positioned at the second insulating barrier 305 above this second semiconductor figure 3036 to have
First opening 3055.First opening 3055 size is typically slightly less than this second semiconductor figure 3036 and exposes the second quasiconductor
Figure 3036, the 3rd insulating barrier 306 covers whole first opening 3055 and the second semiconductor figure 3036 come out.
It should be noted that as shown in Figure 4,5, 6, the second insulating barrier constituted due to organic photosensitive material (i.e. etches resistance
Barrier) 305 after overexposure usual transmitance poor, if pixel region is covered by the second insulating barrier 305, light saturating
The rate of mistake will be very poor, and the light transmittance of the display floater of the tft array substrate provided including embodiment one will be very poor.Therefore real
The tft array substrate that executing example three provides eliminates the second insulating barrier of pixel transmittance region (at the specially first opening 3055)
305, thus substantially increase light transmittance.But simultaneously because it is provided with the second semiconductor figure below the first opening 3055
3036, the first opening 3055 is integrally located in the range of the second semiconductor figure 3036, not by lower section at the first opening 3055
The first insulating barrier 304 come out, thus avoid with the second insulating barrier 305 as mask, etch (such as dry etching) second
By first insulating barrier in pixel transmittance region during the first insulating barrier 304 that opening 3053a and/or the 3rd opening 3054a is exposed
304 also etch away.Concrete processing step is shown in embodiment four.
Preferably, such as embodiment three, embodiment four can also include passivation layer 306 and pixel electrode 3071, difference
Place is, in embodiment four, at the first opening 3055, passivation layer 306 and pixel electrode 3071 are set in turn in the second quasiconductor
On figure 3036.
Embodiment four
The technological process (as shown in Figure 9) of the tft array substrate that the embodiment of the present invention four provides provides in embodiment two
Being made that improvement on the basis of the technological process of tft array substrate, the part identical with embodiment two no longer repeats, and it distinguishes it
Place is described below:
S1, provide a substrate 300；
S2, on the substrate 300 deposition one first conductive layer, pattern this first conductive layer and form the first electrode pattern, the
One electrode pattern includes grid 3031, first conductive pattern 3011 of grid line (not shown), TFT；Preferably, the first electrode
Pattern also includes the 3rd conductive pattern 3012.
S3, on the basis of step S2 deposit one covering whole substrate scope the first insulating barrier (i.e. gate insulator)
304, this first insulating barrier 304 covers this first electrode pattern；
S4, on the basis of step S3, deposit semi-conductor layer, pattern this semiconductor layer and form the first half in TFT zone
Conductor fig 3032, form the second semiconductor figure 3036 in pixel electrode area (or pixel transmittance region)；
S5, on the basis of step S4, deposit second insulating barrier (i.e. etching barrier layer) 305 of an organic photosensitive material, right
This second insulating barrier (i.e. etching barrier layer) 305 is exposed, and patterning (such as development) this second insulating barrier 305 is in TFT zone
Formation runs through the first via 3051 and second via 3052 of this second insulating barrier 305, is formed in pixel electrode area and run through this
First opening 3055 of the second insulating barrier 305, form the second opening 3053a running through this second insulating barrier 305 in via area.
Preferably, run through the second opening of this second insulating barrier 305 in step s 5 in via area formation the most simultaneously
3054a。
S6, on the basis of step S5 with this second insulating barrier 305 as mask, etch (such as dry etching) second opening 3053a
The first insulating barrier 304 exposed, to expose this first conductive pattern 3011.Material is thus formed and run through the first insulating barrier
304 and second the 3rd via 3053 of insulating barrier 305.Now, owing to being provided with the second quasiconductor figure below the first opening 3055
Shape 3036, and the second semiconductor figure 3036 is bigger with the etching selection of the first insulating barrier 304, can as etching barrier layer,
The first insulating barrier 304 below will not be etched.
Preferably, in step s 6 the most simultaneously with this second insulating barrier 305 as mask, etch (such as dry etching) second opening
The first insulating barrier 304 that 3054a is exposed, to expose the 3rd conductive pattern 3012.Material is thus formed that to run through first exhausted
Edge layer 304 and the 5th via 3054 of the second insulating barrier 305.
S7, on the basis of step S6 deposit one second conductive layer, pattern this second conductive layer and form the second electrode figure
Case, this second electrode pattern includes the source electrode 3033 of TFT, drain electrode the 3034, second conductive pattern 3021, and source electrode 3033 is by first
Via 3051 is connected with the first semiconductor figure 3032, and drain electrode 3034 is by the second via 3052 and the first semiconductor figure 3032
Connecting, the second conductive pattern 3021 is connected with the first conductive pattern 3011 by the 3rd via 3053.So, the second conductive pattern
3021 are directly connected formed attachment structure G by the 3rd via 3053 with the first conductive pattern 3011.
Preferably, step S7 also concurrently forms the 4th conductive pattern 3022, by the 5th via 3054 and the 3rd conductive pattern
Shape 3012 connects.
In addition to above-mentioned steps S1-S7, the manufacture method of the tft array substrate that the embodiment of the present invention four provides also includes
Following steps:
S8, on the basis of step S7 deposit one the 3rd insulating barrier (i.e. passivation layer) 306, pattern the 3rd insulating barrier
306 form the 4th via 3061 in TFT zone；
Preferably, step S8 also concurrently forms the 6th via 3062 running through passivation layer 306, the 6th usual position of via 3062
Binding (bonding) region in external circuitry (such as FPC, IC) etc..
S9, on the basis of step S8 deposit one the 3rd conductive layer, pattern the 3rd conductive layer formed the 3rd electrode figure
Case, the 3rd electrode pattern includes the pixel electrode 3071 being positioned at pixel electrode area.
Preferably, the 3rd electrode pattern also includes the 5th conductive pattern being positioned at via area (specially binding region)
3072, the 5th conductive pattern 3072 is connected with the 4th conductive pattern 3021 by the 6th via 3062.5th conductive pattern 3072,
4th conductive pattern the 3022, the 3rd conductive pattern 3021 is formed even by the 6th via 3062 and the series connection of the 5th via 3054 respectively
A portion of access node structure B(actually attachment structure B is identical with attachment structure G).
Last width figure from the processing step of the tft array substrate shown in above-mentioned Fig. 9 it can be seen that in Fig. 9 to be prepared
The shown tft array substrate including attachment structure G, needs through step S1-S9, also only with 6 road lithographic process steps, work
Skill step is simplified.
Embodiment five
The display floater that the embodiment of the present invention five provides, including the tft array substrate described in embodiment one or embodiment three.
This display floater can be display panels, Electronic Paper or OLED display panel.
It should be noted that present specification is meant that " on ... " and can directly contact, can not also directly connect
Touch.
Obviously, those skilled in the art can carry out various change and the modification essence without deviating from the present invention to the present invention
God and scope.So, if these amendments of the present invention and modification belong to the scope of the claims in the present invention and equivalent technologies thereof
Within, then the present invention is also intended to comprise these change and modification.
Claims (17)
1. a tft array substrate, including:
Substrate；
It is positioned at the grid on described substrate and the first conductive pattern；
Cover the first insulating barrier of described grid, the first conductive pattern and substrate；
It is positioned at the first semiconductor figure on described first insulating barrier, above described grid；
Covering the second insulating barrier of described first semiconductor figure and the first insulating barrier, described second insulating barrier is organic photo material
Material；
Run through the first via and second via of described second insulating barrier, run through the of described second insulating barrier and the first insulating barrier
Three vias；
It is positioned at the source electrode on described second insulating barrier, drain electrode and the second conductive pattern；
Described source electrode is electrically connected with described first semiconductor figure by described first via, and described drain electrode is by described second mistake
Hole electrically connects with described first semiconductor figure, and described second conductive pattern is by described 3rd via and described first conductive pattern
Shape electrically connects.
Tft array substrate the most according to claim 1, it is characterised in that described tft array substrate also includes:
Cover the 3rd insulating barrier of described source electrode, drain electrode, the second conductive pattern and the second insulating barrier；
Run through the 4th via of described 3rd insulating barrier；
Pixel electrode, is electrically connected with described drain/source by described 4th via.
Tft array substrate the most according to claim 1, it is characterised in that described tft array substrate also includes:
With the second semiconductor figure that described first semiconductor figure is positioned at same layer；
Run through the first opening of described second insulating barrier, be positioned at above described second semiconductor figure.
Tft array substrate the most according to claim 3, it is characterised in that described first opening is integrally located at described second
In the range of semiconductor figure and expose described second semiconductor figure.
Tft array substrate the most according to claim 3, it is characterised in that described tft array substrate also includes:
Cover the 3rd insulating barrier of described source electrode, drain electrode, the second conductive pattern and the second insulating barrier；
Run through the 4th via of described 3rd insulating barrier；
Pixel electrode, is electrically connected with described drain/source by described 4th via；
At described first opening part, described 3rd insulating barrier and pixel electrode are set in turn on described second semiconductor figure.
6. according to the tft array substrate described in claim 2 or 5, it is characterised in that described pixel electrode uses electrically conducting transparent material
Material or metal material.
7. according to the tft array substrate described in claim 2 or 5, it is characterised in that described tft array substrate also includes and institute
State pixel electrode and be positioned at the public electrode of same layer or different layers.
8. according to the tft array substrate described in claim 2 or 5, it is characterised in that described tft array substrate also includes organic
Light emitting diode.
9. according to the tft array substrate described in claim 2 or 5, it is characterised in that described second conductive pattern is by described the
Three vias are connected formed attachment structure with described first conductive pattern and are covered by described 3rd insulating barrier.
10. according to the tft array substrate described in claim 2 or 5, it is characterised in that described tft array substrate also includes:
With the 3rd conductive pattern that described first conductive pattern is positioned at same layer；
Run through the 5th via of described second insulating barrier and the first insulating barrier；
With the 4th conductive pattern that described second conductive pattern is positioned at same layer；
Described 4th conductive pattern is electrically connected with described 3rd conductive pattern by described 5th via.
11. tft array substrates according to claim 10, it is characterised in that described tft array substrate also includes with described
Pixel electrode is positioned at the 5th conductive pattern of same layer；Run through the 6th via of described 3rd insulating barrier；Described 5th conductive pattern
Shape is electrically connected with described 4th conductive pattern by described 6th via.
12. 1 kinds of display floaters, including the tft array substrate as described in any one of claim 1-11.
13. display floaters according to claim 12, it is characterised in that described display floater is display panels or electricity
Sub-paper or OLED display panel.
The manufacture method of 14. 1 kinds of tft array substrates, including:
S1, provide a substrate；
S2, deposition one first conductive layer, pattern described first conductive layer and form the first electrode pattern, described first electrode pattern
Including grid, the first conductive pattern；
S3, deposition one first insulating barrier, cover described first electrode pattern；
S4, deposition semi-conductor layer, pattern described semiconductor layer and form the first semiconductor figure；
S5, deposit the second insulating barrier of an organic photosensitive material, pattern described second insulating barrier and formed and run through described second exhausted
First via of edge layer, the second via, the second opening；
S6, with the second insulating barrier of described patterning as mask, etch the first insulating barrier that described second opening is exposed, expose
Go out described first conductive pattern, to form the 3rd via running through described first insulating barrier and the second insulating barrier；
S7, deposition one second conductive layer, pattern described second conductive layer and form the second electrode pattern, described second electrode pattern
Including source electrode, drain electrode, the second conductive pattern, described source electrode is connected with described first semiconductor figure by described first via,
Described drain electrode is connected with described first semiconductor figure by described second via, and described second conductive pattern passes through the described 3rd
Via is connected with described first conductive pattern.
The manufacture method of 15. tft array substrates according to claim 14, it is characterised in that described tft array substrate
Manufacture method also comprises the steps:
S8, deposition one the 3rd insulating barrier, pattern described 3rd insulating barrier and form the 4th via；
S9, deposition one the 3rd conductive layer, pattern described 3rd conductive layer and form the 3rd electrode pattern, described 3rd electrode pattern
Including pixel electrode, described pixel electrode is connected with described source/drain by described 4th via.
The manufacture method of 16. tft array substrates according to claim 14, it is characterised in that
Described in step S2, the first electrode pattern also includes the 3rd conductive pattern；
Step S5 is also formed with running through the 3rd opening of described second insulating barrier；
Also with the second insulating barrier of described patterning as mask in step S6, etch the first insulation that described 3rd opening is exposed
Layer, exposes described 3rd conductive pattern, to form the 5th via running through described first insulating barrier and the second insulating barrier；
Described in step S7, the second electrode pattern also includes the 4th conductive pattern, by described 5th via and described 3rd conduction
Figure connects.
The manufacture method of 17. tft array substrates according to claim 16, it is characterised in that described tft array substrate
Manufacture method also comprises the steps:
S8, deposition one the 3rd insulating barrier, pattern described 3rd insulating barrier and form the 4th via and the 6th via；
S9, deposition one the 3rd conductive layer, pattern described 3rd conductive layer and form the 3rd electrode pattern, described 3rd electrode pattern
Including pixel electrode and the 5th conductive pattern, described pixel electrode is connected with described drain electrode by described 4th via, and described the
Five conductive patterns are connected with described 4th conductive pattern by described 6th via.
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| CN106783869B (en) * | 2016-09-07 | 2019-11-22 | 武汉华星光电技术有限公司 | Thin-film transistor array base-plate and its manufacturing method |
| US10192909B2 (en) | 2017-04-17 | 2019-01-29 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Array substrate structure and manufacturing method of array substrate |
| CN106932986B (en) * | 2017-04-17 | 2019-04-02 | 深圳市华星光电半导体显示技术有限公司 | The preparation method of array base-plate structure and array substrate |
| CN106941093B (en) * | 2017-05-12 | 2019-10-11 | 京东方科技集团股份有限公司 | Display device, array substrate and its manufacturing method |
| CN107359177B (en) * | 2017-06-28 | 2020-03-31 | 武汉华星光电半导体显示技术有限公司 | Manufacturing method of flexible back plate, liquid crystal display panel and OLED display panel |
| CN110176429B (en) * | 2019-04-08 | 2021-04-13 | 北海惠科光电技术有限公司 | Manufacturing method of array substrate, array substrate and display panel |
| WO2021189247A1 (en) | 2020-03-24 | 2021-09-30 | 京东方科技集团股份有限公司 | Display substrate and manufacturing method therefor, and display panel |
| CN113113430A (en) * | 2021-03-30 | 2021-07-13 | Tcl华星光电技术有限公司 | Array substrate, manufacturing method thereof and display panel |
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