1321853 九、發明說明： 【發明所屬之技術領域】 .本發明係關於一種薄膜電晶體基板及其製造方法❶ 【先前技術】 液晶顯示裝置具有低輻射性、體積輕薄短小及耗電低 等眾多優點’故於使用上日漸廣& ’同時仍具有視角各向 異性和視角範圍較小的弱點，即在離開顯示面板法線方向 觀察時，對比度明顯下降；在彩色顯示時，㈣大時還會 發生灰階反轉的現象。在液晶顯示裝置向大尺寸發展的情 況下’這-弱點尤為突出。邊緣電場開關型液晶顯示器克 服了這-缺點，則邊緣電場開關型液晶顯示器的應用日漸 廣泛。邊緣電場開關型液晶顯示器主要包括一液晶顯示面 板及為該液晶顯示面板提供光源之背光模組。該液晶顯示 面板包括-薄臈電晶體基板、—彩色濾光片基板及夹於該 薄膜電晶體基板與該彩色濾、光片基板之間之液晶層。該 膜電晶體基板靠近該m側設置依序設置—像素電極 及一對向電極，該像素電極與該對向電極共同作用以 該液晶層之偏轉。 工 母晝素元件100包括一對向電極120 請參閱圖1，係一種先前技術薄膜電晶體基板之处構 示意圖。該薄膜電晶體基板10包括複數閘極線13、^數 公共電極線及複數資料線17。該複數公共電極線14斑 該複數閘極線間隔設置’且相互平行。該複數閘極線 13與該複數資料線17垂直絕緣相交，界定複數書 100。每一書去开杜，A k ______ ~ ^ —薄膜電晶 7 1321853 體180及複數像素電極19〇。該薄膜電晶體包括一閘 極181、一源極182、一汲極183及一導通孔184。該導通 孔184電性導通該汲極183與該像素電極19〇。該對向電 極120為具有一定圖案之透明導電層，其與該公共電極線 14部份重疊，且電導通。 士請一併參閱圖2，係圖1沿該IMI線之剖面示意圖。 該薄膜電晶體基板1〇進一步包括一絕緣基底n、一閘極 絕緣層15、一半導體層1〇7及一保護層16。該閘極線13、 該公共電極線14、該閘極181及該對向電極12〇均設置於 該絕緣基底11上。該閘極絕緣層15覆蓋該對向電極12〇、 該複數閘極線13、該閘極181及該複數公共電極線14。該 半導體層107沉積在該閘極絕緣層15上，且與該閘極ΐ8ι 對應。該源極182及汲極183對應該閘極181設置於該半 導體層107上。該保護層16覆蓋該閘極絕緣層15、該源 極182=該汲極183。該像素電極19〇設置於該保護層μ 上，且藉由該導通孔184與該汲極183電連接。 請參閱圖3,係該薄膜電晶體基板1〇之傳統製造方法 之流程圖。該製造方法採用六道光罩製程，包括以下步驟： 一、第一道光罩 步驟S1 :形成透明導電層； 提供一絕緣基底11，在該絕緣基底11上，依序形成 一透明導電層及一第一光阻層。 步驟S2 :形成對向電極； 以第-光罩的圖案對該第一光阻層進行曝光並顯影， 8 1321853 ，：成-預定光阻圖案；對該透明導電層進行祕刻，形成 對向電極120，移去光阻層。惟，該透明導電層是以濕 y方式來似彳’ n似彳方式易似彳不完全，從而製程 導電層，如一殘留塊121。 二、第二道光罩 步驟S3 :形成金屬層；1321853 IX. Description of the Invention: [Technical Field] The present invention relates to a thin film transistor substrate and a method of manufacturing the same. [Prior Art] The liquid crystal display device has many advantages such as low radiation, small size, short power consumption, and low power consumption. 'Therefore, the use of the day is getting wider & 'At the same time, there is still a weak point of view anisotropy and a small range of viewing angles, that is, the contrast is significantly reduced when viewed from the normal direction of the display panel; in the case of color display, (4) Grayscale inversion occurs. In the case where the liquid crystal display device is developed to a large size, this weakness is particularly prominent. The edge electric field switch type liquid crystal display overcomes this disadvantage, and the application of the edge electric field switch type liquid crystal display is increasingly widespread. The edge electric field switch type liquid crystal display mainly comprises a liquid crystal display panel and a backlight module for providing a light source for the liquid crystal display panel. The liquid crystal display panel comprises a thin germanium transistor substrate, a color filter substrate, and a liquid crystal layer sandwiched between the thin film transistor substrate and the color filter and the light substrate. The film transistor substrate is disposed adjacent to the m side in sequence - a pixel electrode and a pair of electrodes, and the pixel electrode and the counter electrode cooperate to deflect the liquid crystal layer. The masterbatch element 100 includes a pair of electrodes 120. Referring to Fig. 1, a schematic view of a prior art thin film transistor substrate. The thin film transistor substrate 10 includes a plurality of gate lines 13, a plurality of common electrode lines, and a plurality of data lines 17. The plurality of common electrode lines 14 are arranged such that the plurality of gate lines are spaced apart and parallel to each other. The plurality of gate lines 13 are vertically insulated from the plurality of data lines 17 to define a plurality of books 100. Each book goes to open Du, A k ______ ~ ^ - thin film crystal 7 1321853 body 180 and complex pixel electrode 19 〇. The thin film transistor includes a gate 181, a source 182, a drain 183 and a via 184. The via 184 electrically turns on the drain 183 and the pixel electrode 19A. The counter electrode 120 is a transparent conductive layer having a pattern partially overlapping the common electrode line 14 and electrically conducting. Please refer to Figure 2 together for a cross-sectional view of Figure 1 along the IMI line. The thin film transistor substrate 1 further includes an insulating substrate n, a gate insulating layer 15, a semiconductor layer 1 and a protective layer 16. The gate line 13, the common electrode line 14, the gate 181, and the opposite electrode 12'' are all disposed on the insulating substrate 11. The gate insulating layer 15 covers the counter electrode 12A, the plurality of gate lines 13, the gate electrode 181, and the plurality of common electrode lines 14. The semiconductor layer 107 is deposited on the gate insulating layer 15 and corresponds to the gate electrode ΐ8ι. The source electrode 182 and the drain electrode 183 are disposed on the semiconductor layer 107 corresponding to the gate electrode 181. The protective layer 16 covers the gate insulating layer 15, and the source 182 = the drain 183. The pixel electrode 19 is disposed on the protective layer μ, and is electrically connected to the drain 183 via the via 184. Referring to Fig. 3, there is shown a flow chart of a conventional manufacturing method of the thin film transistor substrate. The manufacturing method adopts a six-mask process, and includes the following steps: 1. The first mask step S1: forming a transparent conductive layer; providing an insulating substrate 11 on which a transparent conductive layer and a layer are sequentially formed The first photoresist layer. Step S2: forming a counter electrode; exposing and developing the first photoresist layer in a pattern of a photomask, 8 1321853 : into a predetermined photoresist pattern; secretly engraving the transparent conductive layer to form a facing Electrode 120 removes the photoresist layer. However, the transparent conductive layer is in a wet y-like manner, and the conductive layer, such as a residual block 121, is formed. Second, the second mask step S3: forming a metal layer;
於該對向電極120、該殘留塊121及該絕緣基底lljL 沉積-金屬層’再覆蓋一第二光阻層於該金屬層上。 步驟S4 ·开> 成公共電極線、閘極線及閑極； 以第二光罩的圖案對該第二光阻層進行曝光並顯影， 1 成一預定光阻圖案；對該金屬層進行㈣，形成該公丑 線14、該閘極線13及該閘極181，該閘極181係與該 閘極線13 -體形成。該公共電極線14與該閘極線η平 ==塊121分別被部份該公共電極線14與部 極踝U覆蓋。 鲁 三、第三道光罩 步驟S5:形成閘極絕緣層、非^及摻雜非晶石夕層· 於該對向電極120、公共極、線14、該問極線13、該曰間 極18丨及該絕緣基底u上形成一閘極絕緣層15、一 矽及摻雜非晶矽層及一第三光阻層。 曰 步驟S6 :形成半導體層； 從而^三光罩之圖案對該第三光阻層進行曝光並顯影， 從而开/成-預定光阻圖案；對該非晶石夕及摻雜非晶石夕 打钱刻’進而形成一半導體層1〇7，移除該第三光阻 9 1321853 四、 第四道光罩 步驟S7 :形成源極/汲極金屬層； 於該半導體層107及該閘極絕緣層15上依序沉積一 極/汲極金屬層及一第四光阻層。 藏 •步驟S8 :形成源極及汲極； 以該第四光罩之圖案對該第四光阻層進行曝光並蔡 影，形成一預定光阻圖案；對該源極/汲極金屬層進行蝕 刻，進而形成--源極182與一没極183。 五、 第五道光罩 步驟S9 :形成保護層； 於具有該源極182、該汲極183及該閘極絕緣層^上 形成一保護層16及一第五光阻層。 步驟S10.形成導通孔； 以第五光罩之圖案對該第五光阻層進行曝光並卿， 形成^•默光阻圖案；對該保護層16進純刻，曝露二部 參份該汲極I83,進而形成一導通孔1§4。 六、第六道光罩 步驟S11 :形成透明導電層； 2該保護層16上形成—透明導電層及第六光阻層。 y驟S12 .形成像素電極； 以第六光罩之圖案對第 一日闰安.# 步，、尤丨且進仃曝先並顯影，形成 迈月導電層進仃蝕刻，進而形成一 像素電極190。該像+雪权，# 取 素電極190錯由該導通孔ι84盥 極183電連接。 十、几丄畀茲汲 1321853 在該薄膜電晶體基板之製造方法中，由 10n x , T 田於該對向電極 120、該公共電極線14及該閘極線13形成於同一平面且 第：道光罩中，該透明導電層是以濕_方式來㈣，該 濕姓刻方式易钱刻不完全而發生製程異f，在形成對向電 極120後，殘存—些透明導電層，即該殘留塊⑵。在第 二道光罩形成該閘極線13與公共電極線14時，該殘留塊 121被部份閘極線13與部份公共電極線14覆蓋，由於該 殘留塊121之導電特性’該薄膜電晶體基板忉的晝素元^ 謂在傳輸閘極訊號與公共電極訊號時，傳輸閘極訊號之 閘極線13將會與傳輸公共訊號之公共電極線14及該對向 電極120短路，引起面板測試時的點亮異常從而影響該 薄膜電晶體基板10之良率。 【發明内容】 、有鑑於上述内容，提供一種良率高之薄膜電晶體基板 實為必要。 有鑑於上述内容，提供一種上述薄膜電晶體基板的製 造方法實為必要。 一種薄膜電晶體基板，其包括複數閘極線、與該複數 閘極線相互平行之複數公共電極線及與該複數閘極線垂 直、、邑緣相乂之複數資料線，該複數閘極線與該複數資料線 界定複數晝素單元，該每一畫素單元對應一對向電極及至 少一截斷區，該截斷區設置於該對向電極與該閘極線之 間’切斷該對向電極與該閘極線之間的電連接。 一種薄膜電晶體基板的製造方法，其步驟包括：提供 11 1321853 絕緣基底；於一道光罩製程中，形成對向電極於該絕緣 基底；於一道光罩製程中，形成公共電極線、閘極線及與 該Θ極線相連之閘極於該絕緣基底，該對向電極與該閘極 線相鄰設置；於一道光罩製程中，形成一閘極絕緣層及形 成一對應該閘極設置之半導體層於該閘極絕緣層；於一道 光罩製程中’形成源極及汲極於該半導體層；於一道光罩 製程中，形成一保護層及至少一截斷區，該截斷區使該對A deposition-metal layer is deposited on the counter electrode 120, the residual block 121, and the insulating substrate 11jL, and a second photoresist layer is overlaid on the metal layer. Step S4 · Opening > forming a common electrode line, a gate line, and a dummy electrode; exposing and developing the second photoresist layer in a pattern of the second mask, to form a predetermined photoresist pattern; and performing (4) on the metal layer The ugly line 14, the gate line 13 and the gate 181 are formed, and the gate 181 is formed with the gate line 13 - body. The common electrode line 14 is flat with the gate line η == block 121 is covered by a portion of the common electrode line 14 and the portion 踝U, respectively. Lu 3, the third mask step S5: forming a gate insulating layer, a non-doped and doped amorphous layer, on the opposite electrode 120, the common pole, the line 14, the interrogating line 13, the inter-electrode A gate insulating layer 15, a germanium and doped amorphous germanium layer and a third photoresist layer are formed on the insulating substrate u. Step S6: forming a semiconductor layer; thereby patterning and developing the third photoresist layer by the pattern of the three masks, thereby opening/forming the predetermined photoresist pattern; and playing the amorphous stone and the doped amorphous stone Forming a semiconductor layer 1〇7, removing the third photoresist 9 1321853 4. The fourth mask step S7: forming a source/drain metal layer; the semiconductor layer 107 and the gate insulating layer 15 A one-pole/dipper metal layer and a fourth photoresist layer are sequentially deposited. Step S8: forming a source and a drain; exposing and patterning the fourth photoresist layer in a pattern of the fourth mask to form a predetermined photoresist pattern; and performing the source/drain metal layer on the source/drain metal layer Etching, in turn, forms a source 182 and a gate 183. V. The fifth mask step S9: forming a protective layer; forming a protective layer 16 and a fifth photoresist layer on the source electrode 182, the drain electrode 183, and the gate insulating layer. Step S10. Forming a via hole; exposing and illuminating the fifth photoresist layer in a pattern of a fifth mask to form a photoresist pattern; the protective layer 16 is purely engraved, and the two portions are exposed. The pole I83 further forms a via hole 1§4. Sixth, the sixth mask step S11: forming a transparent conductive layer; 2 the protective layer 16 is formed with a transparent conductive layer and a sixth photoresist layer. y S12. Forming a pixel electrode; using a pattern of a sixth mask to the first day of the . .. # step, 丨 丨 仃 仃 并 并 并 并 并 并 仃 仃 仃 仃 仃 仃 仃 迈 迈 迈 迈 迈 迈 迈 迈 迈 迈 迈 迈 迈 迈 迈 迈 迈 迈190. The image + snow weight, the # electrode electrode 190 is electrically connected by the via hole ι84 183. In the method for manufacturing a thin film transistor substrate, 10 n x , T field is formed on the same plane on the counter electrode 120, the common electrode line 14 and the gate line 13 and the first: In the reticle, the transparent conductive layer is in a wet manner (four), and the wet etching method is incomplete and the process is different. After the opposite electrode 120 is formed, some transparent conductive layers remain, that is, the residual Block (2). When the gate layer 13 and the common electrode line 14 are formed by the second mask, the residual block 121 is covered by the partial gate line 13 and the partial common electrode line 14, due to the conductive property of the residual block 121. When the gate signal and the common electrode signal are transmitted, the gate line 13 of the transmission gate signal will be short-circuited with the common electrode line 14 transmitting the common signal and the opposite electrode 120, causing the panel. The lighting abnormality at the time of the test affects the yield of the thin film transistor substrate 10. SUMMARY OF THE INVENTION In view of the above, it is necessary to provide a thin film transistor substrate having a high yield. In view of the above, it is necessary to provide a method of manufacturing the above-described thin film transistor substrate. A thin film transistor substrate comprising a plurality of gate lines, a plurality of common electrode lines parallel to the plurality of gate lines, and a plurality of data lines perpendicular to the plurality of gate lines and opposite to each other, the complex gate lines And a plurality of pixel units defining a plurality of pixel units, wherein each of the pixel units corresponds to a pair of electrodes and at least one of the cut-off regions, and the cut-off region is disposed between the opposite electrode and the gate line to cut off the opposite direction An electrical connection between the electrode and the gate line. A method for manufacturing a thin film transistor substrate, comprising the steps of: providing an insulating substrate of 11 1321853; forming a counter electrode on the insulating substrate in a mask process; forming a common electrode line and a gate line in a mask process And a gate connected to the drain line is opposite to the insulating substrate, the opposite electrode is disposed adjacent to the gate line; in a mask process, a gate insulating layer is formed and a pair of gate electrodes are formed a semiconductor layer is disposed on the gate insulating layer; forming a source and a drain in the semiconductor layer in a mask process; forming a protective layer and at least one cut-off region in a mask process, the cut-off region
向電極與該閘極線之間斷開；於一道光罩製程中，形成像 素電極於該保護層。 相較於先前技術，本發明於一道光罩製程中，在相鄰 设置於該絕緣基底上的對向電極與閘極線之間形成至少一 截斷區，該截斷區間隔該對向電極與該閘極線，以使該對 向電極與該閘極線絕緣，防止傳輸該相異訊號之電極之間 的電導通而發生的訊號相互干擾現象，故，可提高製造薄 膜電晶體基板的良率。 【實施方式】 請參閱圖3’係本發明液晶顯示器第一實施方式之製 造流程示意圖。其包含步驟如下： 明參閱圖4 ’係本發明薄膜電晶體基板之結構示意 =。該薄膜電晶體基板20包括複數閘極線23、複數公共 電極線24及複數資料線27 ^該複數公共電極線％與該複 數閘極線23相互平行設置。該閘極線23與該資料線27 垂直絕緣相交，界定複數畫素元件200。該每一畫素元件 200對應一對向電極22〇、一薄膜電晶體28〇、複數像素電 12 1321853 -極290及二截斷區225。該薄膜電晶體280包括一閘極 281、一源極282、一汲極283及一導通孔284。該導通孔 284電性導通該汲極283與該像素電極290。該對向電極 220與該公共電極線24部份重疊且電導通，以傳輸公共電 • 壓ifl號，且該對向電極220為具有一定圖案之透明導電 層，在形成該對向電極220時，有可能產生一殘留塊222。 該二截斷區225可截斷該殘留塊222，以切斷該公共電極 線24與該閘極線23之間的電連接，亦切斷該閘極線23 鲁與該對向電極220之間的電連接。 請一併參閱圖5，係圖4沿V-V線之剖面示意圖。該 薄膜電晶體基板20進一·步包括一絕緣基底201、一閘極絕 緣層204、一半導體層207及一保護層25。該閘極線23、 該公共電極線24、該閘極281及該對向電極220均設置於 該絕緣基底201上。該閘極絕緣層204覆蓋該對向電極 220、該複數閘極線23、該閘極281及該複數公共電極線 24。該半導體層207沉積在該閘極絕緣層204上，且與該 籲閘極281對應。該源極282及汲極283對應該閘極281設 置於該半導體層207上。該保護層25覆蓋該閘極絕緣層 204、該源極282及汲極283。該像素電極290藉由該導通 孔284與該汲極283電連接。該二截斷區225分別設置於 該公共電極線24與該閘極線23之間及該閘極線23與該對 向電極220之間，以切斷可能形成之該殘留塊222。 請參閱圖6,係本發明之薄膜電晶體基板的製造方法 之流程圖。該製造方法採用六道光罩製程，包括以下步驟： 13 1321853 . 一、第一道光罩 步驟S21 :形成透明導電層； 請參閱圖7,提供一絕緣基底2〇1，該絕緣基底2〇1 可以係玻璃、石英或者陶瓷等絕緣材質；在該絕緣基底2〇1 上洸積一透明導電層202，該透明導電層2〇2可以為銦錫 氧化物（Indium Tin 〇xide，IT〇 )或銦鋅氧化物（Indium zinc 〇xide，IZO)’·在該透明導電層2〇2上沉積第一光阻層9〇， 再提供一光罩91。 步驟S22 :形成對向電極； "月併參閱圖8 ’以該第一光罩91的圖案對該第一光 阻層90進行曝光並顯影，形成一預定光阻圖帛％。請一 9 ’㈣透明導電層2Q2未被該敎光阻圖案％ 覆盍之部份進行濕银刻，從而形成對向電極220。惟，在 蝕刻出該對向電極220時，目 透明導電層202以濕蝕刻 万式來姓刻，濕蝕刻方式宜屆 j力式今易蝕刻不完全而發生製程異 吊’產生一些殘留塊222。 二、第二道光罩 步驟S23 :形成金屬層； 請一併參閱圖10,於哕斟 加上沈積-金屬層及該絕緣基底 (M。）、絡(Cr)、叙（Ta)或 :再銘（广）二翻 層（圖未示）於該金屬層203 jJ等’再覆盍一第二光阻 J驟=閱:成:共電極線、間極線及閉極； 月1 开参閱圖11，以篦-土 $ , 矛一九罩的圖案對該第二光阻層 1321853 -進行曝光並顯影，形成一預定光阻圖案；對該金屬層203 進行蝕刻。形成一公共電極線24、一閘極線23及一閘極 281。由於第一道光罩中形成一些殘留塊222於該絕緣基底 201上，故，該公共電極線24與該閘極線23將會與該殘 留迤222部份重疊，從而使該對向電極220與該閘極線23 電導通》使該閘極線23與該公共電極線24電導通。 三、 第三道光罩 步驟S25 :形成閘極絕緣層、非晶矽及摻雜非晶矽層； 請參閱圖12，於該對向電極220、該公共極線14、該 閘極線13、該閘極及該絕緣基底201上用化學氣相沈積方 法形成氮化矽（SiNx)構成之閘極絕緣層204;再用化學氣相 沈積（Chemical Phase Deposition，CVD)方法在該閘極絕 緣層204上形成一非晶矽層；再進行一道摻雜工藝，對該 非晶矽層進行摻雜，形成一非晶矽層205及一摻雜非晶矽 層206。再沉積第三光阻層（圖未示）於其上。 步驟S26 :形成半導體層； 請一併參閱圖13,以第三光罩之圖案對該第三光阻層 進行曝光並顯影，從而形成一預定光阻圖案；對該非晶矽 205及摻雜非晶矽層206進行蝕刻，進而形成一半導體層 207，該半導體層207對應該閘極281形成於該閘極絕緣層 204上。移除該第三光阻層。 四、 第四道光罩 步驟S27 :形成源極/汲極金屬層； 請一併參閱圖14,於半導體層207及該閘極絕緣層 15 U21853 -204上形成一源極/汲極金屬層2〇9及第四電阻層（圖未 不）。該源極/汲極金屬層2〇9材料可為金屬鋁（ai)、鉬 (M〇)、鉻（Cr)、钽（Ta)或銅（Cu)等。 步驟S28 :形成源極及没極； •、—請一併參閱圖15,以第四光罩之圖案對該第四光阻層 進=曝光並顯影，形成一預定光阻圖案；對該金屬層2〇9 進行姓刻進而形成資料線（圖未示）及由該資料線一體 _成形之源極282及汲極283。該源極282及該汲極283對 應該閘極281形成於該半導體層207上。 五、第五道光罩 步驟S29 :形成保護層； 請參閱圖16，該源極282、汲極283及該閘極絕緣層 204上依序沉積一保護層25及一第五光阻層（圖未示 該保護層25之材料係氮化矽層。 步驟S210 :形成導通孔及複數截斷區； # 請一併參閱圖17,以第五光罩之圖案對該第五光阻層 進仃曝光並顯影，形成一預定光阻圖案；對該保護層Μ 進行蝕刻，進而形成一預定光阻圖案之導通孔284及複數 通道224。該導通孔284曝露該汲極283 —部份，該複數 通道224分別對應該閘極線23與該公共電極線以之間的 區域，及該閘極線23與該對向電極22〇之間的區域。請再 參閱圖18，沿該複數通道224進一步對該閘極絕緣層2〇4 及該殘留塊222進行蝕刻，形成複數截斷區225。該二截 斷區225切斷在第一道光罩製程中，該透明導電層2〇2蝕 16 1321853 刻異常而形成之殘留塊222，從而切斷該 該閘極線23之間的電連接你兮 220與 魄23难缝；# 對向電極220與該閘極 及切斷該閘極線23與該公共電極_之電連 f Η吏該公共電極線24與該閘極線23絕緣，防 相異訊號的電極之間之電導通。 輪 六、第六道光罩The electrode is disconnected from the gate line; in a mask process, a pixel electrode is formed on the protective layer. Compared with the prior art, the present invention forms at least one cut-off region between the opposite electrode and the gate line disposed adjacent to the insulating substrate in a mask process, and the cut-off region is spaced apart from the opposite electrode and the gate electrode a gate line for insulating the opposite electrode from the gate line to prevent mutual interference of signals generated by electrical conduction between the electrodes of the dissimilar signals, thereby improving the yield of the thin film transistor substrate . [Embodiment] Please refer to Fig. 3', which is a schematic diagram showing the manufacturing process of the first embodiment of the liquid crystal display of the present invention. The steps involved are as follows: See Figure 4 for a schematic representation of the structure of the thin film transistor substrate of the present invention. The thin film transistor substrate 20 includes a plurality of gate lines 23, a plurality of common electrode lines 24, and a plurality of data lines 27. The plurality of common electrode lines % and the plurality of gate lines 23 are disposed in parallel with each other. The gate line 23 is vertically insulated from the data line 27 to define a plurality of pixel elements 200. Each of the pixel elements 200 corresponds to a pair of electrodes 22, a thin film transistor 28, a plurality of pixels 12 1321853 - a pole 290 and two cut-off regions 225. The thin film transistor 280 includes a gate 281, a source 282, a drain 283, and a via 284. The via 284 electrically turns on the drain 283 and the pixel electrode 290. The counter electrode 220 and the common electrode line 24 are partially overlapped and electrically connected to transmit a common electric voltage ifl, and the opposite electrode 220 is a transparent conductive layer having a pattern, when the counter electrode 220 is formed. It is possible to generate a residual block 222. The two cut-off regions 225 can cut off the residual block 222 to cut off the electrical connection between the common electrode line 24 and the gate line 23, and also cut off between the gate line 23 and the opposite electrode 220. Electrical connection. Please refer to FIG. 5 together, and FIG. 4 is a schematic cross-sectional view along line V-V. The thin film transistor substrate 20 further includes an insulating substrate 201, a gate insulating layer 204, a semiconductor layer 207, and a protective layer 25. The gate line 23, the common electrode line 24, the gate 281, and the opposite electrode 220 are all disposed on the insulating substrate 201. The gate insulating layer 204 covers the opposite electrode 220, the complex gate line 23, the gate 281, and the complex common electrode line 24. The semiconductor layer 207 is deposited on the gate insulating layer 204 and corresponds to the gate 281. The source 282 and the drain 283 are disposed on the semiconductor layer 207 corresponding to the gate 281. The protective layer 25 covers the gate insulating layer 204, the source 282, and the drain 283. The pixel electrode 290 is electrically connected to the drain 283 via the via hole 284. The two cut-off regions 225 are respectively disposed between the common electrode line 24 and the gate line 23 and between the gate line 23 and the opposite electrode 220 to cut off the residual block 222 that may be formed. Referring to Figure 6, there is shown a flow chart of a method of fabricating a thin film transistor substrate of the present invention. The manufacturing method adopts a six-mask process, including the following steps: 13 1321853. First, the first mask step S21: forming a transparent conductive layer; Referring to FIG. 7, an insulating substrate 2〇1 is provided, the insulating substrate 2〇1 It may be an insulating material such as glass, quartz or ceramic; a transparent conductive layer 202 may be accumulated on the insulating substrate 2〇1, and the transparent conductive layer 2〇2 may be Indium Tin 〇xide (IT〇) or Indium zinc 〇xide (IZO)'. A first photoresist layer 9 is deposited on the transparent conductive layer 2'2, and a mask 91 is provided. Step S22: forming a counter electrode; " month and referring to Fig. 8' exposes and develops the first photoresist layer 90 in a pattern of the first mask 91 to form a predetermined photoresist pattern 帛%. A portion of the transparent conductive layer 2Q2 that is not covered by the photoresist pattern % is wet-etched to form the counter electrode 220. However, when the counter electrode 220 is etched, the transparent conductive layer 202 is wet-etched by a wet etching method, and the wet etching method is indispensable for the etching process to be incompletely etched. . Second, the second mask step S23: forming a metal layer; please refer to FIG. 10 together with the deposition-metal layer and the insulating substrate (M.), network (Cr), and (Ta) or: Ming (wide) two layers (not shown) in the metal layer 203 jJ, etc. 'repeated a second photoresist J = = read: into: common electrode line, interpolar line and closed pole; Referring to FIG. 11, the second photoresist layer 1321853- is exposed and developed in a pattern of 篦-土$, a spear cover, to form a predetermined photoresist pattern; and the metal layer 203 is etched. A common electrode line 24, a gate line 23 and a gate 281 are formed. Since the residual mask 222 is formed on the insulating substrate 201 in the first mask, the common electrode line 24 and the gate line 23 will partially overlap the residual germanium 222, thereby causing the opposite electrode 220. Electrically conducting with the gate line 23 electrically connects the gate line 23 to the common electrode line 24. Third, the third mask step S25: forming a gate insulating layer, an amorphous germanium layer and a doped amorphous germanium layer; referring to FIG. 12, the opposite electrode 220, the common electrode line 14, the gate line 13, Forming a gate insulating layer 204 made of tantalum nitride (SiNx) by chemical vapor deposition on the gate and the insulating substrate 201; and using the chemical vapor deposition (CVD) method in the gate insulating layer An amorphous germanium layer is formed on 204; a doping process is performed to dope the amorphous germanium layer to form an amorphous germanium layer 205 and a doped amorphous germanium layer 206. A third photoresist layer (not shown) is deposited thereon. Step S26: forming a semiconductor layer; referring to FIG. 13, the third photoresist layer is exposed and developed in a pattern of a third mask to form a predetermined photoresist pattern; the amorphous germanium 205 and the doped non- The germanium layer 206 is etched to form a semiconductor layer 207, which is formed on the gate insulating layer 204 corresponding to the gate 281. The third photoresist layer is removed. Fourth, the fourth mask step S27: forming a source/drain metal layer; please refer to FIG. 14 together to form a source/drain metal layer 2 on the semiconductor layer 207 and the gate insulating layer 15 U21853-204 〇9 and the fourth resistance layer (not shown). The material of the source/drain metal layer 2〇9 may be metal aluminum (ai), molybdenum (M〇), chromium (Cr), tantalum (Ta) or copper (Cu). Step S28: forming a source and a immersion; •, - referring to FIG. 15, the fourth photoresist layer is exposed and developed in a pattern of a fourth reticle to form a predetermined photoresist pattern; The layer 2〇9 is subjected to a surname to form a data line (not shown) and a source 282 and a drain 283 which are integrally formed by the data line. The source electrode 282 and the drain electrode 283 are formed on the semiconductor layer 207 corresponding to the gate electrode 281. 5. The fifth mask step S29: forming a protective layer; referring to FIG. 16, the source 282, the drain 283, and the gate insulating layer 204 are sequentially deposited with a protective layer 25 and a fifth photoresist layer (Fig. The material of the protective layer 25 is not shown as a tantalum nitride layer. Step S210: forming a via hole and a plurality of cut-off regions; #Please refer to FIG. 17 together, and exposing the fifth photoresist layer to the fifth mask pattern. And developing to form a predetermined photoresist pattern; etching the protective layer , to form a predetermined photoresist pattern via hole 284 and a plurality of vias 224. The via hole 284 exposes the drain 283 - the plurality of channels 224 respectively corresponds to the region between the gate line 23 and the common electrode line, and the region between the gate line 23 and the opposite electrode 22A. Referring again to FIG. 18, further along the complex channel 224 The gate insulating layer 2〇4 and the residual block 222 are etched to form a plurality of cut-off regions 225. The two cut-off regions 225 are cut in the first mask process, and the transparent conductive layer 2〇2 etches 16 1321853 anomalies Forming the residual block 222, thereby cutting off the electricity between the gate lines 23.接 兮 220 and 魄 23 difficult to sew; # counter electrode 220 and the gate and cut off the gate line 23 and the common electrode _ electrical connection f Η吏 the common electrode line 24 is insulated from the gate line 23 , the electrical conduction between the electrodes of the anti-dissimilar signal. The sixth and sixth masks
步驟S211 :形成像素電極透明導電層； 請參閱圖19，於該保護層25、 數截斷區（未標示）上依序沉積一 及第六光阻層（圖未示）。 導通孔（未標示）及複 像素電極透明導電層26 步驟S212 :形成像素電極； “請再參閱圖20,以第六光罩之圖案對第六光阻層進行 曝光並顯影’形成一預定光阻圖案；對該透明導電層進行 蝕刻，進而形成像素電極290，該像素電極29〇藉由該導 通孔284與該汲極283電連接。Step S211: forming a pixel electrode transparent conductive layer; referring to FIG. 19, a first and a sixth photoresist layer (not shown) are sequentially deposited on the protective layer 25 and the plurality of cut-off regions (not shown). a via hole (not shown) and a complex pixel electrode transparent conductive layer 26. Step S212: forming a pixel electrode; "Please refer to FIG. 20 again, exposing and developing the sixth photoresist layer in a pattern of a sixth mask to form a predetermined light. a resist pattern; the transparent conductive layer is etched to form a pixel electrode 290, and the pixel electrode 29 is electrically connected to the drain 283 via the via hole 284.
相較於先前技術，在第五道光罩中，蝕刻該保護層25 升^成該V通孔284，以曝露一部份沒極283的同時對應該 殘留塊222形成該複數通道224，再沿該複數通道224進 一步蝕刻該閘極絕緣層2〇4與該殘留塊222，形成複數截 斷區225 ’該截斷區225切斷該殘留塊222，即切斷該對向 電極220與該閘極線23電導通之通路，及該閘極線23與 該公共電極線24導通之通路。故，當傳送該閘極訊號及該 公共電壓訊號時，傳輸該閘極訊號之閘極線23與傳輸該公 共電壓訊號之公共電極線24及該對向電極220之間不會發 生相互干擾現象，防止畫素元件2〇〇在傳輸相異訊號之電 17 丄丄δ:)」 -極間發生短路而提高該薄膜電晶體基板2 0之製造良率。且 本發明於形成該導通孔284之光罩製程中，進一步钱刻該 閘極絕緣層204及該殘留塊222即可形成該二截斷區 225 ’故不需要增加光罩製程就可以提高薄膜電晶體基板的 製造良率。 綜上所述，本發明確已符合發明專利之要件，爰依法 提出專利申請。惟，以上所述者僅為本發明之較佳實施方 鲁式，本發明之範圍並不以上述實施方式為限，舉凡熟習本 =技藝之人士援依本發明之精神所作之等效修飾或變化， 皆應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 圖1係一種先前技術薄膜電晶體基板之結構示意圖。 圖2圖2係圖1沿Π-ΙΙ線之剖面示意圖。 圖3係該薄臈電晶體基板之傳統製造方法之流程圖。 圖4係本發明薄臈電晶體基板之結構示意圖。 籲圖5係圖4沿V-V線之剖面示意圖。 圖6係本發明之薄膜電晶體基板的製造方法之流程圖。 Ώ 7係本發明之薄膜電晶體基板形成透明導電層之示意 圖。 圖8係本發明之薄膜電晶體基板第一光阻層形成預定光阻 圖案之不意圖。 圖9係本發明之薄膜電晶體基板形成對向電極及該殘留塊 之示意圖。 圖10係本發明之薄膜電晶體基板形成金屬層之示意圖。 18 圖11係本發明之薄媒電晶體基板形成公共電極線、間極線 及閘極之示意圖。 圖12係本發明之薄m電晶體基板形成閘極絕緣層、非晶石夕 及摻雜非晶矽層之示意圖。 =13係本發明之薄膜電晶體基板形成半導體層之示意圖。 14係本發明之薄犋電晶體基板形成源極/汲極金屬層之 示意圖。 圖15係_本發明之薄膜電晶體基板形成資料線、源極及沒極 之示意圖。 圖16係本發明之薄膜電晶體基板形成保護層之示意圖。 圖17係本發明之薄膜電晶體基板形成導通孔及複數通道 之示意圖。 圖18係本發明之薄膜電晶體基板形成複數截斷區之示意 圖0 圖19係本發明之薄膜 電晶體基板形成透明導電層之示意 圖。 圖20係本發明之薄膜電晶體基板形成像素 電極之示意圖。 L主要元件符號說明】 薄膜電晶體基板 20 閘極線 23 公共電極線 24 保護層 25 像素電極透明導電層 26 資料線 27 光阻層 90 光罩 91 預定光阻圖案 92 像素單元 200 絕緣基底 201 透明導電層 202 19 2041321853 閘極金屬層 203 閘極絕緣層 非晶矽層 205 摻雜非晶矽層 半導體層 207 源極/汲極金屬層 對向電極 220 殘留塊 it道 224 截斷區 薄膜電晶體 280 閘極 源極 282 汲極 導通孔 284 像素電極 206 209 222 225 281 283 290 20Compared with the prior art, in the fifth mask, the protective layer 25 is etched into the V via 284 to expose a portion of the gate 283 while the residual block 222 is formed to form the complex channel 224. The plurality of channels 224 further etch the gate insulating layer 2〇4 and the residual block 222 to form a plurality of cut-off regions 225. The cut-off region 225 cuts the residual block 222, that is, cuts the opposite electrode 220 and the gate line. A path for conducting electricity, and a path for the gate line 23 to be electrically connected to the common electrode line 24. Therefore, when the gate signal and the common voltage signal are transmitted, the gate line 23 transmitting the gate signal and the common electrode line 24 transmitting the common voltage signal and the opposite electrode 220 do not interfere with each other. The pixel element 2 is prevented from being short-circuited between the electrodes 17 丄丄 δ:)"-transmitting the different signals, thereby improving the manufacturing yield of the thin film transistor substrate 20. In the process of forming the via hole 284, the gate insulating layer 204 and the residual block 222 can be further formed to form the two cut-off regions 225', so that the thin film can be improved without adding a mask process. The manufacturing yield of the crystal substrate. In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and those skilled in the art will be equivalently modified according to the spirit of the present invention. Changes should be covered by the following patents. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing the structure of a prior art thin film transistor substrate. Figure 2 Figure 2 is a schematic cross-sectional view of Figure 1 along the Π-ΙΙ line. 3 is a flow chart of a conventional manufacturing method of the thin germanium transistor substrate. 4 is a schematic structural view of a thin tantalum transistor substrate of the present invention. Figure 5 is a schematic cross-sectional view taken along line V-V of Figure 4. Fig. 6 is a flow chart showing a method of manufacturing the thin film transistor substrate of the present invention. Ώ 7 is a schematic view showing the formation of a transparent conductive layer on the thin film transistor substrate of the present invention. Fig. 8 is a view showing the formation of a predetermined photoresist pattern by the first photoresist layer of the thin film transistor substrate of the present invention. Fig. 9 is a view showing the formation of a counter electrode and the residual block of the thin film transistor substrate of the present invention. Fig. 10 is a schematic view showing the formation of a metal layer of the thin film transistor substrate of the present invention. 18 is a schematic view showing the formation of a common electrode line, an interpole line, and a gate electrode of the thin dielectric transistor substrate of the present invention. Fig. 12 is a schematic view showing the formation of a gate insulating layer, an amorphous layer and an doped amorphous germanium layer on a thin m transistor substrate of the present invention. = 13 is a schematic view showing the formation of a semiconductor layer of the thin film transistor substrate of the present invention. 14 is a schematic view of a thin germanium transistor substrate of the present invention forming a source/drain metal layer. Fig. 15 is a schematic view showing the formation of a data line, a source and a immersion of the thin film transistor substrate of the present invention. Figure 16 is a schematic view showing the formation of a protective layer of the thin film transistor substrate of the present invention. Fig. 17 is a view showing the formation of via holes and a plurality of channels in the thin film transistor substrate of the present invention. Figure 18 is a schematic view showing the formation of a plurality of cut-off regions of the thin film transistor substrate of the present invention. Figure 0 is a schematic view showing the formation of a transparent conductive layer on the thin film transistor substrate of the present invention. Fig. 20 is a view showing the formation of a pixel electrode of the thin film transistor substrate of the present invention. L main component symbol description] thin film transistor substrate 20 gate line 23 common electrode line 24 protective layer 25 pixel electrode transparent conductive layer 26 data line 27 photoresist layer 90 photomask 91 predetermined photoresist pattern 92 pixel unit 200 insulating substrate 201 transparent Conductive layer 202 19 2041321853 Gate metal layer 203 Gate insulating layer Amorphous germanium layer 205 Doped amorphous germanium layer semiconductor layer 207 Source/drain metal layer counter electrode 220 Residual block channel 224 Truncated region thin film transistor 280 Gate source 282 drain via 284 pixel electrode 206 209 222 225 281 283 290 20