CN110176429A - A kind of production method and array substrate, display panel of array substrate - Google Patents
A kind of production method and array substrate, display panel of array substrate Download PDFInfo
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- CN110176429A CN110176429A CN201910275091.2A CN201910275091A CN110176429A CN 110176429 A CN110176429 A CN 110176429A CN 201910275091 A CN201910275091 A CN 201910275091A CN 110176429 A CN110176429 A CN 110176429A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
Abstract
This application discloses a kind of production method of array substrate and array substrates, display panel, comprising steps of the first metal layer and the first insulating layer is formed on the substrate；Active layer is deposited and patterned, generates the first active layer and the second active layer；The first insulating layer is patterned using the mask plate of second insulating layer, wherein sectional hole patterns was correspondingly arranged on the mask plate of the second insulating layer, second active layer is formed in the position for corresponding to sectional hole patterns of the mask plate of the second insulating layer；Second metal layer is deposited and patterned, the position of corresponding first active layer forms channel；Second insulating layer is deposited, forms via hole using the mask plate patterned insulation layer of the second insulating layer；Transparent electrode layer is deposited and patterned, connect transparent electrode layer with second metal layer by via hole, uses the mask plate of the second insulating layer twice, achievees the effect that save cost, while saving processing procedure.
Description
Technical field
This application involves the production methods and array substrate of field of display technology more particularly to a kind of array substrate, display
Panel.
Background technique
Display panel has obtained development by leaps and bounds in recent years and has widely applied.With regard to the TFT-LCD (Thin on mainstream market
Film Transistor-Liquid Crystal Display, thin film transistor liquid crystal display screen) for, including array substrate
And color membrane substrates, thin film transistor (TFT) is formed in array substrate, thin film transistor (TFT) controls the switch of pixel electrode, thin film transistor (TFT)
When opening, pixel electrode generates voltage, so that liquid crystal molecule deflects, shows picture.
In the fabrication process of the array substrate, due to non-display area, some the first metal layer may be exposed
Come, connect with external circuit, then just needing to etch away the gate insulating layer on the first metal layer of corresponding region, be typically necessary
It increases one of mask plate newly, brings higher cost.
Summary of the invention
The purpose of the application is to provide the production method and array substrate, display panel of a kind of array substrate, with reduce at
This.
This application discloses a kind of production methods of array substrate, comprising steps of
The first metal layer and the first insulating layer is formed on the substrate；
Active layer is deposited and patterned, generates the first active layer and the second active layer；
The first insulating layer is patterned using the mask plate of second insulating layer；
Second metal layer is deposited and patterned, the position of corresponding first active layer forms channel；
Second insulating layer is deposited, forms via hole using the mask plate patterning second insulating layer of second insulating layer；
Transparent electrode layer is deposited and patterned, connect transparent electrode layer with second metal layer by via hole；
Wherein, sectional hole patterns were correspondingly arranged on the mask plate of the second insulating layer, second active layer is formed in
The position for corresponding to sectional hole patterns of the mask plate of second insulating layer.
It optionally, further include pair in the step of mask plate using second insulating layer patterns the first insulating layer
The step of the first insulating layer etching of binding region.
Optionally, the width of second active layer is more than or equal to the width of via hole.
Optionally, after the step of mask plate using second insulating layer patterns the first insulating layer, further include
The step of to the second active layer etching.
Disclosed herein as well is a kind of array substrates characterized by comprising substrate, and sequentially form on substrate
The first metal layer, the first insulating layer, active layer, second metal layer, second insulating layer and transparent electrode layer, wherein described active
Layer includes: the first active layer and the second active layer, and the second metal layer is formed at the position of correspondence first active layer
Channel forms via hole in the second insulating layer, and the transparent electrode layer is electrically connected by the via hole and second metal layer,
Second active layer is arranged at the position of the correspondence via hole.
Optionally, first active layer is not connected to mutually with the second active layer.
Optionally, the array substrate includes viewing area and non-display area, and the non-display area includes binding region, described
The first metal layer includes grid and first electrode layer, and the grid is correspondingly arranged at the position of the channel, first electricity
At corresponding binding region, the first electrode layer is exposed for pole layer setting.
Optionally, the width of second active layer is more than or equal to the width of via hole.
Optionally, thickness of the thickness of second active layer less than the first active layer.
Disclosed herein as well is a kind of display panels, including above-mentioned array substrate.
In the present solution, the mask plate that the second active layer is formed in second insulating layer corresponded to the position of sectional hole patterns, utilizing
When the mask plate of second insulating layer is exposed development to the first insulating layer, can expose second at corresponding via hole pattern position has
Active layer, corresponding non-display area need the first insulating layer etched that can also expose, etch at this time to the first insulating layer, can't
Second active layer is etched, to pass through the protection of the second active layer, prevents the mask plate via hole pattern position of second insulating layer
The first insulating layer be etched away, by using script second insulating layer mask plate, in entire array substrate processing procedure, twice
Using the mask plate of second insulating layer, achieve the effect that save cost, while saving processing procedure.
Detailed description of the invention
Included attached drawing is used to provide that a further understanding of the embodiments of the present application, and which constitute one of specification
Point, for illustrating presently filed embodiment, and with verbal description come together to illustrate the principle of the application.Under it should be evident that
Attached drawing in the description of face is only some embodiments of the present application, for those of ordinary skill in the art, is not paying wound
Under the premise of the property made is laborious, it is also possible to obtain other drawings based on these drawings.In the accompanying drawings:
Fig. 1 is a kind of step schematic diagram of the production method of array substrate of the embodiment of the application；
Fig. 2 is the step schematic diagram of the production method of another array substrate of the embodiment of the application；
Fig. 3 is a kind of schematic diagram of array substrate production of the embodiment of the application；
Fig. 4 is a kind of step schematic diagram of the production method of array substrate of another embodiment of the application；
Fig. 5 is a kind of schematic diagram of array substrate of the embodiment of the application；
Fig. 6 is a kind of schematic diagram of display panel of the embodiment of the application.
Wherein, 10, display panel；100, array substrate；110, substrate；120, the first metal layer；121, grid；122,
One electrode layer；130, the first insulating layer；131, gate insulating layer；140, active layer；141, the first active layer；142, second is active
Layer；150, second metal layer；151, source electrode；152, it drains；153, channel；160, second insulating layer；161, via hole；162, it insulate
Layer；170, transparent electrode layer；200, viewing area；210, non-display area；211, binding region.
Specific embodiment
It is to be appreciated that term used herein above, disclosed specific structure and function details, it is only for description
Specific embodiment is representative, but the application can be implemented by many alternative forms, be not construed as only
It is limited to the embodiments set forth herein.
In the description of the present application, term " first ", " second " are used for description purposes only, and it is opposite to should not be understood as instruction
Importance, or implicitly indicate the quantity of indicated technical characteristic.As a result, unless otherwise indicated, " first ", " are defined
Two " feature can explicitly or implicitly include one or more of the features；The meaning of " plurality " is two or two
More than.Term " includes " and its any deformation, mean and non-exclusive include, it is understood that there may be or addition is one or more that other are special
Sign, integer, step, operation, unit, component and/or combination thereof.
In addition, "center", " transverse direction ", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner",
The term of the orientation or positional relationship of the instructions such as "outside" is that orientation or relative positional relationship based on the figure describe, only
Be that the application simplifies description for ease of description, rather than indicate signified device or element must have a particular orientation,
It is constructed and operated in a specific orientation, therefore should not be understood as the limitation to the application.
Furthermore unless specifically defined or limited otherwise, term " installation ", " connected ", " connection " shall be understood in a broad sense, example
Such as it may be fixed connection or may be dismantle connection, or integral connection；It can be mechanical connection, be also possible to be electrically connected
It connects；It can be directly connected, it can also indirectly connected through an intermediary or the connection inside two elements.For ability
For the those of ordinary skill in domain, the concrete meaning of above-mentioned term in this application can be understood as the case may be.
Below with reference to the accompanying drawings it elaborates with optional embodiment to the application.
As shown in Figure 1, one embodiment as the application, discloses a kind of production method of array substrate, including step
It is rapid:
S10: depositing the first metal layer, and after patterned first metal layer on substrate, deposits the first insulating layer；
S20: deposition active layer, and the first active layer and the second active layer are generated after being patterned with active layer；
S30: using the mask plate of second insulating layer for the first time, patterns the first insulating layer；
S40: depositing second metal layer, and second metal layer is patterned, channel is formed in the position of corresponding first active layer；
S50: deposition second insulating layer, second of mask plate using second insulating layer pattern second insulating layer and were formed
Hole；
S60: deposition transparent electrode layer, and patterned transparent electrode layer make transparent electrode layer pass through via hole and the second metal
Layer connection；
Wherein, sectional hole patterns were correspondingly arranged on the mask plate of the second insulating layer, second active layer is formed in
The position for corresponding to sectional hole patterns of the mask plate of second insulating layer；Second active layer protects the of corresponding via hole pattern position
One insulating layer.
In the fabrication process of the array substrate, due to non-display area, some the first metal layer may be exposed
Come, is connect with external circuit, then just needing to etch away the first insulating layer on the first metal layer of corresponding region, known to inventor
A kind of undocumented scheme be the first insulating layer after deposition process, mask plate is fabricated separately, non-display area is needed to etch
The first insulating layer region exposure development expose the first gold medal of non-display area in the first insulating layer for etching away corresponding region
Belong to layer, for this scheme, it is costly to increase one of mask plate newly, the problem of more one of processing procedure, bring higher cost.And
General second insulating layer non-display area in requisition for the region of exposed the first metal layer be also need etch, it is possible to
The first insulating layer is performed etching using second insulating layer mask plate.In the present solution, the second active layer is formed in the second insulation
The mask plate of layer corresponded to the position of sectional hole patterns, was exposed development to the first insulating layer in the mask plate using second insulating layer
When, the second active layer can be exposed by corresponding at via hole pattern position, corresponding non-display area needs the first insulating layer etched also can
It exposes, the first insulating layer is etched at this time, the second active layer can't be etched, to pass through the guarantor of the second active layer
Shield, prevents the first insulating layer of the mask plate via hole pattern position of second insulating layer to be etched away, by exhausted using originally second
The mask plate of edge layer uses the mask plate of second insulating layer in entire array substrate processing procedure twice, reaches the effect for saving cost
Fruit, while saving processing procedure.
The first metal layer of the binding region of non-display area generally requires to expose, with binding chip or circuit board；In
It is that in the S3 step, it is also to be formed figuratum that the mask plate of second insulating layer, which corresponds to binding region, therefore second can be passed through
The mask plate exposure development of insulating layer, and first insulating layer in the region binding (bonding) is etched away, expose corresponding region
The first metal layer.
As shown in Fig. 2, specifically, when the mask plate using second insulating layer is exposed development to the first insulating layer,
The following steps are included:
S301: deposition photoresist；
S302: development is exposed to photoresist by the mask plate of second insulating layer；
S303: photoresist lift off.
Wherein, in S302 step, the photoresist of corresponding via hole pattern position is removed, and forms photoresist gap, corresponding
The position in photoresist gap is the second exposed active layer, and the photoresist of corresponding binding region is also removed, corresponding binding region
For the first exposed insulating layer；Due to the presence of photoresist, the first insulating layer below photoresist is not etched, is corresponding with second
First insulating layer of active layer protection is not also etched, and the first insulating layer etching of only corresponding binding region；
Specifically, the width of the second active layer as described in Figure 3 is more than or equal to the width in photoresist gap, therefore, the
Two active layers can cover the first insulating layer of photoresist gap location, and the first insulating layer can be effectively prevented and be etched.Certainly, institute
State the second active layer width be more than or equal to the width of via hole can also be with.
In another embodiment, after the step of patterning the first insulating layer using the mask plate of second insulating layer, also
Include the steps that etching the second active layer, by etching away the second active layer, prevents the second active layer from leaking electricity to TFT switch
It is active can to etch away second specifically, the width of the second active layer is less than the width of via hole completely for the influence that characteristic generates
Layer.
As shown in figure 4, another specific embodiment as the application, discloses a kind of production method of array substrate,
Comprising steps of
S11: depositing the first metal layer, and after patterned first metal layer on substrate, forms grid and binding region
The first metal layer；
S21: gate insulating layer is deposited, not patterned grid insulating layer；
S31: deposition active layer, and the first active layer and the second active layer are generated after being patterned with active layer；First active layer
It is same processing procedure with the second active layer, same processing procedure can not then increase processing procedure newly to reduce cost, and reduce the time of processing procedure；
Specifically, the material of active layer can be IGZO (indium gallium zinc oxide, indium gallium zinc), it is also possible to
Amorphous silicon and polysilicon etc.；
S41: the mask plate of insulating layer, patterned grid insulating layer, wherein the mask plate of the insulating layer are used for the first time
On be correspondingly arranged on sectional hole patterns, second active layer is formed in the position for corresponding to sectional hole patterns of the mask plate of insulating layer；
Second active layer protects the gate insulating layer of corresponding via hole pattern position；Etch away the grid in the region binding (bonding)
Insulating layer exposes the first metal layer of corresponding region.
S51: depositing second metal layer, and second metal layer is patterned, source electrode and drain electrode is formed, and it is active to correspond to first
The position of layer forms channel；
S61: depositing insulating layer, second of mask plate patterned insulation layer using insulating layer form via hole；
S71: deposition transparent electrode layer, and patterned transparent electrode layer connect transparent electrode layer by via hole and drain electrode.
Wherein, gate insulating layer namely the first insulating layer, insulating layer i.e. second insulating layer, certain second insulating layer
It is also possible to flatness layer or other insulating layers etc..
As described in Fig. 5-6, as another embodiment of the application, a kind of display panel 10 is disclosed, including battle array
Column substrate 100.The array substrate 100 can be made by the above method, and the array substrate 100 includes: substrate 110, and
The first metal layer 120 on substrate is sequentially formed, the first insulating layer 130, active layer 140, second metal layer 150, second absolutely
Edge layer 160 and transparent electrode layer 170, wherein the active layer 140 includes: the first active layer 141 and the second active layer 142, institute
It states second metal layer 150 and includes source electrode 151 and drain electrode 152, formation channel 153 between source electrode 151 and drain electrode 152, described second
Via hole 161 is formed on insulating layer 160, via hole 161 is electrically connected for transparent electrode layer 170 and second metal layer 120, and described the
The position of the corresponding channel 153 of one active layer 141, the position of the corresponding via hole 161 of second active layer 142.
Specifically, the array substrate 100 includes viewing area 200 and non-display area 210, the non-display area 210 includes
Binding region 211, the first metal layer 120 include grid 141 and first electrode layer 122, and the grid 141 is correspondingly arranged at
At the position of the channel 153, the setting of first electrode layer 122 is at corresponding binding region 211, the first electrode layer
122 is exposed in binding region 211.
Certainly, first active layer 141 is not connected to mutually with second active layer 142.First active layer 141 and second
Active layer 142 is not connected to mutually, so that the second active layer 142 will not influence the leakage current characteristic of the first active layer 141, certain first has
Active layer 141 is connected to also possible with the second active layer 142.
Specifically, first active layer 141 and the second active layer 412 are located on the same floor, can be formed with the same processing procedure,
Do not increase additional processing procedure, the increase of cost will not be brought；Certainly, first active layer 141 and the second active layer 142 can also
Not to be located on the same floor, by different processing procedures, the material of the first active layer 141 and the second active layer 142 can be different；Example
Such as, the material of active layer may is that IGZO (indium gallium zinc), amorphous silicon and polysilicon etc., then corresponding first active layer
It can be IGZO, the second active layer can not be that IGZO can when certain second active layer is as the first active layer material
It is formed with same processing procedure, saves processing procedure, reduce cost.
Specifically, thickness of the thickness of second active layer 142 less than the first active layer 141, can be covered by semi-transparent
The same processing procedure of template is made, and can also be made by different processing procedures；To prevent the second metal layer of 142 top of the second active layer
150 is too thin, and when via hole is in transparent electrode layer connection, it causes impedance larger, causes display panel brightness low or show not
Uniformly.
The width of second active layer 142 can be more than or equal to the width of the via hole 161, in etching process
In, the second active layer 142 is more than or equal to the width of via hole 161, could below the second active layer 142 of most effective protection the
One insulating layer 130 is not etched.Certainly, the width of second active layer 142 cannot be too big, in the width of via hole 161
Within twice, 142 width Mrs of the second active layer is too close with the first active layer distance, will affect the semiconductor of the first active layer
Effect, and then influence the leakage current characteristic of TFT.
It should be noted that the restriction for each step being related in this programme, in the premise for not influencing concrete scheme implementation
Under, it does not regard as being can be the step of making restriction to step sequencing, write on front what is first carried out, be also possible to
It executes, is possibly even performed simultaneously afterwards, as long as this programme can be implemented, all shall be regarded as belonging to the protection model of the application
It encloses.
The technical solution of the application can be widely applied to various display panels, such as twisted nematic (Twisted
Nematic, TN) display panel, plane conversion type (In-Plane Switching, IPS) display panel, vertical orientation type
(Vertical Alignment, VA) display panel, more quadrant vertical orientation type (Multi-Domain Vertical
Alignment, MVA) display panel, it is of course also possible to be other kinds of display panel, such as Organic Light Emitting Diode
(Organic Light-Emitting Diode, OLED) display panel, applicable above scheme.
The foregoing is a further detailed description of the present application in conjunction with specific implementation manners, and it cannot be said that this Shen
Specific implementation please is only limited to these instructions.For those of ordinary skill in the art to which this application belongs, it is not taking off
Under the premise of from the application design, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to the protection of the application
Range.
Claims (10)
1. a kind of production method of array substrate, which is characterized in that comprising steps of
Substrate is provided；
The first metal layer and the first insulating layer is formed on the substrate；
Active layer is deposited and patterned, generates the first active layer and the second active layer；
The first insulating layer is patterned using the mask plate of second insulating layer；
Second metal layer is deposited and patterned, the position of corresponding first active layer forms channel；
Second insulating layer is deposited, forms via hole using the mask plate patterning second insulating layer of second insulating layer；
Transparent electrode layer is deposited and patterned, connect transparent electrode layer with second metal layer by via hole；
Wherein, sectional hole patterns were correspondingly arranged on the mask plate of the second insulating layer, second active layer is formed in second
The position for corresponding to sectional hole patterns of the mask plate of insulating layer.
2. a kind of production method of array substrate as described in claim 1, which is characterized in that use second insulating layer described
Mask plate the step of patterning the first insulating layer in, include the steps that the first insulating layer of binding region etching.
3. a kind of production method of array substrate as described in claim 1, which is characterized in that the width of second active layer
More than or equal to the width of the via hole.
4. a kind of production method of array substrate as described in claim 1, which is characterized in that use second insulating layer described
Mask plate pattern the first insulating layer the step of after, further include the steps that the second active layer etch.
5. a kind of array substrate characterized by comprising
Substrate and sequentially form the first metal layer on substrate, the first insulating layer, active layer, second metal layer, the second insulation
Layer and transparent electrode layer；
Wherein, the active layer includes the first active layer and the second active layer；
The second metal layer forms channel at the position of correspondence first active layer；
Via hole is formed in the second insulating layer, the transparent electrode layer is electrically connected by the via hole and the second metal layer
It connects；
Second active layer is arranged at the position of the correspondence via hole.
6. a kind of array substrate as claimed in claim 5, which is characterized in that first active layer and second active layer
It is not connected to mutually.
7. a kind of array substrate as claimed in claim 5, which is characterized in that the array substrate includes viewing area and non-display
Area, the non-display area include binding region, and the first metal layer includes grid and first electrode layer, and the grid correspondence is set
It sets at the position of the channel, the first electrode layer is arranged at the correspondence binding region, and the first electrode layer is naked
Dew.
8. a kind of array substrate as claimed in claim 5, which is characterized in that the width of second active layer is greater than or waits
In the width of the via hole.
9. a kind of array substrate as claimed in claim 5, which is characterized in that the thickness of second active layer is less than described the
The thickness of one active layer.
10. a kind of display panel, which is characterized in that including array substrate described in claim 5-9 any one.
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| CN201910275091.2A CN110176429B (en) | 2019-04-08 | 2019-04-08 | Manufacturing method of array substrate, array substrate and display panel |
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Cited By (3)
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| CN111106149A (en) * | 2019-12-04 | 2020-05-05 | 武汉华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
| CN112885847A (en) * | 2021-01-27 | 2021-06-01 | Tcl华星光电技术有限公司 | Display panel and preparation method thereof |
| CN113012566A (en) * | 2019-12-19 | 2021-06-22 | 群创光电股份有限公司 | Flexible display device and manufacturing method thereof |
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