CN103107133A

CN103107133A - Array substrate, manufacturing method thereof and displaying device

Info

Publication number: CN103107133A
Application number: CN2013100021041A
Authority: CN
Inventors: 陈华斌; 王琳琳; 高英强; 袁剑峰
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Display Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Display Technology Co Ltd
Priority date: 2013-01-04
Filing date: 2013-01-04
Publication date: 2013-05-15
Anticipated expiration: 2033-01-04
Also published as: CN103107133B

Abstract

The invention discloses an array substrate, a manufacturing method of the array substrate and a displaying device and relates to the technical method of manufacturing the array substrate through four times of Masks. The manufacturing method of the array substrate comprises manufacturing processes of a public electrode layer, a gate metal layer, a semiconductor layer, a source leakage electrode layer, a passivation layer and a pixel electrode layer, wherein the passivation layer and the pixel electrode layer are manufactured through once image composition technology. The manufacturing method of the array substrate has the advantages of being capable of saving one time of use of the Masks and reducing production cost, and suitable for manufacturing the array substrate in an advanced super dimension switch (ADS) mode.

Description

Array substrate, manufacturing method thereof and display device

Technical Field

The invention relates to the technical field of display, in particular to an array substrate, a manufacturing method thereof and a display device.

Background

At present, display products are more and more popularized in daily life of people, and related display technologies are more and more concerned by people. The display field has wide market prospect and attracts a large number of enterprises and institutions to research and develop display technology.

The TFT-LCD (Thin Film Transistor-Liquid Crystal Display) has a complex process and a high cost. Among them, the Mask process is very challenging to the precision of the equipment and process, and one more Mask process will increase the production cost, so it is very necessary to reduce the number of masks without affecting the product performance. Efforts to reduce the number of Mask processes have been directed since the invention of TFT-LCD.

As shown in fig. 1, the current method for manufacturing an array substrate in ADS (Advanced Super Dimension Switch, Advanced Super Dimension field switching) mode usually requires 5 masks, which includes: the first transparent conductive layer Mask in step 101 (the first transparent conductive layer Mask may also be referred to as a 1st ITO Mask because the transparent conductive layer usually adopts indium tin oxide ITO), the Gate Mask in step 102 (Gate Mask), the source/drain Mask in step 103 (SDT Mask), the Via Mask in step 104 (Via Hole Mask), and the second transparent conductive layer Mask in step 105 (2 nd ITO Mask). Because Mask process times required by the manufacturing method of the existing ADS mode array substrate are more, the cost of the liquid crystal display based on the ADS technology is higher, and the production efficiency cannot be improved.

Disclosure of Invention

Embodiments of the present invention provide an array substrate, a method of manufacturing the same, and a display device using the same, so as to reduce the production cost of the array substrate and improve the production efficiency.

In order to achieve the purpose, the technical scheme provided by the invention is as follows:

the manufacturing method of the array substrate comprises the manufacturing processes of a common electrode layer, a gate metal layer, a semiconductor layer, a source drain electrode layer, a passivation layer and a pixel electrode layer; wherein,

the passivation layer and the pixel electrode are formed through a one-time composition process.

Preferably, the manufacturing method includes:

step 1, forming a pattern of a common electrode on a substrate through a composition process;

step 2, forming a grid pattern on the substrate subjected to the step 1 through a composition process;

step 3, forming patterns of a semiconductor layer, a source electrode and a drain electrode on the substrate subjected to the step 2 through a composition process;

and 4, forming patterns of a pixel electrode and a passivation layer on the substrate subjected to the step 3 by adopting a one-step composition process.

Preferably, the step 4 specifically includes:

forming a passivation layer on the substrate manufactured in the step 3;

coating a first photoresist on the passivation layer, and exposing the first photoresist by using a two-tone mask plate, wherein a first photoresist complete exposure area is arranged at a corresponding through hole of the passivation layer, a first photoresist semi-exposure area is arranged at a corresponding strip-shaped pixel electrode, and a first photoresist complete reservation area is arranged at the first photoresist complete exposure area and an area outside the first photoresist semi-exposure area;

developing the exposed substrate to obtain a pattern of a first photoresist;

etching the photoresist completely removed region to form a passivation layer through hole and expose part of the source and drain electrode layer;

ashing the first photoresist by using an ashing process, and removing the photoresist in the semi-exposure area, wherein the photoresist completely-reserved area is in a slit-shaped pattern;

forming a second transparent conductive layer;

coating a second photoresist on the second transparent conducting layer, flattening the second photoresist by utilizing the fluidity of the photoresist, and enabling the thickness of the second photoresist above the first photoresist to be smaller than that of other areas except the area where the first photoresist is reserved by utilizing the thickness of the first photoresist;

ashing the second photoresist, removing the second photoresist except the reserved first photoresist, and exposing the second transparent conductive layer; (ii) a

Etching the exposed second transparent conductive layer to obtain a pixel electrode with a slit;

and stripping the residual first photoresist and the residual second photoresist to form the patterns of the passivation layer and the pixel electrode.

Preferably, the step 4 specifically includes:

forming a passivation layer on the substrate manufactured in the step 3;

developing the exposed substrate to obtain a pattern of a first photoresist;

forming a second transparent conductive layer;

and removing the photoresist in the photoresist complete reserved area through a lift-off stripping process to form the pixel electrode with the slit.

Preferably, the step 1 specifically comprises: and forming a first transparent conductive layer on the substrate, and performing a composition process by using a first transparent conductive layer mask to form a pattern of the common electrode.

Preferably, the pattern of the common electrode is a plate-shaped electrode or a slit-shaped electrode.

Preferably, the step 2 specifically comprises: and forming a gate metal film on the substrate, and performing a composition process by using a gate mask to form a pattern of the gate. 8. The method for manufacturing the array substrate according to claim 2, wherein the step 3 specifically comprises: and forming a semiconductor layer and a source-drain metal layer on the substrate, and performing a composition process by using a source-drain mask to form patterns of the source electrode, the drain electrode and the semiconductor layer.

Preferably, an ohmic contact layer is further disposed between the semiconductor layer and the source drain electrode layer.

In order to achieve the above object, the present invention further provides an array substrate manufactured by the method for manufacturing an array substrate.

In order to achieve the above object, the present invention further provides a display device, which structurally includes the array substrate.

According to the invention, through the two methods, the via hole and the pixel electrode structure can be obtained through one-time Mask process, so that one-step Mask process is reduced, and the cost is greatly reduced. The invention is suitable for manufacturing the ADS mode array substrate.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.

FIG. 1 is a schematic flow chart of a prior art manufacturing process of an array substrate;

FIG. 2 is a schematic view of a manufacturing process of the array substrate according to the present invention;

fig. 3 is a schematic plan view of an array substrate according to an embodiment of the present invention;

fig. 4 is a sectional view taken along line a-B in fig. 3 before Halftone processing is performed on the array substrate of example 1;

fig. 5 is a cross-sectional view taken along line a-B of fig. 3 after a Halftone process is performed on an array substrate according to example 1;

FIG. 6 is a cross-sectional view at A-B in FIG. 3 of a via hole resulting from etching of a passivation layer according to example 1;

FIG. 7 is a cross-sectional view taken at A-B in FIG. 3 after ashing of the first photoresist in example 1;

FIG. 8 is a cross-sectional view taken along line A-B in FIG. 3 after a second transparent conductive layer is formed in accordance with example 1;

FIG. 9 is a cross-sectional view at A-B in FIG. 3 after applying a second photoresist of example 1;

FIG. 10 is a cross-sectional view at A-B in FIG. 3 after ashing the second photoresist in example 1;

FIG. 11 is a cross-sectional view taken along line A-B of example 1 after etching a second transparent conductive layer;

FIG. 12 is a cross-sectional view taken along line A-B of FIG. 3 after stripping away the residual photoresist of example 1;

fig. 13 is a cross-sectional view taken along line a-B of fig. 3 before Halftone processing of an array substrate according to example 2;

fig. 14 is a sectional view taken along line a-B in fig. 3 after a Halftone process is performed on the array substrate according to example 2;

FIG. 15 is a cross-sectional view taken at A-B in FIG. 3 of a via hole resulting from etching of a passivation layer in accordance with example 2;

FIG. 16 is a cross-sectional view taken at A-B in FIG. 3 after photoresist ashing in accordance with example 2;

FIG. 17 is a cross-sectional view taken along line A-B of FIG. 3 after a second transparent conductive layer is deposited according to example 2;

FIG. 18 is a cross-sectional view taken at A-B in FIG. 3 after stripping away the residual photoresist of example 2.

Reference numerals: 301. 401-a substrate; 302. 402-a gate; 303. 403-common electrode; 304. 404-a gate insulating layer; 305. 405-a semiconductor layer; 306. 406-a source electrode; 307. 407-channel; 308. 408-a drain electrode; 309. 409-a passivation layer; 310. 3101-a first photoresist; 410. 4101-photoresist; 311. 411-exposure plate; 312. 412-a via; 313. 413, 3131, 4131-pixel electrode; 314. 3141-second photoresist.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

FIG. 2 shows a fourth patterning process of the present invention; the manufacturing method of the array substrate provided by the invention specifically comprises the following steps:

step 201, forming a first transparent conductive layer on a substrate, and obtaining a pattern of a common electrode by using a first transparent conductive layer mask;

202, forming a gate metal layer on a substrate by adopting a sputtering or evaporation technology, and obtaining a pattern of a gate by adopting a gate mask;

step 203, forming a semiconductor layer and a source-drain metal layer on the substrate by adopting a sputtering or evaporation technology, and obtaining patterns of a source electrode, a drain electrode and an active layer by utilizing a source-drain electrode mask;

and 204, coating a passivation layer, and obtaining patterns of the passivation layer and the pixel electrode through a mask process.

The pattern of the common electrode is a plate-shaped electrode or a slit-shaped electrode.

And an ohmic contact layer is also arranged between the semiconductor layer and the source drain electrode layer, so that the contact resistance between the semiconductor and the source drain electrode is reduced.

The technical solutions provided by the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

Example 1

Referring to fig. 4 to 12, the method for manufacturing an array substrate according to the present embodiment includes the following steps:

step F1, depositing a first transparent conductive film on the substrate 301, and forming a pattern of the common electrode 303 through a patterning process;

in step F1, the substrate 301 may be a substrate made of an inorganic material such as a glass substrate or a quartz substrate, or may be a substrate made of an organic material;

the material of the first transparent conductive film may be Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), or the like.

Step F2, forming a gate metal film on the substrate on which the pattern is formed, and forming the pattern of the gate electrode 302 by a patterning process;

step F3, sequentially forming a gate insulating film, a semiconductor layer film, and a source-drain metal film on the substrate on which the above-described pattern is formed, and forming a pattern including the semiconductor layer 305, the source electrode 306, and the drain electrode 308 by a patterning process;

step F41, sequentially forming a passivation layer 309 and a first photoresist 310 on the substrate with the above pattern, and exposing through a dual-tone mask 311 as shown in fig. 4, wherein the dual-tone mask includes: the gray tone mask plate and the semi-permeable membrane mask plate transfer the pattern to the first photoresist 310 by adopting full exposure and semi-exposure technologies, specifically comprising: a completely exposed area of the first photoresist 310 is located at the position corresponding to the via hole 312 of the passivation layer 309, a semi-exposed area of the first photoresist 310 is located at the position corresponding to the strip-shaped pixel electrode 313, and a completely reserved area of the first photoresist 310 is located at the area outside the completely exposed area of the first photoresist 310 and the semi-exposed area of the first photoresist 310, as shown in fig. 5;

step F42, removing the passivation layer 309 at the via 312 by a patterning process on the substrate 301 with the above pattern to form a pattern of the via 312, see fig. 6, where the via 312 is formed on the passivation layer 309 and exposes the drain electrode 308;

step F43, uniformly thinning the first photoresist 310 on the substrate 301 with the pattern formed thereon by using an ashing technique, wherein the first photoresist 310 in the unexposed region is retained, and the retained first photoresist 310 is in a slit-shaped pattern, and the region not retaining the first photoresist 310 is etched to the passivation layer 309 to obtain the final pattern, as shown in fig. 7;

step F44, forming a second transparent conductive film on the substrate 301 with the above pattern, which may be formed by sputtering or evaporation, wherein the pattern shape of the first photoresist 310 causes the pixel electrode 313 to have a pattern with a slit-shaped structure, as shown in fig. 8;

step F45, coating a second layer of photoresist 314 on the substrate 301 with the pattern formed thereon to obtain the pattern shown in fig. 9; then, performing an ashing process on the second photoresist 314 to expose the second transparent conductive layer 313 above the

first photoresist

310 and 3101, thereby obtaining a pattern as shown in fig. 10;

step F46, etching the exposed second transparent conductive layer 313 to obtain the pattern shown in fig. 11;

step F47, finally, stripping all the remaining first photoresist 310 and second photoresist 314 to obtain the pattern shown in fig. 12; wherein, a stripe pattern is formed in the pixel electrode region.

A schematic plan view of the fabricated array substrate can be seen from fig. 3, where a-B only indicate the positions where the cross-section is taken, and do not relate to a specific array substrate structure.

Among them, the formation of the thin film involved in the present embodiment includes: deposition, coating, sputtering, printing, and the like; the related patterning process comprises the following steps: coating photoresist, sputtering, evaporation, exposure and development, etching, ashing, removing the photoresist and the like.

Example 2

Referring to fig. 13 to 18, the method for manufacturing an array substrate according to the present embodiment includes the following steps:

step S1, forming a first transparent conductive film on the substrate 401, and forming a pattern of the common electrode 403 by a patterning process using a first transparent conductive layer mask;

in step S1, the substrate 301 may be a substrate made of an inorganic material such as a glass substrate or a quartz substrate, or may be a substrate made of an organic material;

Step S2, forming a gate metal film on the substrate 401 on which the pattern is formed, and forming the pattern of the gate electrode 402 by a patterning process using a gate mask;

step S3, sequentially forming a gate insulating layer film, a semiconductor layer film, and a source-drain metal film on the substrate 401 on which the pattern is formed, and forming a pattern including the semiconductor layer 405, the source electrode 406, and the drain electrode 408 by a patterning process using a source-drain mask;

step S41, sequentially forming a passivation layer 409 and a photoresist layer 410 on the substrate 401 with the above pattern, and exposing the substrate with a two-tone mask 411 as shown in fig. 13, wherein the two-tone mask comprises: the gray tone mask plate and the semi-permeable membrane mask plate transfer the patterns to the photoresist layer 410 by adopting full exposure and semi-exposure technologies, and specifically comprises the following steps: a completely exposed area of the first photoresist 310 is located at the position corresponding to the via hole 312 of the passivation layer 309, a semi-exposed area of the first photoresist 310 is located at the position corresponding to the strip-shaped pixel electrode 313, and a completely reserved area of the first photoresist 310 is located at the area outside the completely exposed area of the first photoresist 310 and the semi-exposed area of the first photoresist 310, as shown in fig. 14;

step S42, removing the passivation layer 409 at the via 412 through a patterning process on the substrate 401 with the above pattern formed thereon, and forming a pattern of the via 412, see fig. 15, where the via 412 is formed on the passivation layer 409 and exposes the drain electrode 408;

step S43, uniformly thinning the photoresist 410 on the substrate 401 on which the pattern is formed by using an ashing technique, wherein the photoresist 410 in the unexposed region is remained, the remained photoresist 410 is in a strip pattern, and the region not remaining the photoresist 410 is etched to the passivation layer 409 to obtain the final pattern, as shown in fig. 16;

step S44, forming a second transparent conductive film on the substrate 401 with the above-mentioned pattern, which may be formed by sputtering or evaporation, wherein the pixel electrode 413 is in a slit-like pattern due to the pattern shape of the photoresist 410, as shown in fig. 17;

step S45, stripping off the

residual photoresists

410 and 4101 directly from the ground on the substrate 401 with the patterns formed thereon, and simultaneously removing the

residual photoresists

410 and 4101 and the second transparent conductive films thereon, thereby finally obtaining the patterns shown in fig. 18; wherein, the pixel electrode region forms a slit-shaped structure.

Example 3

This embodiment describes an array substrate manufactured by the method of manufacturing the array substrate of embodiment 1 or 2.

Example 4

This embodiment describes a display device including the array substrate manufactured in embodiment 3.

The display device may be: the display device comprises any product or component with a display function, such as a liquid crystal panel, electronic paper, an OLED panel, a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

For example, for a liquid crystal display device, the array substrate and the color film substrate need to be aligned, then peripheral circuits and frames need to be added to obtain a display module, then the display module is assembled with a backlight module and a control circuit system, and finally a shell and a base are added to obtain a final complete liquid crystal display device.

It will be understood by those skilled in the art that the pixel electrode may be plate-shaped or slit-shaped, as may the common electrode, and the up-down order of the pixel electrode and the common electrode may be reversed, but the upper electrode must be slit-shaped, and the lower electrode may be plate-shaped or slit-shaped.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. The manufacturing method of the array substrate is characterized by comprising the manufacturing processes of a common electrode layer, a gate metal layer, a semiconductor layer, a source drain electrode layer, a passivation layer and a pixel electrode layer; wherein,

2. The method for manufacturing the array substrate according to claim 1, wherein the method comprises:

3. The method for manufacturing the array substrate according to claim 1 or 2, wherein the step 4 specifically comprises:

forming a passivation layer on the substrate manufactured in the step 3;

developing the exposed substrate to obtain a pattern of a first photoresist;

forming a second transparent conductive layer;

4. The method for manufacturing the array substrate according to claim 1 or 2, wherein the step 4 specifically comprises:

forming a passivation layer on the substrate manufactured in the step 3;

developing the exposed substrate to obtain a pattern of a first photoresist;

forming a second transparent conductive layer;

5. The method for manufacturing the array substrate according to claim 2, wherein the step 1 specifically comprises: and forming a first transparent conductive layer on the substrate, and performing a composition process by using a first transparent conductive layer mask to form a pattern of the common electrode.

6. The method of claim 5, wherein the pattern of the common electrode is a plate-shaped electrode or a slit-shaped electrode.

7. The method for manufacturing the array substrate according to claim 2, wherein the step 2 is specifically as follows: and forming a gate metal film on the substrate, and performing a composition process by using a gate mask to form a pattern of the gate.

8. The method for manufacturing the array substrate according to claim 2, wherein the step 3 specifically comprises: and forming a semiconductor layer and a source-drain metal layer on the substrate, and performing a composition process by using a source-drain mask to form patterns of the source electrode, the drain electrode and the semiconductor layer.

9. The manufacturing method of the array substrate according to claim 1 or 2, wherein an ohmic contact layer is further arranged between the semiconductor layer and the source drain electrode layer.

10. An array substrate manufactured by the method of any one of claims 1 to 8.

11. A display device comprising the array substrate according to claim 9.