CN103107133A - Array substrate, manufacturing method thereof and displaying device - Google Patents

Array substrate, manufacturing method thereof and displaying device Download PDF

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Publication number
CN103107133A
CN103107133A CN2013100021041A CN201310002104A CN103107133A CN 103107133 A CN103107133 A CN 103107133A CN 2013100021041 A CN2013100021041 A CN 2013100021041A CN 201310002104 A CN201310002104 A CN 201310002104A CN 103107133 A CN103107133 A CN 103107133A
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photoresist
described
layer
pattern
form
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CN2013100021041A
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CN103107133B (en
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陈华斌
王琳琳
高英强
袁剑峰
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Abstract

The invention discloses an array substrate, a manufacturing method of the array substrate and a displaying device and relates to the technical method of manufacturing the array substrate through four times of Masks. The manufacturing method of the array substrate comprises manufacturing processes of a public electrode layer, a gate metal layer, a semiconductor layer, a source leakage electrode layer, a passivation layer and a pixel electrode layer, wherein the passivation layer and the pixel electrode layer are manufactured through once image composition technology. The manufacturing method of the array substrate has the advantages of being capable of saving one time of use of the Masks and reducing production cost, and suitable for manufacturing the array substrate in an advanced super dimension switch (ADS) mode.

Description

Array base palte and manufacture method thereof and display unit

Technical field

The present invention relates to the Display Technique field, relate in particular to array base palte and manufacture method thereof and display unit.

Background technology

At present, show that product is more and more universal in people's daily life, relevant Display Technique also more and more receives people's concern.The demonstration field has wide market prospects, and has attracted a large amount of enterprises, institutes to be engaged in the research and development of Display Technique.

TFT-LCD(Thin Film Transistor-Liquid Crystal Display, Thin Film Transistor-LCD) complex process, cost are higher.Wherein, Mask(mask plate) technical process extremely tests the precision of equipment and process, and it is a lot of that many Mask techniques can make production cost increase, and is very important therefore reduce the quantity of Mask on the basis that does not affect properties of product.People are devoted to reduce the work of Mask number of processes always since the TFT-LCD invention.

as shown in Figure 1, present ADS(Advanced Super Dimension Switch, a senior super dimension switch technology) array substrate manufacturing method of pattern needs 5 Mask usually, comprise: the ground floor transparency conducting layer mask plate in step 101 is (because transparency conducting layer adopts tin indium oxide ITO usually, therefore ground floor transparency conducting layer mask plate also can be described as 1st ITO Mask), gate mask version in step 102 (Gate Mask), source-drain electrode mask plate in step 103 (SDT Mask), via hole mask plate in step 104 (Via Hole Mask), second layer transparency conducting layer mask plate in step 105 (2nd ITO Mask).Because the Mask technique number of times that the manufacture method of existing ADS pattern array substrate needs is many, make based on the cost of the liquid crystal display of ADS technology highlyer, and production efficiency can't get a promotion.

Summary of the invention

Embodiments of the invention provide a kind of array base palte and manufacture method thereof, and the display unit of using this array base palte, in order to the production cost that reduces array base palte and enhance productivity.

For achieving the above object, technical scheme provided by the invention is as follows:

A kind of manufacturing method of array base plate comprises the manufacturing process of common electrode layer, grid metal level, semiconductor layer, source-drain electrode layer, passivation layer and pixel electrode layer; Wherein,

Described passivation layer and described pixel electrode form by a composition technique.

Preferably, described manufacture method comprises:

Step 1, form the pattern of public electrode by composition technique on substrate;

Step 2, through form the pattern of grid on the substrate of described step 1 by composition technique;

Step 3, through form the pattern of semiconductor layer, source electrode and drain electrode on described step 2 described substrate by composition technique;

Step 4, through adopting composition technique to form the pattern of pixel electrode and passivation layer on described step 3 described substrate.

Preferably, described step 4 specifically comprises:

Form passivation layer on the substrate that described step 3 is made;

Apply again the first photoresist on described passivation layer, and utilize the duotone mask plate that the first photoresist is exposed, wherein, corresponding passivation layer via hole place is the first photoresist complete exposure area, corresponding strip pixel electrode place is the first photoresist half exposure area, is the first complete reserve area of photoresist to the zone beyond described the first photoresist complete exposure area and described the first photoresist half exposure area;

Substrate after exposure is developed, obtain the pattern of the first photoresist;

Described photoresist is removed the zone fully carry out etching, form passivation layer via hole, and expose part source-drain electrode layer;

Utilize cineration technics to carry out ashing to the first photoresist, remove the photoresist of described half exposure area, the complete reserve area of described photoresist is the slit-shaped pattern;

Form the second transparency conducting layer;

Apply the second photoresist on described the second transparency conducting layer, utilize the mobility of photoresist to make described the second photoresist planarization, utilize the thickness of described the first photoresist, make the thickness of the second photoresist of described the first photoresist top less than other zones, the zone except reservation the first photoresist;

The second photoresist is carried out ashing, remove described reservation the first photoresist with the second photoresist of exterior domain, and expose described the second transparency conducting layer;

The described second layer transparency conducting layer that exposes is carried out etching, obtain having the pixel electrode of slit;

The first residual photoresist and the second photoresist are peeled off, formed the pattern of described passivation layer and pixel electrode.

Preferably, described step 4 specifically comprises:

Form passivation layer on the substrate that described step 3 is made;

Apply again the first photoresist on described passivation layer, and utilize the duotone mask plate that the first photoresist is exposed, wherein, corresponding passivation layer via hole place is the first photoresist complete exposure area, corresponding strip pixel electrode place is the first photoresist half exposure area, is the first complete reserve area of photoresist to the zone beyond described the first photoresist complete exposure area and described the first photoresist half exposure area;

Substrate after exposure is developed, obtain the pattern of the first photoresist;

Described photoresist is removed the zone fully carry out etching, form passivation layer via hole, and expose part source-drain electrode layer;

Utilize cineration technics to carry out ashing to the first photoresist, remove the photoresist of described half exposure area, the complete reserve area of described photoresist is the slit-shaped pattern;

Form the second transparency conducting layer;

Remove the photoresist of the complete reserve area of photoresist by liftoff stripping technology, form the pixel electrode with slit.

Preferably, described step 1 is specially: form the first transparency conducting layer on substrate, utilize the first transparency conducting layer mask plate to carry out composition technique to form the pattern of public electrode.

Preferably, the pattern of described public electrode is plate electrode or slit-shaped electrode.

Preferably, described step 2 is specially: form the grid metallic film on substrate, adopt the gate mask version to carry out the pattern that composition technique forms grid.8, manufacturing method of array base plate according to claim 2, it is characterized in that, described step 3 is specially: form semiconductor layer and source leakage metal level on substrate, utilize the source-drain electrode mask plate to carry out composition technique to form the pattern of source electrode, drain electrode and semiconductor layer.

Preferably, also be provided with ohmic contact layer between semiconductor layer and source-drain electrode layer.

To achieve these goals, the present invention also provides a kind of array base palte, and this array base palte adopts the manufacture method manufacturing of above-mentioned array base palte.

To achieve these goals, the present invention also provides a kind of display unit, and the structure of this display unit comprises above-mentioned array base palte.

The present invention only can obtain via hole and pixel electrode structure by a mask plate technique by top described two kinds of methods, has reduced by a step Mask technical process, greatly reduces cost.The present invention is applicable to the manufacturing of ADS pattern array substrate.

Description of drawings

In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, during the below will describe embodiment, the accompanying drawing of required use is done to introduce simply, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.

Fig. 1 is the array base palte fabrication processing schematic diagram of prior art;

Fig. 2 is array base palte fabrication processing schematic diagram of the present invention;

The floor map of the array base palte that Fig. 3 provides for the embodiment of the present invention;

Fig. 4 is the sectional view that embodiment 1 pair array substrate carries out the place of A-B in Fig. 3 before Halftone technique;

Fig. 5 is the sectional view at A-B place in Fig. 3 after embodiment 1 pair array substrate carries out Halftone technique;

Fig. 6 is the sectional view that obtains the place of A-B in Fig. 3 of via hole after embodiment 1 etching passivation layer;

Fig. 7 is the sectional view at A-B place in Fig. 3 after 1 pair of the first photoresist ashing of embodiment;

Fig. 8 is the sectional view at A-B place in Fig. 3 after embodiment 1 forms the second transparency conducting layer;

Fig. 9 is the sectional view at A-B place in Fig. 3 after embodiment 1 applies the second photoresist;

Figure 10 is the sectional view at A-B place in Fig. 3 after embodiment 1 ashing the second photoresist;

Figure 11 is the sectional view at A-B place in 3 after embodiment 1 etching the second transparency conducting layer;

Figure 12 is the sectional view at A-B place in Fig. 3 after embodiment 1 peels off residual photoresist;

Figure 13 is the sectional view that embodiment 2 pair array substrates carry out the place of A-B in Fig. 3 before Halftone technique;

Figure 14 is the sectional view at A-B place in Fig. 3 after embodiment 2 pair array substrates carry out Halftone technique;

Figure 15 is the sectional view that obtains the place of A-B in Fig. 3 of via hole after embodiment 2 etching passivation layers;

Figure 16 is the sectional view at A-B place in Fig. 3 after 2 pairs of photoresist ashings of embodiment;

Figure 17 is the sectional view at A-B place in Fig. 3 after embodiment 2 deposition the second transparency conducting layers;

Figure 18 is the sectional view at A-B place in Fig. 3 after embodiment 2 peels off residual photoresist.

Reference numeral: 301,401-substrate; 302,402-grid; 303,403-public electrode; 304,404-gate insulation layer; 305,405-semiconductor layer; 306,406-source electrode; 307,407-raceway groove; 308,408-drain electrode; 309,409-passivation layer; 310,3101-the first photoresist; 410,4101-photoresist; 311,411-exposed plate; 312,412-via hole; 313,413,3131,4131-pixel electrode; 314,3141-the second photoresist.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.

Be illustrated in figure 2 as four composition techniques of the present invention; The manufacture method of array base palte provided by the present invention specifically comprises:

Step 201, form the first transparency conducting layer on substrate, utilize the first transparency conducting layer mask plate to obtain the pattern of public electrode;

The technology of step 202, employing sputter or evaporation forms the grid metal level on substrate, adopt the gate mask version to obtain the pattern of grid;

The technology of step 203, employing sputter or evaporation forms semiconductor layer on substrate and metal level is leaked in the source, utilizes the source-drain electrode mask plate to obtain the pattern of source electrode, drain electrode and active layer;

Step 204, apply passivation layer, obtain the pattern of passivation layer and pixel electrode by mask plate technique.

The pattern of described public electrode is plate electrode or slit-shaped electrode.

Also be provided with ohmic contact layer between semiconductor layer and source-drain electrode layer, reduce the contact resistance between semiconductor and source-drain electrode.

Below in conjunction with accompanying drawing, the technical scheme that the embodiment of the present invention provides is described in detail.

Embodiment 1

To shown in Figure 12, the manufacturing method of array base plate that provides in the present embodiment comprises the following steps in conjunction with Fig. 4:

Step F 1, on substrate 301 deposition the first transparent conductive film, form the pattern of public electrode 303 by composition technique;

In step F 1, aforesaid substrate 301 can be glass substrate, quartz base plate etc. based on the underlay substrate of inorganic material, can be also the underlay substrate that adopts organic material;

The material of above-mentioned ground floor transparent conductive film can be tin indium oxide (ITO), indium zinc oxide (IZO, Indium Zinc Oxide) etc.

Step F 2, form the grid metallic film on the substrate of above-mentioned pattern forming, form the pattern of gate electrode 302 by composition technique;

Step F 3, form successively gate insulation layer film, semiconductor layer film and source on the substrate of above-mentioned pattern and leak metallic film forming, form the pattern that comprises semiconductor layer 305, source electrode 306 and drain electrode 308 by composition technique;

step F 41, form successively passivation layer 309 on the substrate that forms above-mentioned pattern, the first photoresist 310, as shown in Figure 4, by 311 exposures of duotone mask plate, described duotone mask plate comprises: gray mask plate and pellicle mask plate, adopt full exposure and half exposure technique with pattern transfer to described the first photoresist 310, be specially: corresponding passivation layer 309 via hole 312 places are the first photoresist 310 complete exposure area, corresponding strip pixel electrode 313 places are the first photoresist 310 half exposure areas, be the first complete reserve area of photoresist 310 to described the first photoresist 310 complete exposure area and described the first zone in addition, photoresist 310 half exposure areas, see Fig. 5,

Step F 42, forming the passivation layer 309 of removing via hole 312 places on the substrate 301 of above-mentioned pattern by composition technique, forming the pattern of via hole 312, seeing Fig. 6, described via hole 312 is formed on described passivation layer 309 and described drain electrode 308 is come out;

Step F 43, utilize the ashing technology that the first photoresist 310 is evenly thinned forming on the substrate 301 of above-mentioned pattern, the first photoresist 310 of exposure area does not keep, the first photoresist 310 that keeps is the slit-shaped pattern, the zone that need not keep the first photoresist 310 is etched to passivation layer 309, the pattern that finally obtains is seen Fig. 7;

Step F 44, form the second transparent conductive film on the substrate 301 of above-mentioned pattern forming, specifically can adopt the method for sputter or evaporation to form, because the pattern form of the first photoresist 310 makes pixel electrode 313 present the pattern of slit-shaped structure, see Fig. 8;

Step F 45, carry out again layer photoetching glue 314 on the substrate 301 of above-mentioned pattern and apply forming, obtain pattern as shown in Figure 9; Then the second photoresist 314 is carried out cineration technics, make the second transparency conducting layer 313 of the first photoresist 310,3101 tops, place come out, obtain pattern as shown in figure 10;

Step F 46, the second transparency conducting layer 313 that comes out is carried out etching, obtain pattern as shown in figure 11;

Step F 47, at last all first residual photoresists 310 and the second photoresist 314 are peeled off, finally obtained pattern as shown in figure 12; Wherein, form strip pattern in pixel electrode area.

The floor map of the array base palte of made as seen from Figure 3, wherein A-B only represents the position that the cross section intercepts, and does not relate to concrete array base-plate structure.

Wherein, the formation that relates in the present embodiment film comprises: the methods such as deposition, coating, sputter, printing; Related composition technique comprises: apply the operations such as photoresist, sputter, evaporation, exposure imaging, etching, ashing and removal photoresist.

Embodiment 2

To shown in Figure 180, the manufacturing method of array base plate that provides in the present embodiment comprises the following steps in conjunction with Figure 13:

Step S1, form the ground floor transparent conductive film on substrate 401, adopt the first transparency conducting layer mask plate to form the pattern of public electrode 403 by composition technique;

In step S1, aforesaid substrate 301 can be glass substrate, quartz base plate etc. based on the underlay substrate of inorganic material, can be also the underlay substrate that adopts organic material;

The material of above-mentioned the first transparent conductive film can be tin indium oxide (ITO), indium zinc oxide (IZO, Indium Zinc Oxide) etc.

Step S2, form the grid metallic film on the substrate 401 of above-mentioned pattern forming, adopt the gate mask version to form the pattern of gate electrode 402 by composition technique;

Step S3, form successively gate insulation layer film, semiconductor layer film and source on the substrate 401 of above-mentioned pattern and leak metallic film forming, adopt the source-drain electrode mask plate to form the pattern that comprises semiconductor layer 405, source electrode 406 and drain electrode 408 by composition technique;

step S41, form successively passivation layer 409 on the substrate 401 that forms above-mentioned pattern, photoresist layer 410, as shown in figure 13, by 411 exposures of duotone mask plate, described duotone mask plate comprises: gray mask plate and pellicle mask plate, adopt full exposure and half exposure technique with pattern transfer to described photoresist layer 410, be specially: corresponding passivation layer 309 via hole 312 places are the first photoresist 310 complete exposure area, corresponding strip pixel electrode 313 places are the first photoresist 310 half exposure areas, be the first complete reserve area of photoresist 310 to described the first photoresist 310 complete exposure area and described the first zone in addition, photoresist 310 half exposure areas, see Figure 14,

Step S42, forming the passivation layer 409 of removing via hole 412 places on the substrate 401 of above-mentioned pattern by composition technique, forming the pattern of via hole 412, seeing Figure 15, described via hole 412 is formed on described passivation layer 409 and described drain electrode 408 is come out;

Step S43, utilize the ashing technology that photoresist 410 is evenly thinned forming on the substrate 401 of above-mentioned pattern, the photoresist 410 of exposure area does not keep, the photoresist 410 that keeps is strip pattern, the zone that need not keep photoresist 410 is etched to passivation layer 409, the pattern that finally obtains is seen Figure 16;

Step S44, form second layer transparent conductive film on the substrate 401 of above-mentioned pattern forming, specifically can adopt the method for sputter or evaporation to form, because the pattern form of photoresist 410 makes pixel electrode 413 present the pattern of slit-shaped, see Figure 17;

Step S45, directly residual photoresist 410,4101 is carried out liftoff peeling off forming on the substrate 401 of above-mentioned pattern, remove simultaneously residual photoresist 410,4101 and the second transparent conductive film above it, finally obtain pattern as shown in figure 18; Wherein, pixel electrode area forms the slit-shaped structure.

The floor map of the array base palte of made as seen from Figure 3, wherein A-B only represents the position that the cross section intercepts, and does not relate to concrete array base-plate structure.

The formation of the film that wherein, relates in the present embodiment comprises: the methods such as deposition, coating, sputter, printing; Related composition technique comprises: apply the operations such as photoresist, sputter, evaporation, exposure imaging, etching, ashing and removal photoresist.

Embodiment 3

The present embodiment has been introduced a kind of array base palte, and this array base palte utilizes the manufacture method manufacturing of array base palte in embodiment 1 or 2.

Embodiment 4

The present embodiment has been introduced a kind of display unit, and this display unit comprises the display unit of the array base palte of making in embodiment 3.

Described display unit can be any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.

For example, for liquid crystal indicator, need first described array base palte and color membrane substrates box, the circuit and the frame that increase periphery obtain showing module again, with backlight module and control circuit system assembles, add at last shell and base again, obtain final complete liquid crystal indicator.

It will be understood by those skilled in the art that pixel electrode can be tabular or slit-shaped, public electrode is also like this, the order up and down of pixel electrode and public electrode can be put upside down, but must be slit-shaped at upper electrode, under electrode can be tabular, perhaps slit-shaped.

The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement are within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.

Claims (11)

1. a manufacturing method of array base plate, is characterized in that, comprises the manufacturing process of common electrode layer, grid metal level, semiconductor layer, source-drain electrode layer, passivation layer and pixel electrode layer; Wherein,
Described passivation layer and described pixel electrode form by a composition technique.
2. manufacturing method of array base plate according to claim 1, is characterized in that, described manufacture method comprises:
Step 1, form the pattern of public electrode by composition technique on substrate;
Step 2, through form the pattern of grid on the substrate of described step 1 by composition technique;
Step 3, through form the pattern of semiconductor layer, source electrode and drain electrode on described step 2 described substrate by composition technique;
Step 4, through adopting composition technique to form the pattern of pixel electrode and passivation layer on described step 3 described substrate.
3. manufacturing method of array base plate according to claim 1 and 2, is characterized in that, described step 4 specifically comprises:
Form passivation layer on the substrate that described step 3 is made;
Apply again the first photoresist on described passivation layer, and utilize the duotone mask plate that the first photoresist is exposed, wherein, corresponding passivation layer via hole place is the first photoresist complete exposure area, corresponding strip pixel electrode place is the first photoresist half exposure area, is the first complete reserve area of photoresist to the zone beyond described the first photoresist complete exposure area and described the first photoresist half exposure area;
Substrate after exposure is developed, obtain the pattern of the first photoresist;
Described photoresist is removed the zone fully carry out etching, form passivation layer via hole, and expose part source-drain electrode layer;
Utilize cineration technics to carry out ashing to the first photoresist, remove the photoresist of described half exposure area, the complete reserve area of described photoresist is the slit-shaped pattern;
Form the second transparency conducting layer;
Apply the second photoresist on described the second transparency conducting layer, utilize the mobility of photoresist to make described the second photoresist planarization, utilize the thickness of described the first photoresist, make the thickness of the second photoresist of described the first photoresist top less than other zones, the zone except reservation the first photoresist;
The second photoresist is carried out ashing, remove described reservation the first photoresist with the second photoresist of exterior domain, and expose described the second transparency conducting layer;
The described second layer transparency conducting layer that exposes is carried out etching, obtain having the pixel electrode of slit;
The first residual photoresist and the second photoresist are peeled off, formed the pattern of described passivation layer and pixel electrode.
4. manufacturing method of array base plate according to claim 1 and 2, is characterized in that, described step 4 specifically comprises:
Form passivation layer on the substrate that described step 3 is made;
Apply again the first photoresist on described passivation layer, and utilize the duotone mask plate that the first photoresist is exposed, wherein, corresponding passivation layer via hole place is the first photoresist complete exposure area, corresponding strip pixel electrode place is the first photoresist half exposure area, is the first complete reserve area of photoresist to the zone beyond described the first photoresist complete exposure area and described the first photoresist half exposure area;
Substrate after exposure is developed, obtain the pattern of the first photoresist;
Described photoresist is removed the zone fully carry out etching, form passivation layer via hole, and expose part source-drain electrode layer;
Utilize cineration technics to carry out ashing to the first photoresist, remove the photoresist of described half exposure area, the complete reserve area of described photoresist is the slit-shaped pattern;
Form the second transparency conducting layer;
Remove the photoresist of the complete reserve area of photoresist by liftoff stripping technology, form the pixel electrode with slit.
5. manufacturing method of array base plate according to claim 2, is characterized in that, described step 1 is specially: form the first transparency conducting layer on substrate, utilize the first transparency conducting layer mask plate to carry out composition technique to form the pattern of public electrode.
6. manufacturing method of array base plate according to claim 5, is characterized in that, the pattern of described public electrode is plate electrode or slit-shaped electrode.
7. manufacturing method of array base plate according to claim 2, is characterized in that, described step 2 is specially: form the grid metallic film on substrate, adopt the gate mask version to carry out the pattern that composition technique forms grid.
8. manufacturing method of array base plate according to claim 2, it is characterized in that, described step 3 is specially: form semiconductor layer and source leakage metal level on substrate, utilize the source-drain electrode mask plate to carry out composition technique to form the pattern of source electrode, drain electrode and semiconductor layer.
9. manufacturing method of array base plate according to claim 1 and 2, is characterized in that, also is provided with ohmic contact layer between semiconductor layer and source-drain electrode layer.
10. an array base palte, is characterized in that, the array base palte of this array base palte for adopting the arbitrary described manufacturing method of array base plate of claim 1-8 to make.
11. a display unit is characterized in that, this display unit comprises the arbitrary described array base palte of claim 9.
CN201310002104.1A 2013-01-04 2013-01-04 Array substrate, manufacturing method thereof and displaying device CN103107133B (en)

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