CN108183108A - The production method and array substrate and display device of a kind of array substrate - Google Patents

The production method and array substrate and display device of a kind of array substrate Download PDF

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Publication number
CN108183108A
CN108183108A CN201711462028.7A CN201711462028A CN108183108A CN 108183108 A CN108183108 A CN 108183108A CN 201711462028 A CN201711462028 A CN 201711462028A CN 108183108 A CN108183108 A CN 108183108A
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China
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layer
planarization layer
array substrate
source electrode
production
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CN201711462028.7A
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Chinese (zh)
Inventor
罗浩
张毅先
任思雨
苏君海
李建华
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信利(惠州)智能显示有限公司
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Priority to CN201711462028.7A priority Critical patent/CN108183108A/en
Publication of CN108183108A publication Critical patent/CN108183108A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1296Multistep manufacturing methods adapted to increase the uniformity of device parameters
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/28Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
    • H01L27/32Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes [OLED]
    • H01L27/3241Matrix-type displays
    • H01L27/3244Active matrix displays
    • H01L27/3248Connection of the pixel electrode to the TFT

Abstract

The production method and array substrate of a kind of array substrate, production method include the following steps:The thin film transistor (TFT) for including source electrode and drain electrode is formed on substrate;Passivation layer is formed in source electrode and drain electrode;The first via corresponding with source electrode and the drain electrode is formed on the passivation layer;Planarization layer is formed on the passivation layer;Development exposure-processed is carried out to planarization layer, second is formed on planarization layer and crosses sectional hole patterns;Ashing processing is carried out to planarization layer using oxygen, the second via is formed on planarization layer, the second via is aligned with the first via;Secondary ashing processing is carried out to planarization layer using reducing agent.In the production method of above-mentioned array substrate, by using O2Ashing processing is carried out to the planarization layer that sectional hole patterns are crossed containing second with reducing agent, reduces source electrode or drain electrode and the overlap resistance of anode electrode, the bad problems such as fever, color displays unevenness and power consumption height occurs when in use in the screen for avoiding array substrate.

Description

The production method and array substrate and display device of a kind of array substrate

Technical field

The present invention relates to technical field of flat panel display, production method and array base more particularly to a kind of array substrate Plate.

Background technology

With the development of FPD, high-resolution, the panel demand of low energy consumption is constantly suggested.Wherein AMOLED (has Source matrix Organic Light Emitting Diode) panel is because its colour gamut is wide, contrast is high, high resolution, frivolous, low in energy consumption, fast response time And have the advantages that the LCD such as flexibility (liquid crystal display) are difficult to, obtain the highest attention in market and industry

The array substrate of AMOLED panel includes LTPS TFT (low-temperature polysilicon film transistor), passivation layer, planarization Layer and anode etc., LTPS TFT include polysilicon semiconductor layer and source/drain with high mobility, source/drain and polysilicon Semiconductor layer connects, AMOLED anodes by passivation layer via hole and planarization layer ashing realize with the overlap joint of source/drain, pass through to Polysilicon semiconductor layer and source/drain provide electric current, and then drive the anode of AMOLED.However, in traditional making array base During plate, generally use CF4 and O2 mixed gas performs etching passivation layer, and ash is carried out to planarization layer using oxygen Change, since the Facing material of source/drain is metal, in passivation layer etching and podzolic process, the presence of oxygen leads to source/drain The metal part on surface is oxidized to metal oxide, and the overlap resistance so as to cause source/drain and the anode of AMOLED is bigger than normal, And then the screen of the array substrate made containing the above method is caused to occur fever, color displays unevenness and power consumption height when in use Etc. bad problem, wherein, the resistance that when positive contact of the overlap resistance for source/drain and AMOLED generates.

Invention content

Based on this, it is necessary to provide a kind of making for the array substrate for reducing the contact resistance between anode and source/drain Method and array substrate and display device.

A kind of production method of array substrate, includes the following steps:The film for including source electrode and drain electrode is formed on substrate Transistor;Passivation layer is formed in source electrode and drain electrode;It is formed on the passivation layer corresponding with the source electrode and the drain electrode First via;Planarization layer is formed on the passivation layer;Development exposure-processed is carried out to the planarization layer, described flat Change formation second on layer and cross sectional hole patterns;Ashing processing is carried out to the planarization layer using oxygen, the shape on the planarization layer Into the second via, second via is aligned with first via;Secondary ash is carried out to the planarization layer using reducing agent Change is handled.

The reducing agent includes hydrogen in one of the embodiments,.

The temperature of the hydrogen is 90 DEG C in one of the embodiments,.

The material of the planarization layer is organic insulation in one of the embodiments,.

The thickness of the planarization layer is 1.8 μm~3.2 μm in one of the embodiments,.

It is described in one of the embodiments, that development exposure imaging processing is carried out to the planarization layer, described flat Change formation second on layer to cross after sectional hole patterns, further include following steps:In 250 DEG C~350 DEG C temperature ranges, to described flat Change layer and carry out quiescence in high temperature.

The source electrode and the drain electrode include titanium layer stacked on top of each other, aluminium layer and molybdenum in one of the embodiments, Layer.

The source electrode and the drain electrode include titanium layer stacked on top of each other, aluminium layer and chromium in one of the embodiments, Layer.

A kind of array substrate makes to obtain using the production method of array substrate described in any of the above-described.

A kind of display device, including organic electroluminescence device and the array substrate, the organic electroluminescence Part includes anode, cathode and luminescent layer, and the luminescent layer is between the anode and the cathode, the organic electroluminescence hair The anode of optical device is connect with the source/drain of the array substrate.

The production method and its array substrate of above-mentioned array substrate, in the production method of array substrate, by using O2 Ashing processing is carried out to the planarization layer that sectional hole patterns are crossed containing second with reducing agent, is remained after removing the exposed and developed technique of yellow light Planarization layer material, the metal part for preferably avoiding source electrode or drain surface is oxidized to gold in ashing processes The situation for belonging to oxide occurs, and so as to preferably avoid source electrode or drain electrode bigger than normal with the overlap resistance of anode electrode, causes Occur that fever, color displays are uneven when in use containing the screen of array substrate that the above method makes and power consumption height etc. is bad asks Topic.

Description of the drawings

Fig. 1 is the production method flow diagram figure of the array substrate of an embodiment of the present invention;

Fig. 2 is the structure diagram of the array substrate of an embodiment of the present invention.

Specific embodiment

In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.Many details are elaborated in the following description in order to fully understand this hair It is bright.But the invention can be embodied in many other ways as described herein, those skilled in the art can be not Similar improvement is done in the case of violating intension of the present invention, therefore the present invention is not limited to the specific embodiments disclosed below.

It should be noted that when element is referred to as " being set to " another element, it can be directly on another element Or there may also be elements placed in the middle.When an element is considered as " connection " another element, it can be directly connected to To another element or it may be simultaneously present centering elements.Term as used herein " vertical ", " horizontal ", " left side ", For illustrative purposes only, it is unique embodiment to be not offered as " right side " and similar statement.

Unless otherwise defined, all of technologies and scientific terms used here by the article is with belonging to technical field of the invention The normally understood meaning of technical staff is identical.Term used in the description of the invention herein is intended merely to description tool The purpose of the embodiment of body, it is not intended that in the limitation present invention.Term as used herein " and/or " including one or more The arbitrary and all combination of relevant Listed Items.

For example, a kind of production method of array substrate, including:Passivation layer is formed in source electrode and drain electrode;In the passivation The first via corresponding with the source electrode and the drain electrode is formed on layer;Planarization layer is formed on the passivation layer;To described Planarization layer carries out development exposure-processed, and second is formed on the planarization layer and crosses sectional hole patterns;Using O2To the planarization Layer carries out ashing processing;Secondary ashing processing is carried out to the planarization layer using reducing agent, is formed on the planarization layer Second via, second via are aligned with first via.

The production method for describing array substrate according to embodiments of the present invention below in conjunction with the accompanying drawings.

As shown in Figure 1, the production method of the array substrate of an embodiment includes the following steps:

S110:The thin film transistor (TFT) for including source electrode and drain electrode is formed on substrate.

In one embodiment, the substrate is glass substrate, and the substrate of glass material can cause light directly to transmit Loss may be not present, the buffer layer set on the substrate is convenient for the formation of other follow-up levels, avoids other layers Grade is formed directly on the substrate.

S120:Passivation layer is formed in source electrode and drain electrode.

In one embodiment, the passivation layer is located on the source electrode and the drain electrode, and the passivation layer is used to protect institute Source electrode and the drain electrode, i.e. protective film transistor are stated, thin film transistor (TFT) is avoided and is contaminated in subsequent technique.

S130:The first via corresponding with the source electrode and the drain electrode is formed on the passivation layer.

By developing, exposure handles the passivation layer, and the first via is formed on the passivation layer, is had The passivation layer of first via, first via is for exposing source electrode or drain electrode, in other words, the position of first via The position of position or drain electrode corresponding to source electrode.

S140:Planarization layer is formed on the passivation layer.

In one embodiment, in passivation layer backwards to one layer of planarization layer of coated on one side of thin film transistor (TFT), planarization layer is used In bumps of the reduction array substrate in the side far from thin film transistor (TFT) so that array substrate is in the side far from thin film transistor (TFT) Become flat, conducive to anode electrode is set in array substrate in subsequent step.For another example, the method for coating include slot coated, Any one in spin coating and silk-screen, is not limited herein.

S150:Development exposure-processed is carried out to the planarization layer, second is formed on the planarization layer and crosses sectional hole patterns.

In one embodiment, development exposure-processed is carried out to planarization layer using mask plate so that planarization layer corresponds to The position denaturation of first via, is got rid of the planarization layer of denaturation portion by developing, and obtains crossing sectional hole patterns containing second Planarization layer.For example, the second mistake sectional hole patterns include the shape of the second via, and the position of the second mistake sectional hole patterns and the first mistake The aligned in position in hole, in other words, second cross sectional hole patterns in via shape and position correspond to the first via shape with And position.

S160:Ashing processing is carried out to the planarization layer using oxygen, the second via is formed on the planarization layer, Second via is aligned with first via.

Ashing processing carries out planarization layer using oxygen, i.e., the planarization layer containing the second via is ashed Processing removes remaining planarization layer material after exposed and developed technique of developing, obtains the planarization layer containing the second via, the Two vias are aligned and connect with the first via so that and source electrode or drain electrode can be placed on outside by the first via and the second via, So that the anode electrode formed in subsequent step can pass through the second via and the first via and source electrode or drain contact.

S170:Secondary ashing processing is carried out to the planarization layer using reducing agent.

In one embodiment, the source electrode and the drain electrode include titanium layer stacked on top of each other, aluminium layer and molybdenum layer, above-mentioned Primary ashing processing aoxidizes the molybdenum layer of the source/drain, increases between source/drain and anode in order to avoid the molybdenum oxide of generation Contact resistance, secondary ashing handle during, the reducing agent include hydrogen, hydrogen is to organic insulation material and source electrode Or the metal molybdenum layer of drain surface has selectivity well, it is easier to occur with source electrode or the metal molybdenum layer of drain surface anti- Should, the metal molybdenum layer aoxidized in ashing processes is restored, i.e., molybdenum oxide is reduced into good conductive and heat conduction The metal molybdenum of performance;In the present embodiment, according to the adaptable reducing agent of the reproducibility power of reducing agent selection, for example, The reducing agent includes methane;For another example, the reducing agent includes carbon monoxide.

In another embodiment, the source electrode and the drain electrode include titanium layer stacked on top of each other, aluminium layer and layers of chrome, on It states primary ashing processing to aoxidize the layers of chrome of the source/drain, the reducing agent in secondary ashing processes includes hydrogen, methane And one kind in carbon monoxide, the metallic chromium layer aoxidized in ashing processes is restored, i.e., is reduced into chromium oxide Crome metal with good conductive and heat conductivility.

For the ease of molybdenum oxide is reduced to metal molybdenum, in the present embodiment, the reducing agent is hydrogen, hydrogen in room temperature For gaseous state under state, reproducibility just can will be demonstrated out at a certain temperature, for example, using hydrogen to copper oxide into line replacement During reaction, need reaction temperature being heated to 120 DEG C, for another example, using hydrogen to iron oxide into line replacement react when, react ring Border is hot environment, and reaction temperature is at 450 DEG C~500 DEG C, since metal molybdenum has stronger reproducibility in itself, in order to aoxidize Molybdenum is reduced to metal simple-substance molybdenum, and will certain change occur for the form of hydrogen, for example, hydrogen is plasmoid, temperature 90 ℃。

In one embodiment, the secondary ashing that planarization layer carries out is handled so that planarization layer and source drain contact portion The metal oxide divided is reduced to metal, and a podzolic process and secondary podzolic process carry out in same ash chamber, I.e. described primary ashing and the secondary ashing carry out in ash chamber successively, wherein, the temperature of ash chamber is 90 DEG C, thin The substrate temperature of film transistor is 30 DEG C, and during secondary ashing is handled, the reducing agent used is under plasmoid Hydrogen, the radio-frequency power for generating the hydrogen under plasmoid are 1000W~4000W, and substrate bias is 0W~200W, acquisition Hydrogen flowing quantity is 200sccm, and pressure is 1Pa~1.33Pa, and the time of secondary ashing is 30s~60s;In order to obtain the present embodiment Required plasma hydrogen, radio-frequency power be 1500W~3500W, substrate bias be 50W~150W, the hydrogen stream of acquisition It measures as 240sccm, pressure is 1.5Pa~1.33Pa, and the time of secondary ashing is 30s~50s.

In one embodiment, the material of planarization layer is organic insulation.For example, the material of planarization layer is heat resistance Organic insulation.For another example, the material of planarization layer is acrylic resin.For another example, the material of planarization layer is sub- for polyamides Amine.For another example, the material of planarization layer is benzocyclobutane vinyl resin.For another example, the material of planarization layer is polyamide.Again Such as, the material of planarization layer is epoxy resin.Further, it in order to improve the insulation heat resistance of planarization layer, can also carry The flatness on high planarization layer surface, for example, planarization layer is polyimide layer and acrylic resin stacked on top of each other Laminated construction, for another example, planarization layer are the lamination knot of benzocyclobutane vinyl resin layer and acrylic resin stacked on top of each other Structure, for another example, planarization layer are the laminated construction of polyamide resin layer and acrylic resin stacked on top of each other, for another example, flat Change the laminated construction that layer is epoxy resin layer and acrylic resin stacked on top of each other, according to different actual production conditions and The process requirements of different model array substrate, planarization layer can be polyimide layer, acrylic resin, benzocyclobutene The laminated construction that two or more arbitrary film layers of resinoid layer, polyamide resin layer and epoxy resin layer are formed.

In one embodiment, for example, the thickness of planarization layer is 1.8 μm~3.2 μm.For another example, the thickness of planarization layer is 1.9 μm~2.5 μm.For another example, the thickness of planarization layer is 2.0 μm~3.0 μm.For another example, the thickness of planarization layer is 1.8 μm, 2 μm Or 3 μm.For another example, the thickness of planarization layer is 3.2 μm.It should be noted that the thickness of planarization layer is too low, such as less than 1.8 μ During m, it is unfavorable for smoothing concave-convex situation of the array substrate in the side far from thin film transistor (TFT), the thickness of planarization layer is excessively high, example When being such as higher than 3.2 μm, it is unfavorable for the anode electrode formed in subsequent step and is connected with source electrode or drain electrode, can also increase array substrate Cost of manufacture, when planarization layer thickness for 1.8 μm~3.2 μm, especially 1.9 μm~2.5 μm when, not only improve smooth battle array Row substrate and is conducive to the anode electrode and source electrode formed in subsequent step in the concave-convex degree of the side far from thin film transistor (TFT) Or drain electrode connects, and will not also increase the cost of manufacture of array substrate.

In one embodiment, for example, carrying out development exposure-processed to planarization layer, is formed on the planarization layer Two cross after sectional hole patterns, are carrying out ashing processing to the planarization layer using oxygen, second is formed on the planarization layer Via before second via is aligned with first via, further includes following steps:

In 250 DEG C~350 DEG C temperature ranges, quiescence in high temperature is carried out to the planarization layer containing the second via, is made It obtains planarization layer and further hardens solid.

In the present embodiment, patterned process is carried out to passivation layer using development exposure, obtains and cross sectional hole patterns containing first Passivation layer, then, to containing first cross sectional hole patterns passivation layer carry out dry etching, obtain the passivation layer containing the first via.Again Such as, the passivation layer that sectional hole patterns are crossed containing first is done using RIE (Reactive Ion Etching, reactive ion etching) It carves.For another example, using ICP (Inductively Couple Plasma Etch, inductively coupled plasma etching) to containing One passivation layer for crossing sectional hole patterns carries out dry etching.For another example, using PE (Plasma Etch, plasma etching) to containing the first mistake The passivation layer of sectional hole patterns carries out dry etching.For another example, the technological parameter of dry etching is as follows:The gas used is being capable of Etch Passivation material Gas and O2, the throughput of Etch Passivation material is 100sccm~500sccm, O2Throughput for 100sccm~ 500sccm, radio-frequency power are 2000W~6000W, and etch period is 30s~120s, and dry carving technology under this state is conducive to It obtains high-visible first and crosses sectional hole patterns, wherein, for example, etch period is less than 30s, etches first come and cross sectional hole patterns Obscurity boundary can not be unfavorable for being subsequently formed the first via, for another example, during etching as the imitation pattern for forming the first via Between be more than 120s, be easy to cause passivation layer etching the first via pattern area it is excessive.Furthermore it is capable of Etch Passivation material Gas further includes CF4、SF6And CF4And SF6Mixed gas.

In one embodiment, using LPCVD (Low Pressure Chemical Vapor Deposition, low-pressure Chemical vapour deposition technique) deposit passivation layer on the thin film transistor (TFT) including source electrode and drain electrode, it should be noted that compared to CVD (Chemical Vapor Deposition, chemical vapour deposition technique), LPCVD can be realized since mass transfer rate is very fast The purpose of large area fast deposition passivation layer.For another example, using LCVD (Laser-induced Chemical Vapor Deposition, laser induced chemical vapor depostion method) deposit passivation layer on the thin film transistor (TFT) including source electrode and drain electrode, it needs Bright, compared to CVD, in LCVD, laser participates in chemical vapor deposition so that purity, intensity and the toughness of passivating film obtain Good raising is arrived.For another example, using PECVD (Plasma Enhanced Chemical Vapor Deposition, wait from Daughter enhances chemical vapor deposition) deposit passivation layer on the thin film transistor (TFT) including source electrode and drain electrode, it should be noted that phase Compared with CVD, the passivating film obtained using PECVD, thicknesses of layers is more uniform, and technique is reproducible.

In the production method of above-mentioned array substrate, the planarization layer that sectional hole patterns are crossed containing second is ashed using oxygen Processing removes remaining planarization layer material after exposed and developed technique of developing, later using reducing agent to the planarization layer Secondary ashing processing is carried out, the metal oxide that the metal part of source electrode or drain surface is aoxidized in ashing processes Metal is reduced to, so as to preferably avoid source electrode or drain electrode bigger than normal with the overlap resistance of anode electrode, and is caused containing upper There are the bad problems such as fever, color displays unevenness and power consumption height when in use in the screen for stating the array substrate of method making.

The invention also includes a kind of array substrate, array substrate is made to using the production method of above-mentioned any one embodiment It arrives.

The invention also includes a kind of display device 10, including the array substrate 100 in any of the above-described embodiment and organic Electroluminescent device 200, array substrate 100 include thin film transistor (TFT) 110, passivation layer 120, planarization layer 130, passivation layer 120 Be covered on thin film transistor (TFT) 110, planarization layer 130 is covered on passivation layer 120, thin film transistor (TFT) 110 include substrate 111, Polysilicon semiconductor layer 112, source/drain 113 and grid 114, source/drain 112 are in contact with polysilicon semiconductor layer 112, The first via 121 is provided on passivation layer 120, the second via 131, the first via 121 and second are provided on planarization layer 130 Via 131 is aligned, and the first via 121 and the second via 131 are used to expose source/drain 113, that is, source/drain 112 and first Via 121 is aligned with the second via 131, and anode electrode wears the second via 131 and the first via 121, and and source/drain successively 113 contacts, that is, connect with source/drain 113.The organic electroluminescence device 200 includes anode 210, cathode 220 and hair Photosphere 230, the luminescent layer 230 is between the anode 210 and the cathode 220, the organic electroluminescence device 200 Anode 210 200 shape of organic electroluminescence device is connect with the source/drain 113 of the low-temperature polysilicon film transistor 110 Into on low-temperature polysilicon film transistor 110, for example, the anode 210 is formed in protection film layer, the protection film layer is opened Equipped with contact hole, anode 210 is connect by the contact hole with source/drain 113.For example, the display device 10 further includes luminous zone Domain determines film layer, which determines that film layer is set between anode 210 and cathode 220, and the light-emitting zone determines film layer The outside of the luminescent layer 230 is set to, i.e. light-emitting zone determines that film layer coats the luminescent layer 230, and the light-emitting zone is used for Light transmission, the light-emitting zone are used to be aligned with the luminescent layer 230 of organic electroluminescence device 200 so that the light energy of luminescent layer 230 Enough go out through each film layer in the light-emitting zone.For the ease of forming pixel, pixel definition is set on the anode 210 Layer 240, the material of the pixel defining layer 240 is PI (polyimides) material, due to after the pixel defining layer 240 is formed It needs to carry out baking operation, and polyimide material has the spy of excellent thermal stability, chemical resistance and mechanical performance Point also there is bending strength can reach 345MPa, and composite bending modulus reaches 20GPa, Thermocurable polyimide creep very little, have compared with High tensile strength, the use temperature range covering of polyimides is wider, from subzero more than 100 degrees Celsius to 100 degrees Celsius, In order to avoid the oxidation of the anode 210, Spacer (barrier) layer 250, institute are formed on the pixel defining layer 240 is formed It is identical with the material of the pixel defining layer 240 to state Spacer layers 250, the Spacer layers 250 is set to play second protection Effect so that the situation that the anode 210 and thin film transistor base plate are extruded deformation in vapor deposition is inhibited.

Embodiment described above only expresses the several embodiments of the present invention, and description is more specific and detailed, but simultaneously Cannot the limitation to the scope of the claims of the present invention therefore be interpreted as.It should be pointed out that for those of ordinary skill in the art For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the guarantor of the present invention Protect range.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.

Claims (10)

1. a kind of production method of array substrate, which is characterized in that include the following steps:
The thin film transistor (TFT) for including source electrode and drain electrode is formed on substrate;
Passivation layer is formed in source electrode and drain electrode;
The first via corresponding with the source electrode and the drain electrode is formed on the passivation layer;
Planarization layer is formed on the passivation layer;
Development exposure-processed is carried out to the planarization layer, second is formed on the planarization layer and crosses sectional hole patterns;
Ashing processing is carried out to the planarization layer using oxygen, forms the second via on the planarization layer, described second Via is aligned with first via;
Secondary ashing processing is carried out to the planarization layer using reducing agent.
2. according to the method described in claim 1, it is characterized in that, the reducing agent includes hydrogen.
3. according to the method described in claim 2, it is characterized in that, the temperature of the hydrogen is 90 DEG C.
4. the production method of array substrate according to claim 1, which is characterized in that the material of the planarization layer is has Machine insulating materials.
5. the production method of array substrate according to claim 1, which is characterized in that the thickness of the planarization layer is 1.8 μm~3.2 μm.
6. the production method of array substrate according to claim 1, which is characterized in that described to be carried out to the planarization layer The exposure imaging that develops is handled, and second is formed on the planarization layer and is crossed after sectional hole patterns, further includes following steps:
In 250 DEG C~350 DEG C temperature ranges, quiescence in high temperature is carried out to the planarization layer.
7. the production method of array substrate according to claim 1, which is characterized in that the source electrode and the drain electrode are wrapped Include titanium layer stacked on top of each other, aluminium layer and molybdenum layer.
8. the production method of array substrate according to claim 1, which is characterized in that the source electrode and the drain electrode are wrapped Include titanium layer stacked on top of each other, aluminium layer and layers of chrome.
9. a kind of array substrate, which is characterized in that using the making side of the array substrate as described in any one of claim 1 to 8 Method makes to obtain.
10. a kind of display device, which is characterized in that including array substrate described in organic electroluminescence device and claim 9, The organic electroluminescence device includes anode, cathode and luminescent layer, and the luminescent layer is located at the anode and the cathode Between, the anode of the organic electroluminescence device is connect with the source/drain of the array substrate.
CN201711462028.7A 2017-12-28 2017-12-28 The production method and array substrate and display device of a kind of array substrate CN108183108A (en)

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CN104517995A (en) * 2013-10-08 2015-04-15 乐金显示有限公司 Organic light-emitting display device and method for manufacturing the same
CN106847742A (en) * 2017-01-22 2017-06-13 信利(惠州)智能显示有限公司 The preparation method and array base palte of array base palte
CN107464776A (en) * 2017-08-30 2017-12-12 京东方科技集团股份有限公司 A kind of display panel, its preparation method and display device

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