CN103107133B - Array substrate, manufacturing method thereof and displaying device - Google Patents

Array substrate, manufacturing method thereof and displaying device Download PDF

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Publication number
CN103107133B
CN103107133B CN201310002104.1A CN201310002104A CN103107133B CN 103107133 B CN103107133 B CN 103107133B CN 201310002104 A CN201310002104 A CN 201310002104A CN 103107133 B CN103107133 B CN 103107133B
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China
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photoresist
pattern
layer
array base
substrate
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CN201310002104.1A
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Chinese (zh)
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CN103107133A (en
Inventor
陈华斌
王琳琳
高英强
袁剑峰
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to CN201310002104.1A priority Critical patent/CN103107133B/en
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Abstract

The invention discloses an array substrate, a manufacturing method of the array substrate and a displaying device and relates to the technical method of manufacturing the array substrate through four times of Masks. The manufacturing method of the array substrate comprises manufacturing processes of a public electrode layer, a gate metal layer, a semiconductor layer, a source leakage electrode layer, a passivation layer and a pixel electrode layer, wherein the passivation layer and the pixel electrode layer are manufactured through once image composition technology. The manufacturing method of the array substrate has the advantages of being capable of saving one time of use of the Masks and reducing production cost, and suitable for manufacturing the array substrate in an advanced super dimension switch (ADS) mode.

Description

Array base palte and manufacture method thereof and display unit

Technical field

The present invention relates to Display Technique field, particularly relate to array base palte and manufacture method thereof and display unit.

Background technology

At present, display product is more and more universal in people's daily life, and relevant Display Technique also more and more receives the concern of people.Display field has wide market prospects, and attracted a large amount of enterprises, research and development that institutes is engaged in Display Technique.

TFT-LCD(Thin Film Transistor-Liquid Crystal Display, Thin Film Transistor-LCD) complex process, cost higher.Wherein, Mask(mask plate) technical process extremely tests the precision of equipment and process, and it is a lot of that many Mask technique can make production cost increase, therefore the quantity reducing Mask on the basis not affecting properties of product is very important.Since TFT-LCD invention, people are devoted to the work reducing Mask number of processes always.

As shown in Figure 1, current ADS(Advanced Super Dimension Switch, senior super dimension field switch technology) array substrate manufacturing method of pattern needs 5 Mask usually, comprise: the ground floor transparency conducting layer mask plate in step 101 is (because transparency conducting layer adopts tin indium oxide ITO usually, therefore ground floor transparency conducting layer mask plate also can be described as 1st ITO Mask), gate mask version (Gate Mask) in step 102, source-drain electrode mask plate (SDT Mask) in step 103, via hole mask plate (Via Hole Mask) in step 104, second layer transparency conducting layer mask plate (2nd ITO Mask) in step 105.The Mask technique number of times needed due to the manufacture method of existing ADS pattern array substrate is many, make the cost of the liquid crystal display based on ADS technology higher, and production efficiency cannot get a promotion.

Summary of the invention

Embodiments of the invention provide a kind of array base palte and manufacture method thereof, and use the display unit of this array base palte, in order to reduce the production cost of array base palte and to enhance productivity.

For achieving the above object, technical scheme provided by the invention is as follows:

A kind of manufacturing method of array base plate, comprises the manufacturing process of common electrode layer, grid metal level, semiconductor layer, source-drain electrode layer, passivation layer and pixel electrode layer; Wherein,

Described passivation layer and described pixel electrode are formed by a patterning processes.

Preferably, described manufacture method comprises:

Step 1, on substrate, form the pattern of public electrode by patterning processes;

Step 2, on the substrate through described step 1, form the pattern of grid by patterning processes;

Step 3, at the pattern being formed semiconductor layer, source electrode and drain electrode on the substrate described in described step 2 by patterning processes;

Step 4, on the substrate described in described step 3, patterning processes is being adopted to form the pattern of pixel electrode and passivation layer.

Preferably, described step 4 specifically comprises:

The substrate that described step 3 makes forms passivation layer;

The first photoresist is applied again on described passivation layer, and utilize duotone mask plate to expose the first photoresist, wherein, corresponding passivation layer via hole place is the first photoresist complete exposure area, corresponding strip pixel electrode place is the first photoresist half exposure area, is the complete reserve area of the first photoresist to the region beyond described first photoresist complete exposure area and described first photoresist half exposure area;

Substrate after exposure is developed, obtains the pattern of the first photoresist;

Remove region completely to described photoresist to etch, form passivation layer via hole, and expose part source-drain electrode layer;

Utilize cineration technics to carry out ashing to the first photoresist, remove the photoresist of described half exposure area, the complete reserve area of described photoresist is slit-shaped pattern;

Form the second transparency conducting layer;

Described second transparency conducting layer applies the second photoresist, the mobility of photoresist is utilized to make described second photoresist planarization, utilize the thickness of described first photoresist, the thickness of the second photoresist above described first photoresist is made to be less than other regions, except the region except reservation first photoresist;

Ashing is carried out to the second photoresist, removes described reservation first photoresist with the second photoresist of exterior domain, and expose described second transparency conducting layer; ;

The described second layer transparency conducting layer exposed is etched, obtains the pixel electrode with slit;

The first residual photoresist and the second photoresist are peeled off, forms the pattern of described passivation layer and pixel electrode.

Preferably, described step 4 specifically comprises:

The substrate that described step 3 makes forms passivation layer;

The first photoresist is applied again on described passivation layer, and utilize duotone mask plate to expose the first photoresist, wherein, corresponding passivation layer via hole place is the first photoresist complete exposure area, corresponding strip pixel electrode place is the first photoresist half exposure area, is the complete reserve area of the first photoresist to the region beyond described first photoresist complete exposure area and described first photoresist half exposure area;

Substrate after exposure is developed, obtains the pattern of the first photoresist;

Remove region completely to described photoresist to etch, form passivation layer via hole, and expose part source-drain electrode layer;

Utilize cineration technics to carry out ashing to the first photoresist, remove the photoresist of described half exposure area, the complete reserve area of described photoresist is slit-shaped pattern;

Form the second transparency conducting layer;

Removed the photoresist of the complete reserve area of photoresist by liftoff stripping technology, form the pixel electrode with slit.

Preferably, described step 1 is specially: on substrate, form the first transparency conducting layer, utilizes the first transparency conducting layer mask plate to carry out patterning processes to form the pattern of public electrode.

Preferably, the pattern of described public electrode is plate electrode or slit-shaped electrode.

Preferably, described step 2 is specially: on substrate, form grid metallic film, adopts gate mask version to carry out the pattern of patterning processes formation grid.8, manufacturing method of array base plate according to claim 2, it is characterized in that, described step 3 is specially: on substrate, form semiconductor layer and source and drain metal level, utilizes source-drain electrode mask plate to carry out patterning processes to form the pattern of source electrode, drain electrode and semiconductor layer.

Preferably, also ohmic contact layer is provided with between semiconductor layer and source-drain electrode layer.

To achieve these goals, present invention also offers a kind of array base palte, this array base palte adopts the manufacture method manufacture of above-mentioned array base palte.

To achieve these goals, present invention also offers a kind of display unit, the structure of this display unit comprises above-mentioned array base palte.

The present invention passes through described two kinds of methods above, can obtain via hole and pixel electrode structure, decrease a step Mask technical process, greatly reduce cost by means of only a mask plate technique.The present invention is applicable to the manufacture of ADS pattern array substrate.

Accompanying drawing explanation

In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.

Fig. 1 is the array base palte fabrication processing schematic diagram of prior art;

Fig. 2 is array base palte fabrication processing schematic diagram of the present invention;

The floor map of the array base palte that Fig. 3 provides for the embodiment of the present invention;

Fig. 4 is the sectional view at A-B place in the Fig. 3 before embodiment 1 array substrate carries out Halftone technique;

Fig. 5 is the sectional view at A-B place in the Fig. 3 after embodiment 1 array substrate carries out Halftone technique;

Fig. 6 is the sectional view obtaining A-B place in Fig. 3 of via hole after embodiment 1 Etch Passivation;

Fig. 7 is the sectional view of embodiment 1 to A-B place in the Fig. 3 after the first photoresist ashing;

Fig. 8 is the sectional view at A-B place in the Fig. 3 after embodiment 1 forms the second transparency conducting layer;

Fig. 9 is the sectional view at A-B place in the Fig. 3 after embodiment 1 applies the second photoresist;

Figure 10 is the sectional view at A-B place in the Fig. 3 after embodiment 1 ashing second photoresist;

Figure 11 is the sectional view that embodiment 1 etches A-B place in 3 after the second transparency conducting layer;

Figure 12 is the sectional view at A-B place in the Fig. 3 after embodiment 1 peels off residual photoresist;

Figure 13 is the sectional view at A-B place in the Fig. 3 before embodiment 2 array substrate carries out Halftone technique;

Figure 14 is the sectional view at A-B place in the Fig. 3 after embodiment 2 array substrate carries out Halftone technique;

Figure 15 is the sectional view obtaining A-B place in Fig. 3 of via hole after embodiment 2 Etch Passivation;

Figure 16 is the sectional view at A-B place in the Fig. 3 after embodiment 2 pairs of photoresist ashings;

Figure 17 is the sectional view at A-B place in the Fig. 3 after embodiment 2 deposits the second transparency conducting layer;

Figure 18 is the sectional view at A-B place in the Fig. 3 after embodiment 2 peels off residual photoresist.

Reference numeral: 301,401-substrate; 302,402-grid; 303,403-public electrode; 304,404-gate insulation layer; 305,405-semiconductor layer; 306,406-source electrode; 307,407-raceway groove; 308,408-drain electrode; 309,409-passivation layer; 310,3101-first photoresist; 410,4101-photoresist; 311,411-exposed plate; 312,412-via hole; 313,413,3131,4131-pixel electrode; 314,3141-second photoresist.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.

Be illustrated in figure 2 four patterning processes of the present invention; The manufacture method of array base palte provided by the present invention specifically comprises:

Step 201, on substrate, form the first transparency conducting layer, utilize the first transparency conducting layer mask plate to obtain the pattern of public electrode;

Step 202, adopt sputtering or the technology of evaporation, substrate is formed grid metal level, adopts gate mask version to obtain the pattern of grid;

Step 203, adopt sputtering or the technology of evaporation, substrate is formed semiconductor layer and source and drain metal level, utilize source-drain electrode mask plate to obtain the pattern of source electrode, drain electrode and active layer;

Step 204, coating passivation layer, obtain the pattern of passivation layer and pixel electrode by mask plate technique.

The pattern of described public electrode is plate electrode or slit-shaped electrode.

Also be provided with ohmic contact layer between semiconductor layer and source-drain electrode layer, reduce the contact resistance between semiconductor and source-drain electrode.

Below in conjunction with accompanying drawing, the technical scheme that the embodiment of the present invention provides is described in detail.

Embodiment 1

Shown in composition graphs 4 to Figure 12, the manufacturing method of array base plate provided in the present embodiment, comprises the following steps:

Step F 1, on substrate 301, deposit the first transparent conductive film, formed the pattern of public electrode 303 by patterning processes;

In step F 1, aforesaid substrate 301 can be the underlay substrate based on inorganic material such as glass substrate, quartz base plate, also can be the underlay substrate adopting organic material;

The material of above-mentioned ground floor transparent conductive film can be tin indium oxide (ITO), indium zinc oxide (IZO, Indium Zinc Oxide) etc.

Step F 2, on the substrate forming above-mentioned pattern, form grid metallic film, form the pattern of gate electrode 302 by patterning processes;

Step F 3, on the substrate forming above-mentioned pattern, form gate insulation layer film, semiconductor layer film and source and drain metallic film successively, formed by patterning processes and comprise the pattern of semiconductor layer 305, source electrode 306 and drain electrode 308;

Step F 41, the substrate forming above-mentioned pattern forms passivation layer 309 successively, first photoresist 310, as shown in Figure 4, exposed by duotone mask plate 311, described duotone mask plate comprises: gray mask plate and pellicle mask plate, full exposure and half exposure technique is adopted to transfer pattern on described first photoresist 310, be specially: corresponding passivation layer 309 via hole 312 place is the first photoresist 310 complete exposure area, corresponding strip pixel electrode 313 place is the first photoresist 310 half exposure area, be the first photoresist 310 completely reserve area to the region beyond described first photoresist 310 complete exposure area and described first photoresist 310 half exposure area, see Fig. 5,

Step F 42, on the substrate 301 forming above-mentioned pattern, remove the passivation layer 309 at via hole 312 place by patterning processes, form the pattern of via hole 312, see Fig. 6, described via hole 312 to be formed on described passivation layer 309 and described drain electrode 308 is come out;

Step F 43, formed above-mentioned pattern substrate 301 on utilize incinerator technology evenly to be thinned by the first photoresist 310, the first photoresist 310 of exposure area does not retain, the first photoresist 310 retained is in slit-shaped pattern, the region etch of the first photoresist 310 need not be retained to passivation layer 309, the pattern finally obtained, is shown in Fig. 7;

Step F 44, formed above-mentioned pattern substrate 301 on form the second transparent conductive film, specifically can adopt sputtering or evaporation method formed, the pattern form due to the first photoresist 310 makes pixel electrode 313 present the pattern of slit-shaped structure, sees Fig. 8;

Step F 45, the substrate 301 forming above-mentioned pattern carries out layer photoetching glue 314 again and applies, obtain pattern as shown in Figure 9; Then cineration technics is carried out to the second photoresist 314, the second transparency conducting layer 313 above the first photoresist 310,3101 place is come out, obtains pattern as shown in Figure 10;

Step F 46, the second transparency conducting layer 313 come out to be etched, obtain pattern as shown in figure 11;

Step F 47, finally all the first residual photoresists 310 and the second photoresist 314 to be peeled off, finally obtain pattern as shown in figure 12; Wherein, strip pattern is formed in pixel electrode area.

The floor map of array base palte made as seen from Figure 3, wherein A-B only represents and does not relate to concrete array base-plate structure in the position that cross section intercepts.

Wherein, the formation relating to film in the present embodiment comprises: the methods such as deposition, coating, sputtering, printing; Involved patterning processes comprises: the operations such as coating photoresist, sputtering, evaporation, exposure imaging, etching, ashing and removal photoresist.

Embodiment 2

In conjunction with shown in Figure 13 to Figure 18, the manufacturing method of array base plate provided in the present embodiment, comprises the following steps:

Step S1, on substrate 401, form ground floor transparent conductive film, adopt the first transparency conducting layer mask plate to form the pattern of public electrode 403 by patterning processes;

In step sl, aforesaid substrate 301 can be the underlay substrate based on inorganic material such as glass substrate, quartz base plate, also can be the underlay substrate adopting organic material;

The material of above-mentioned first transparent conductive film can be tin indium oxide (ITO), indium zinc oxide (IZO, Indium Zinc Oxide) etc.

Step S2, on the substrate 401 forming above-mentioned pattern, form grid metallic film, adopt gate mask version to form the pattern of gate electrode 402 by patterning processes;

Step S3, on the substrate 401 forming above-mentioned pattern, form gate insulation layer film, semiconductor layer film and source and drain metallic film successively, adopt source-drain electrode mask plate to be formed the pattern comprising semiconductor layer 405, source electrode 406 and drain electrode 408 by patterning processes;

Step S41, the substrate 401 forming above-mentioned pattern forms passivation layer 409 successively, photoresist layer 410, as shown in figure 13, exposed by duotone mask plate 411, described duotone mask plate comprises: gray mask plate and pellicle mask plate, full exposure and half exposure technique is adopted to transfer pattern on described photoresist layer 410, be specially: corresponding passivation layer 309 via hole 312 place is the first photoresist 310 complete exposure area, corresponding strip pixel electrode 313 place is the first photoresist 310 half exposure area, be the first photoresist 310 completely reserve area to the region beyond described first photoresist 310 complete exposure area and described first photoresist 310 half exposure area, see Figure 14,

Step S42, on the substrate 401 forming above-mentioned pattern, remove the passivation layer 409 at via hole 412 place by patterning processes, form the pattern of via hole 412, see Figure 15, described via hole 412 to be formed on described passivation layer 409 and described drain electrode 408 is come out;

Step S43, formed above-mentioned pattern substrate 401 on utilize incinerator technology evenly to be thinned by photoresist 410, the photoresist 410 of exposure area does not retain, the photoresist 410 retained is in strip pattern, the region etch of photoresist 410 need not be retained to passivation layer 409, the pattern finally obtained, is shown in Figure 16;

Step S44, formed above-mentioned pattern substrate 401 on form second layer transparent conductive film, specifically can adopt sputtering or evaporation method formed, the pattern form due to photoresist 410 makes pixel electrode 413 present the pattern of slit-shaped, sees Figure 17;

Step S45, on the substrate 401 forming above-mentioned pattern, directly liftoff stripping is carried out to residual photoresist 410,4101, remove residual photoresist 410,4101 and the second transparent conductive film above it simultaneously, finally obtain pattern as shown in figure 18; Wherein, pixel electrode area forms slit-shaped structure.

The floor map of array base palte made as seen from Figure 3, wherein A-B only represents and does not relate to concrete array base-plate structure in the position that cross section intercepts.

Wherein, the formation of the film related in the present embodiment comprises: the methods such as deposition, coating, sputtering, printing; Involved patterning processes comprises: the operations such as coating photoresist, sputtering, evaporation, exposure imaging, etching, ashing and removal photoresist.

Embodiment 3

This embodiment describes a kind of array base palte, this array base palte utilizes the manufacture method manufacture of array base palte in embodiment 1 or 2.

Embodiment 4

This embodiment describes a kind of display unit, this display unit comprises the display unit of the array base palte manufactured in embodiment 3.

Described display unit can be: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.

Such as, for liquid crystal indicator, need first by described array base palte and color membrane substrates to box, the circuit and the frame that increase periphery again obtain showing module, again with backlight module and control circuit system assembles, finally add shell and base, obtain final complete liquid crystal indicator.

It will be understood by those skilled in the art that pixel electrode can be tabular or slit-shaped, public electrode is also like this, the order up and down of pixel electrode and public electrode can be put upside down, but must be slit-shaped at upper electrode, under electrode can be tabular, or slit-shaped.

The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.

Claims (8)

1. a manufacturing method of array base plate, is characterized in that, comprising:
Step 1, on substrate, form the pattern of public electrode by patterning processes;
Step 2, on the substrate through described step 1, form the pattern of grid by patterning processes;
Step 3, at the pattern being formed semiconductor layer, source electrode and drain electrode on the substrate described in described step 2 by patterning processes;
Step 4, the substrate that makes in described step 3 form passivation layer; The first photoresist is applied again on described passivation layer, and utilize duotone mask plate to expose the first photoresist, wherein, corresponding passivation layer via hole place is the first photoresist complete exposure area, corresponding strip pixel electrode place is the first photoresist half exposure area, and the region except described first photoresist complete exposure area and described first photoresist half exposure area is the complete reserve area of the first photoresist; Substrate after exposure is developed, obtains the pattern of the first photoresist; Remove region completely to described photoresist to etch, form passivation layer via hole, and expose part source-drain electrode layer; Utilize cineration technics to carry out ashing to the first photoresist, remove the photoresist of described half exposure area, the complete reserve area of described photoresist is slit-shaped pattern; Form the second transparency conducting layer; Described second transparency conducting layer applies the second photoresist, the mobility of photoresist is utilized to make described second photoresist planarization, utilize the thickness of described first photoresist, make the thickness of the second photoresist above described first photoresist be less than the thickness of the second photoresist except the first photoresist region; Ashing is carried out to the second photoresist, removes described reservation first photoresist with the second photoresist of exterior domain, and expose described second transparency conducting layer; The described second layer transparency conducting layer exposed is etched, obtains the pixel electrode with slit; The first residual photoresist and the second photoresist are peeled off, forms the pattern of described passivation layer and pixel electrode.
2. manufacturing method of array base plate according to claim 1, is characterized in that, described step 1 is specially: on substrate, form the first transparency conducting layer, utilizes the first transparency conducting layer mask plate to carry out patterning processes to form the pattern of public electrode.
3. manufacturing method of array base plate according to claim 2, is characterized in that, the pattern of described public electrode is plate electrode or slit-shaped electrode.
4. manufacturing method of array base plate according to claim 1, is characterized in that, described step 2 is specially: on substrate, form grid metallic film, adopts gate mask version to carry out the pattern of patterning processes formation grid.
5. manufacturing method of array base plate according to claim 1, it is characterized in that, described step 3 is specially: on substrate, form semiconductor layer and source and drain metal level, utilizes source-drain electrode mask plate to carry out patterning processes to form the pattern of source electrode, drain electrode and semiconductor layer.
6. manufacturing method of array base plate according to claim 1, is characterized in that, is also provided with ohmic contact layer between semiconductor layer and source-drain electrode layer.
7. an array base palte, is characterized in that, this array base palte is the array base palte adopting the arbitrary described manufacturing method of array base plate of claim 1-6 to manufacture.
8. a display unit, is characterized in that, this display unit comprises array base palte according to claim 7.
CN201310002104.1A 2013-01-04 2013-01-04 Array substrate, manufacturing method thereof and displaying device CN103107133B (en)

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CN103715138B (en) 2013-12-31 2017-01-25 京东方科技集团股份有限公司 Array substrate and manufacturing method and display device thereof
CN103779232B (en) 2014-01-28 2016-08-17 北京京东方光电科技有限公司 A kind of manufacture method of thin film transistor (TFT)
CN104409418B (en) * 2014-11-13 2018-02-13 京东方科技集团股份有限公司 A kind of thin-film transistor array base-plate and preparation method thereof, display device
CN105093823B (en) 2015-06-03 2019-09-20 京东方科技集团股份有限公司 A kind of manufacturing method of gap electrode, gap electrode and display panel
CN105374852B (en) * 2015-11-16 2019-10-11 Tcl集团股份有限公司 A kind of printed form active display and preparation method thereof of no pixel bank
CN105470282B (en) * 2015-11-20 2020-03-31 Tcl集团股份有限公司 TFT-OLED (thin film transistor-organic light emitting diode) without pixel bank and preparation method
CN105489611A (en) * 2015-11-26 2016-04-13 Tcl集团股份有限公司 Printed type light emitting display and manufacturing method therefor
CN108183108A (en) * 2017-12-28 2018-06-19 信利(惠州)智能显示有限公司 The production method and array substrate and display device of a kind of array substrate
CN109037151B (en) * 2018-07-25 2020-02-07 深圳市华星光电半导体显示技术有限公司 Preparation method of array substrate

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