CN103715135B - A kind of via hole and preparation method thereof, array base palte - Google Patents
A kind of via hole and preparation method thereof, array base palte Download PDFInfo
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- CN103715135B CN103715135B CN201310689054.9A CN201310689054A CN103715135B CN 103715135 B CN103715135 B CN 103715135B CN 201310689054 A CN201310689054 A CN 201310689054A CN 103715135 B CN103715135 B CN 103715135B
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Abstract
The embodiment of the present invention provides a kind of via hole and preparation method thereof, array base palte, relates to Display Technique field, can improve the problem of the bigger than normal and open circuit of contact resistance in via hole technology.This via hole is included on substrate and is formed with the first electrode and metal level successively; Metal level is electrically connected with the first electrode.Be formed with insulating barrier and the second electrode on the surface of metal level successively, the surface of insulating barrier is provided with via hole, the second electrode is electrically connected with metal level by this via hole.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of via hole and preparation method thereof, array base palte.
Background technology
TFT-LCD(ThinFilmTransistorLiquidCrystalDisplay, thin film transistor-liquid crystal display) as a kind of panel display apparatus, because it has the features such as little, low in energy consumption, the radiationless and cost of manufacture of volume is relatively low, and be applied to more and more in the middle of high-performance display field.
The manufacturing process of TFT-LCD display floater comprises: manufacturing array (Array) substrate and color film (ColorFilter) substrate, and then array base palte is carried out contraposition with color membrane substrates, becomes box (Cell).As shown in Figure 1, typical tft array substrate comprise transparency carrier 11 and be positioned at successively transparency carrier 11 on the surface grid 120, gate insulator 13, active layer 14, the drain electrode 121 being positioned at active layer 14 both sides and source class 122, the passivation layer 15 be positioned on active layer 14, drain electrode 121 and source class 122 surface, be positioned at the ITO16(Indiumtinoxide on passivation layer 15 surface, tin indium oxide).
In the manufacturing process of array base palte, the wires design on array base palte is a very important content.Wherein, need to realize being electrically connected to each other by via hole between the various level retes such as data wire, grid line and public electrode wire.Such as, the surface of passivation layer 15 is provided with via hole, to make drain electrode 121 conducting of ITO16 and thin-film transistor.And consider the factor of pixel aperture ratio, this via hole can be set to half via hole 20 as shown in Figure 1.A part of the ITO16 on this half via hole 20 surface is overlapped on the surface of drain electrode 121, and another part is overlapped on the surface of half via hole 20 bottom gate insulator layer 13, adopts a kind of like this half via hole to increase pixel aperture ratio.
But half via hole of the prior art exists following defect: on the one hand, because the contact area between the rete that half via hole place contacts with each other is less, its contact resistance is caused to increase.As shown in Figure 1, half via hole 20 place transparency electrode 16 reduces with the contact area of drain electrode 121, and therefore its contact resistance can corresponding rising, and so the electric conductivity of TFT can decline the charging interval of TFT is extended; On the other hand, the offset that the rete marginal existence at half via hole place is certain, as in Fig. 1, there is offset in half via hole 20 place drain electrode 121, when the angle of gradient at this offset place is comparatively large or because when chamfering appears in etching technics, can there is open circuit in the ITO16 being positioned at drain electrode 121 angle of gradient or chamfering place, drain electrode 121 cannot be connected with ITO16.Thus affect the performance of display device, reduce product quality.Certainly, also the problems referred to above can be there are in the via hole of other types.
Summary of the invention
Embodiments of the invention provide a kind of via hole and preparation method thereof, array base palte.The problem of the bigger than normal and open circuit of contact resistance in via hole technology can be improved.
For achieving the above object, embodiments of the invention adopt following technical scheme:
The one side of the embodiment of the present invention provides a kind of manufacture method of via hole, comprising:
Substrate is formed by patterning processes the pattern of the first electrode;
Metal level is formed at the substrate surface being formed with described first electrode pattern; Described metal level is electrically connected with the pattern of described first electrode;
Insulating barrier is formed at the substrate surface being formed with described metal level;
Via hole is formed by patterning processes on the surface of described insulating barrier;
Formed the pattern of the second electrode by patterning processes at the substrate surface being formed with described via hole;
Wherein, described second electrode is electrically connected with described metal level by described via hole.
The another aspect of the embodiment of the present invention provides a kind of via hole, comprising:
Substrate is formed the first electrode;
Metal level is formed on the surface of described first electrode; Described metal level is electrically connected with described first electrode;
Insulating barrier is formed on the surface of described metal level;
Via hole is formed on the surface of described insulating barrier;
The second electrode is formed on the surface of described via hole;
Wherein, described second electrode is electrically connected with described metal level by described via hole.
The another aspect of the embodiment of the present invention provides a kind of array base palte, comprises any one via hole as above.
The embodiment of the present invention provides a kind of via hole and preparation method thereof, array base palte.This via hole is included on substrate and is formed with the first electrode and metal level successively; Metal level is electrically connected with the first electrode.Be formed with insulating barrier and the second electrode on the surface of metal level successively, the surface of insulating barrier is provided with via hole, the second electrode is electrically connected with metal level by this via hole.So, the degree of depth of via hole can be reduced, and increase the contact area between the rete that is electrically connected to each other, thus improve the problem of the bigger than normal and open circuit of contact resistance in via hole technology.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The structural representation of a kind of array base palte that Fig. 1 provides for prior art;
The fabrication processing figure of a kind of via hole that Fig. 2 provides for the embodiment of the present invention;
The structural representation of a kind of via hole that Fig. 3 provides for the embodiment of the present invention;
The structural representation of the another kind of via hole that Fig. 4 provides for the embodiment of the present invention;
The structural representation of another via hole that Fig. 5 provides for the embodiment of the present invention;
The structural representation of a kind of array base palte that Fig. 6 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The embodiment of the present invention provides a kind of manufacture method of via hole, as shown in Figure 2, comprising:
S101, as shown in Figure 3, formed the pattern of the first electrode 21 on the substrate 10 by patterning processes.
S102, be formed with metal level 22 at the substrate surface being formed with the first electrode 21 pattern; Metal level 22 is electrically connected with the pattern of the first electrode 21.
S103, be formed metal level 22 substrate surface formed insulating barrier 23.
S104, on the surface of insulating barrier 23 by patterning processes formed via hole 24.
S105, formed the pattern of the second electrode 25 by patterning processes at the substrate surface being formed with via hole 24.
Wherein, the second electrode 25 is electrically connected with metal level 22 by via hole 24.
It should be noted that, the patterning processes in the embodiment of the present invention, can refer to comprise photoetching process, or, comprise photoetching process and etch step, other techniques for the formation of predetermined pattern such as printing, ink-jet can also be comprised simultaneously; Photoetching process, refers to that utilize photoresist, mask plate, the exposure machine etc. that comprise the technical processs such as film forming, exposure, development form the technique of figure.Can according to the structure choice formed in the present invention corresponding patterning processes.
The embodiment of the present invention provides a kind of via hole and preparation method thereof, array base palte.The manufacture method of this via hole is included in pattern substrate being formed successively the first electrode and metal level; Metal level is electrically connected with the pattern of the first electrode.Form the pattern of insulating barrier and the second electrode on the surface of metal layer pattern successively, form via hole on the surface of insulating layer pattern, the second electrode is electrically connected with metal level by this via hole.So, the degree of depth of via hole can be reduced, and increase the contact area between the rete that is electrically connected to each other, thus improve the problem of the bigger than normal and open circuit of contact resistance in via hole technology.
Further, as shown in Figure 4, can also be comprised by the method for patterning processes formation via hole 24 on the surface of insulating barrier 23:
On the surface of insulating barrier 23, the position of corresponding metal level 22 and the first electrode 21 forms via hole 24 by patterning processes.
Wherein, the second electrode 25 is electrically connected with the first electrode 21 and metal level 22 by via hole 24.
It should be noted that, the corresponding metal level 22 in surface of above-mentioned insulating barrier 23 and the position of the first electrode 21 specifically refer to exposed portion, bottom metal level 22 and first electrode 21 of the via hole 24 formed on the surface of insulating barrier 23 by patterning processes such as etching technics.So, in a subsequent step, the pattern being formed at second electrode 25 on insulating barrier 23 surface can cover this via hole 24, and is all electrically connected with metal level 22 and the first electrode 21 by via hole 24.
It should be noted that above-mentioned via hole 24 is half via hole, can realize not only can improving aperture opening ratio while the second electrode 25 is electrically connected with metal level 22 by this half via hole, and the contact area of metal level 22 and the first electrode 21 and the second electrode 25 can be increased, so can reduce the contact resistance between metal level 22 and electrode, thus promote the electric conductivity of array base palte.In addition, because although the metal level 22 at this half via hole place exists offset, when the angle of gradient at this offset place is comparatively large or because when chamfering appears in etching technics, can cause the second electrode 25 being positioned at metal level 22 angle of gradient or chamfering place that open circuit occurs, at this moment metal level 22 so can be connected with the second electrode 25 by the first electrode 21, thus avoids array base palte generation open circuit.
Or, as shown in Figure 5, can also be comprised by the method for patterning processes formation via hole 24 on the surface of insulating barrier 23:
On the surface of insulating barrier 23, the position of corresponding first electrode 21 forms via hole 24 by patterning processes.
Wherein, the second electrode 25 is electrically connected with the first electrode 21 by via hole 24.
It should be noted that, the position of corresponding first electrode 21 pattern in surface of insulating barrier 23 specifically refers to the pattern of exposed portion, bottom first electrode 21 of the via hole 24 formed on the surface of insulating barrier 23 by patterning processes such as etching technics.So, in a subsequent step, the pattern being formed at second electrode 25 on insulating barrier 23 surface can cover this via hole 24, and is electrically connected with the pattern of the first electrode 21 by via hole 24.So, not only can realize the electrical connection of the second electrode 25 and metal level 22, and can by increasing the contact resistance that metal level 22 and the contact area of the first electrode 21 and the contact area of the first electrode 21 and the second electrode 25 reduce to be electrically connected to each other between rete.Thus promote the electric conductivity of array base palte.In addition, owing to having the first electrode 21 between the second electrode 25 and substrate 10, the offset of via hole 24 is reduced, thus there is the probability of fracture in the second electrode 25 reducing Hole chamfering place, and then improve the quality of array base palte.
Preferably, the first electrode 21 and the second electrode 25 can be all transparent conductive material.Such as: tin indium oxide (IndiumTinOxide is called for short ITO).
Further, the first electrode 21 can comprise at least one rete.Because the first electrode 21 can be electrically connected with between metal level 22, therefore, the rete of the first electrode 21 near this side of metal level 22 has the function of conduction.So, under the prerequisite that guarantee first electrode 21 is electrically connected with metal level 22, those skilled in the art, in process of manufacture, can increase and decrease the quantity of rete in the first electrode 21 according to actual needs, thus can control the degree of depth of via hole 24.
The embodiment of the present invention provides a kind of via hole, as shown in Figure 3, comprising:
Be formed with the first electrode 21 on the substrate 10.
Metal level 22 is formed on the surface of the first electrode 21; This metal level 22 is electrically connected with the first electrode 21.
Insulating barrier 23 is formed on the surface of metal level 22.
Via hole 24 is formed on the surface of insulating barrier 23.
The second electrode 25 is formed on the surface of via hole 24.
Wherein, the second electrode 25 is electrically connected with metal level 22 by via hole 24.
The embodiment of the present invention provides a kind of via hole.This via hole is included on substrate and is formed with the first electrode and metal level successively; Metal level is electrically connected with the first electrode.Be formed with the pattern of insulating barrier and the second electrode on the surface of metal level successively, be formed with via hole on the surface of insulating barrier, the second electrode is electrically connected with metal level by this via hole.So, the degree of depth of via hole can be reduced, and increase the contact area between the rete that is electrically connected to each other, thus improve the problem of the bigger than normal and open circuit of contact resistance in via hole technology.
Further, as shown in Figure 4, the position of via hole 24 is corresponding with the position of metal level 22 and the first electrode 21.
Wherein, the second electrode 25 is electrically connected with the first electrode 21 and metal level 22 by via hole 24.
It should be noted that, corresponding exposed portion, bottom metal level 22 and first electrode 21 specifically referring to the via hole 24 formed on the surface of insulating barrier 23 by patterning processes such as etching technics in position of the position of via hole 24 and metal level 22 and the first electrode 21.So, in a subsequent step, the pattern being formed at second electrode 25 on insulating barrier 23 surface can cover this via hole 24, and is all electrically connected with metal level 22 and the first electrode 21 by via hole 24.
It should be noted that above-mentioned via hole 24 is half via hole, can realize not only can improving aperture opening ratio while the second electrode 25 is electrically connected with metal level 22 by this half via hole, and the contact area of metal level 22 and the first electrode 21 and the second electrode 25 can be increased, so can reduce the contact resistance between metal level 22 and electrode, thus promote the electric conductivity of array base palte.In addition, because although the metal level 22 at this half via hole place exists offset, when the angle of gradient at this offset place is comparatively large or because when chamfering appears in etching technics, can cause the second electrode 25 being positioned at metal level 22 angle of gradient or chamfering place that open circuit occurs, at this moment metal level 22 so can be connected with the second electrode 25 by the first electrode 21, thus avoids array base palte generation open circuit.
Or as shown in Figure 5, the position of via hole 24 is corresponding with the position of the first electrode 21.
Wherein, the second electrode 25 is electrically connected with the first electrode 21 by via hole 24.
It should be noted that, the position of via hole 24 pattern that specifically refer to bottom exposed portion first electrode 21 of the via hole 24 that by patterning processes such as etching technics on the surface of insulating barrier 23 formed corresponding with the position of the first electrode 21.So, in a subsequent step, the pattern being formed at second electrode 25 on insulating barrier 23 surface can cover this via hole 24, and is electrically connected with the pattern of the first electrode 21 by via hole 24.So, not only can realize the electrical connection of the second electrode 25 and metal level 22, and can by increasing the contact resistance that metal level 22 and the contact area of the first electrode 21 and the contact area of the first electrode 21 and the second electrode 25 reduce to be electrically connected to each other between rete.Thus promote the electric conductivity of array base palte.In addition, owing to having the first electrode 21 between the second electrode 25 and substrate 10, the offset of via hole 24 is reduced, thus there is the probability of fracture in the second electrode 25 reducing Hole chamfering place, and then improve the quality of array base palte.
The embodiment of the present invention provides a kind of array base palte, comprises any one via hole as above.Have, with the via hole that previous embodiment of the present invention provides, there is identical beneficial effect, because via hole has been described in detail in the aforementioned embodiment, repeat no more herein.
The embodiment of the present invention provides array base palte.This array base palte comprises via hole, and this via hole is included on substrate and is formed with the first electrode and metal level successively; Metal level is electrically connected with the first electrode.Be formed with insulating barrier and the second electrode on the surface of metal level successively, the surface of insulating barrier is provided with via hole, the second electrode is electrically connected with metal level by this via hole.So, the degree of depth of via hole can be reduced, and increase the contact area between the rete that is electrically connected to each other, thus improve the problem of the bigger than normal and open circuit of contact resistance in via hole technology.
Further, as shown in Figure 6, above-mentioned array base palte also comprises:
Grid 120 is formed on the surface of transparency carrier 11.
Gate insulator 13, active layer 14 is formed successively on the surface of grid 120.
The first electrode 21 is formed on the surface of gate insulator 13.
Source class 122 and drain electrode 121 is formed in the surperficial both sides of active layer 14.
Passivation layer 15 is coated with at the substrate surface being formed with above-mentioned pattern.
On the surface of passivation layer 15, the position of corresponding first electrode 21 and drain electrode 121 is provided with via hole 24.
The second electrode 25 is formed at the substrate surface being provided with via hole 24.
Wherein, via hole 24 is half via hole, and the second electrode 25 121 to be electrically connected with draining by this half via hole and the first electrode 21.
On above-mentioned array base palte, the TFT drain electrode 121 at half via hole place is between the first electrode 21 and the second electrode 25, and the TFT be exposed in half via hole drains 121 by above-mentioned electrodes surrounding.So, while raising aperture opening ratio, the contact area between TFT drain electrode 121 and first, second electrode can be increased, thus reduces the contact resistance between the rete that is electrically connected to each other, promote the electric conductivity of TFT.In addition, because the drain electrode 121 at this half via hole place exists offset, when the angle of gradient at this offset place is comparatively large or because when chamfering appears in etching technics, can cause the second electrode 25 being positioned at drain electrode 121 angle of gradient or chamfering place that open circuit occurs, at this moment drain 121 and so can be connected with the second electrode 25 by the first electrode 21, thus ensure that TFT can normally work.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (9)
1. a manufacture method for via hole, is characterized in that, comprising:
Substrate is formed by patterning processes the pattern of the first electrode for reducing hole depth;
Metal level is formed at the substrate surface being formed with described first electrode pattern; Described metal level is electrically connected with the pattern of described first electrode;
Insulating barrier is formed at the substrate surface being formed with described metal level;
Via hole is formed by patterning processes on the surface of described insulating barrier;
Formed the pattern of the second electrode by patterning processes at the substrate surface being formed with described via hole;
Wherein, described second electrode is electrically connected with described metal level by described via hole.
2. manufacture method according to claim 1, is characterized in that, describedly forms the method for via hole on the surface of described insulating barrier by patterning processes and also comprises:
On the surface of described insulating barrier, the position of corresponding described metal level and described first electrode forms via hole by patterning processes;
Wherein, the second electrode is electrically connected with described first electrode and described metal level by described via hole.
3. manufacture method according to claim 1, is characterized in that, describedly forms the method for via hole on the surface of described insulating barrier by patterning processes and also comprises:
On the surface of described insulating barrier, the position of corresponding described first electrode forms described via hole by patterning processes;
Wherein, described second electrode is electrically connected with described first electrode by described via hole.
4. manufacture method according to any one of claim 1-3, is characterized in that, described first electrode and described second electrode are transparent conductive material.
5. manufacture method according to claim 4, is characterized in that, described first electrode layer comprises at least one rete.
6. a via hole, is characterized in that, comprising:
Substrate is formed the first electrode for reducing hole depth;
Metal level is formed on the surface of described first electrode; Described metal level is electrically connected with described first electrode;
Insulating barrier is formed on the surface of described metal level;
Via hole is formed on the surface of described insulating barrier;
The second electrode is formed on the surface of described via hole;
Wherein, the position of described via hole is corresponding with the position of described metal level and described first electrode; Described second electrode is electrically connected with described first electrode and described metal level by described via hole.
7. a via hole, is characterized in that, comprising:
Substrate is formed the first electrode for reducing hole depth;
Metal level is formed on the surface of described first electrode; Described metal level is electrically connected with described first electrode;
Insulating barrier is formed on the surface of described metal level;
Via hole is formed on the surface of described insulating barrier;
The second electrode is formed on the surface of described via hole;
Wherein, the position of described via hole is corresponding with the position of described first electrode; Described second electrode is electrically connected with described first electrode by described via hole.
8. an array base palte, is characterized in that, comprising: the via hole as described in any one of claim 6-7.
9. array base palte according to claim 8, is characterized in that, also comprises:
Grid is formed on the surface of transparency carrier;
Gate insulator, active layer is formed successively on the surface of described grid;
The first electrode is formed on the surface of described gate insulator;
Source electrode and drain electrode is formed in the surperficial both sides of described active layer;
Passivation layer is coated with at the substrate surface being formed with above-mentioned pattern;
On the surface of described passivation layer, the position of corresponding described first electrode and described drain electrode is provided with described via hole;
The second electrode is formed at the substrate surface being provided with described via hole;
Wherein, described second electrode is electrically connected with described first electrode and described drain electrode by described via hole.
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| CN104678671B (en) | 2015-03-30 | 2018-12-21 | 京东方科技集团股份有限公司 | Display base plate and its manufacturing method and display device |
| CN106782241A (en) * | 2016-12-29 | 2017-05-31 | 武汉华星光电技术有限公司 | A kind of test circuit and preparation method for array base palte |
| CN108535928A (en) * | 2018-04-13 | 2018-09-14 | 京东方科技集团股份有限公司 | A kind of array substrate and preparation method thereof, display panel and display device |
| CN109752891B (en) * | 2019-01-14 | 2021-03-19 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display panel |
| CN111564453B (en) * | 2020-05-14 | 2023-10-31 | Tcl华星光电技术有限公司 | Backboard, manufacturing method of backboard and backlight module |
| CN112038374B (en) * | 2020-09-02 | 2023-04-18 | 昆山国显光电有限公司 | Display panel and display device |
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| CN101794049A (en) * | 2009-01-30 | 2010-08-04 | 三星移动显示器株式会社 | Panel display apparatus and manufacture method thereof |
| CN103021940A (en) * | 2012-12-12 | 2013-04-03 | 京东方科技集团股份有限公司 | Array substrate, manufacture method of array substrate and display device |
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| CN202033562U (en) * | 2011-04-29 | 2011-11-09 | 京东方科技集团股份有限公司 | Liquid crystal display array base plate |
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| CN101794049A (en) * | 2009-01-30 | 2010-08-04 | 三星移动显示器株式会社 | Panel display apparatus and manufacture method thereof |
| CN103021940A (en) * | 2012-12-12 | 2013-04-03 | 京东方科技集团股份有限公司 | Array substrate, manufacture method of array substrate and display device |
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