CN113097295A - Thin film transistor, preparation method thereof and display panel - Google Patents
Thin film transistor, preparation method thereof and display panel Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Abstract
The embodiment of the invention discloses a thin film transistor, a preparation method thereof and a display panel. The preparation method of the thin film transistor comprises the following steps: sequentially manufacturing a grid electrode insulating layer and a grid electrode on a semiconductor layer, and conducting the semiconductor layer to form a channel region and a source drain region on the semiconductor layer; the size of the gate insulating layer is larger than the designed length of the channel region along the length direction of the channel region; and manufacturing source and drain electrodes at positions corresponding to the source and drain regions to form the thin film transistor. Compared with the prior art, the embodiment of the invention increases the channel length of the thin film transistor, reduces the error of the channel length and improves the yield of the thin film transistor.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a thin film transistor, a preparation method of the thin film transistor and a display panel.
Background
With the continuous development of display technology, the application range of display panels is wider and wider, and the requirements of people on the display panels are higher and higher. Among them, a Thin Film Transistor (TFT) is an important device in a display panel, and plays an important role in the operation performance and the display effect of the display panel. However, the existing method for manufacturing a thin film transistor has a defect that the actual channel length of the manufactured thin film transistor is smaller than the designed length and the error is large. Therefore, the yield of the conventional thin film transistor is low.
Disclosure of Invention
The embodiment of the invention provides a thin film transistor, a preparation method thereof and a display panel, which are used for increasing the channel length of the thin film transistor, reducing the error of the channel length and improving the yield of the thin film transistor.
In order to achieve the technical purpose, the embodiment of the invention provides the following technical scheme:
a method for preparing a thin film transistor comprises the following steps:
sequentially manufacturing a grid electrode insulating layer and a grid electrode on a semiconductor layer, and conducting the semiconductor layer to form a channel region and a source drain region on the semiconductor layer; the size of the gate insulating layer is larger than the designed length of the channel region along the length direction of the channel region;
and manufacturing source and drain electrodes at positions corresponding to the source and drain regions to form the thin film transistor.
Further, a mask process is adopted to simultaneously manufacture the grid insulation layer and the grid;
preferably, the sequentially fabricating a gate insulating layer and a gate electrode on the semiconductor layer includes:
sequentially manufacturing a grid insulating material layer and a grid material layer on the semiconductor layer;
patterning the grid electrode insulating material layer and the grid electrode material layer by adopting a half-tone mask process to form the grid electrode insulating layer and the grid electrode; and the size of the gate insulating layer is larger than that of the gate along the length direction of the channel region.
Further, the halftone mask plate adopted in the halftone mask process comprises at least three light transmittances which respectively correspond to different positions of the photoresist layer;
preferably, the gate insulating material layer comprises an insulating main region, an insulating tail region and an etched region; the insulation tail region is positioned at the outer side of the insulation main region, and the etching region is positioned at the outer side of the insulation tail region; the half-tone mask plate comprises a first light transmission area, a second light transmission area and a third light transmission area, wherein the light transmission rates of the first light transmission area, the second light transmission area and the third light transmission area are sequentially reduced;
the photoresist layer is positive photoresist, the third light-transmitting area corresponds to the insulating main area, the second light-transmitting area corresponds to the insulating tail area, and the first light-transmitting area corresponds to the etching area;
or, the photoresist layer is a negative photoresist, the first light-transmitting area corresponds to the insulating main area, the second light-transmitting area corresponds to the insulating tail area, and the third light-transmitting area corresponds to the etching area.
Further, the patterning the gate insulating material layer and the gate material layer by using a half-tone mask process includes:
forming a photoresist layer on the gate material layer;
exposing and developing the photoresist layer by using the halftone mask plate, and removing a part, corresponding to the source drain region, on the photoresist layer;
performing first etching on the grid electrode insulating material layer and the grid electrode material layer to form a grid electrode insulating layer;
removing the photoresist layer corresponding to the part except the grid electrode;
performing second etching on the grid material layer to form the grid;
preferably, the method further comprises, while or after the first etching is performed on the gate insulating material layer and the gate material layer, the step of: and forming a conductor in the semiconductor layer.
Further, two mask processes are adopted to respectively manufacture the grid insulation layer and the grid;
preferably, the sequentially fabricating a gate insulating layer and a gate electrode on the semiconductor layer includes:
manufacturing a grid insulating material layer on the semiconductor layer, and patterning the grid insulating material layer to form a grid insulating layer;
and manufacturing a grid electrode material layer on the grid electrode insulating layer, and patterning the grid electrode material layer to form the grid electrode.
Further, the material of the semiconductor layer includes an oxide; and forming the gate insulating layer by adopting a dry etching process, and performing conductor formation on the semiconductor layer by utilizing the dry etching process.
Correspondingly, the invention also provides a thin film transistor, which can be prepared by adopting the thin film transistor preparation method provided by any embodiment of the invention, and the thin film transistor comprises:
the semiconductor layer comprises a channel region and a source drain region, and a source drain electrode is arranged at a position corresponding to the source drain region;
the grid electrode insulating layer is positioned on one side of the semiconductor layer close to the source drain electrode;
the grid is positioned on one side of the grid insulating layer close to the source drain electrode; wherein a dimension of the gate insulating layer in a length direction of the channel region is greater than a design length of the channel region.
Further, the gate insulating layer includes an insulating main region and an insulating tail region; along the length direction of the channel region, the size of the insulating main region is equal to that of the gate, and the insulating tail regions are located on two sides of the insulating main region;
preferably, along the length direction of the channel region, the length range of the gate is 3um to 5um, and the length range of the insulation tail region at one side of the gate is 500nm to 800 nm;
preferably, the insulated tail region is symmetrical about the insulated main region.
Further, the material of the semiconductor layer includes an oxide;
preferably, the oxide comprises at least one of indium gallium zinc oxide, indium tin zinc oxide or indium zinc oxide.
Accordingly, the present invention also provides a display panel including the thin film transistor according to any of the embodiments of the present invention.
The embodiment of the invention provides a preparation method of a thin film transistor, and the size of a grid insulation layer is set to be larger than the design length of a channel region in the preparation process of the thin film transistor, so that buffer is formed under the semiconductor diffusion effect of a semiconductor layer. Compared with the prior art, on one hand, the embodiment of the invention is beneficial to increasing the actual length of the channel region, so that the actual length of the channel region is closer to the designed length, the yield of the thin film transistor is improved, and the characteristic uniformity of the thin film transistor is improved. On the other hand, an LDD structure is formed corresponding to a portion where a buffer is formed by a semiconductor diffusion action. Therefore, the transition region is moved outwards by setting the size of the gate insulating layer to be larger than the design length of the channel region, so that the length of the channel region is more approximate to the design length, and the yield and the characteristic uniformity of the thin film transistor are improved; and the transition region also plays the role of LDD, which is beneficial to reducing the leakage current of the thin film transistor and improving the performance of the thin film transistor.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a thin film transistor according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the structure formed in each step of the fabrication method of FIG. 1;
fig. 3 is a schematic top view of a conventional tft;
FIG. 4 is a schematic cross-sectional view taken along line A-A in FIG. 3;
fig. 5 is a schematic flow chart of another method for manufacturing a thin film transistor according to an embodiment of the present invention;
FIGS. 6-7 are schematic views of structures formed in various steps of the fabrication method of FIG. 5;
fig. 8 is a schematic flow chart illustrating a method for manufacturing a thin film transistor according to another embodiment of the present invention;
FIGS. 9-10 are schematic views of structures formed in various steps of the fabrication method of FIG. 8;
fig. 11 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a schematic flow chart of a method for manufacturing a thin film transistor according to an embodiment of the present invention, and fig. 2 is a schematic structural diagram formed in each step of the manufacturing method of fig. 1. Referring to fig. 1 and 2, the method for manufacturing the thin film transistor includes the steps of:
s110, sequentially manufacturing a gate insulating layer 30 and a gate 40 on the semiconductor layer 20, and conducting the semiconductor layer 20 to form a channel region 201 and a source-drain region 203 on the semiconductor layer 20; wherein, along the length direction X of the channel region 201, the size of the gate insulation layer 30 is larger than the designed length of the channel region 201.
The semiconductor layer 20 includes a channel region 201 and source and drain regions 203, and the source and drain regions 203 are located on two sides of the channel region along a length direction X of the channel region 201. The longitudinal direction X of the channel region 201 refers to a current flowing direction when the thin film transistor is turned on. The length direction X of the channel region 201 is explained with reference to fig. 3 and fig. 4, in which fig. 3 is a schematic top view of a conventional thin film transistor, and fig. 4 is a schematic cross-sectional view along a-a in fig. 3. Referring to fig. 3 and 4, the thin film transistor includes a buffer layer 10, a semiconductor layer 20, a gate insulating layer 30, a gate electrode 40, a dielectric layer 50, and source and drain electrodes 60, which are stacked. Since the thin film transistor has a symmetrical structure, the source and drain electrodes are not distinguished in the embodiment of the present invention, the source and drain electrode 60 on the left side may be set as the source electrode, the source and drain electrode 60 on the right side may be set as the drain electrode, or the source and drain electrode 60 on the right side may be set as the source electrode, and the source and drain electrode 60 on the left side may be set as the drain electrode. When the thin film transistor is turned on, carriers in the channel region 201 flow between the source and the drain to form a current, and thus a flow path direction of the current is defined as a longitudinal direction X of the channel region 201.
With continued reference to fig. 3 and 4, source drain regions 203 overlap source drain electrodes 60. In the prior art, in order to ensure that the source/drain electrode 60 and the semiconductor layer 20 can be in good contact, reduce the overlap impedance between the source/drain electrode 60 and the semiconductor layer 20, and improve the performance of the thin film transistor, it is necessary to make a conductor to the source/drain region 203 of the semiconductor layer 20, that is, to reduce the resistance of the source/drain region 203. However, the inventors have found that the conventional conductor process has a defect, resulting in that the actual length of the channel region 201 of the semiconductor layer 20 is smaller than the design length 204. This problem occurs because the gate insulating layer 30 blocks the semiconductor layer 20 in a semiconductor process of the semiconductor layer 20 (for example, the semiconductor layer 20 is made into a semiconductor by plasma, and the plasma destroys some chemical bonds in the semiconductor layer 20 to make the semiconductor into a semiconductor). The gate insulating layer 30 is sized to be equal to the designed length 204 of the channel region in the prior art, and ideally, the channel region 201 is formed at a corresponding portion of the gate insulating layer 30. However, due to the diffusion effect of the plasma, the plasma diffuses from the source-drain region 203 to the channel region 201, and the boundary region between the source-drain region 203 and the channel region 201 is made conductive, thereby forming a transition region between the source-drain region 203 and the channel region 201. Due to the transition region, the actual channel length of source drain region 201 is less than design length 204. The length of the channel region 201 in the thin film transistor determines the characteristics of the thin film transistor, and when the length of the channel region 201 is too small compared to the design length 204, the thin film transistor cannot accurately establish an electric field, thereby causing poor performance and low yield.
In view of this, with reference to fig. 2, in the method for manufacturing a thin film transistor according to the embodiment of the present invention, the size of the gate insulating layer 30 is set to be larger than the design length 204 of the channel region 201, which is beneficial to increase the actual length of the channel region 201, so that the actual length of the channel region 201 is closer to the design length 204 (fig. 2 shows that the actual length of the channel region 201 is equal to the design length 204), thereby being beneficial to improving the yield of the thin film transistor and improving the uniformity of the characteristics of the thin film transistor.
Specifically, the gate insulating layer 30 includes an insulating main region 301 and an insulating tail region 302, the insulating main region 301 has a size equal to the designed length 204 of the channel region in the length direction X of the channel region, and the insulating tail regions 302 are located on both sides of the insulating main region 301. Correspondingly, the semiconductor layer 20 includes a channel region 201, a transition region 202, and source and drain regions 203, in the length direction X of the channel region, the transition region 202 is located on two sides of the channel region 201, and the source and drain regions 203 are located on two sides of the transition region 202.
Wherein, the channel region 201 is of semiconductor nature and has the largest resistance; the transition region 202 is partially conductive, the resistance of the transition region 202 being less than the resistance of the channel region 201; source drain region 203 is fully conductive and the resistance of source drain region 203 is minimal. The transition region 202 is equivalent to a Lightly Doped Drain (LDD) structure, and is equivalent to a large resistor connected in series between the source/Drain electrode 60 and the channel region 201, so as to reduce the horizontal electric field of the channel region 201, reduce the hot carriers generated by impact ionization caused by electric field acceleration, and effectively suppress the leakage current. Therefore, for the prior art, the transition region between the channel region 201 and the source/drain region 203 can only play a bad role in reducing the length of the channel region 201, however, through the ingenious design of the inventor, in the embodiment of the present invention, the transition region 202 can be moved outwards, which is not only beneficial to making the length of the channel region 201 closer to the design length 204, but also beneficial to reducing the leakage current of the thin film transistor because the transition region 202 also plays a role of LDD.
Where the transition region 202 is formed by diffusion of a plasma, the length of the transition region 202 may be considered constant under the same process conditions. It can be understood that the longer the length of the insulation tail region 302, the better the shielding effect on the channel region 201, and the longer the length of the channel region 201 formed in the conductor process; conversely, the shorter the length of the isolation tail region 302, the shorter the length of the channel region 201 formed during the conductimerization process. Optimally, the isolation tail region 302 is positioned such that the length of the channel region 201 is equal to the design length 204. In practical applications, the length of the insulation tail region 302 may be set as desired to make the actual length of the channel region 201 closer to the design length 204.
Optionally, the designed length 204 of the channel region 201 is in a range of 3um-5um, and the length of the insulation tail region 302 at one side of the insulation main region 301 along the length direction X of the channel region 201 is in a range of 500nm-800 nm. Since the tfts are symmetrically disposed, the insulating tail regions 302 are symmetrically disposed on two sides of the insulating main region 301, where the length of the insulating tail region 302 on one side is set to be 500nm-800nm, and correspondingly, the length of the insulating tail region 302 on the other side is also set to be 500nm-800 nm. This arrangement facilitates the length of the transition region 202 being equal to the length of the insulating tail region 302, thereby facilitating the length of the insulating main region 301 being equal to the length of the channel region 201 and facilitating the length of the channel region 201 being equal to the design length 204.
With continued reference to fig. 2, optionally, the size of the gate 40 is equal to the designed length 204 of the channel region 201, i.e. the size of the gate 40 is equal to the size of the insulating main region 301. Then, the size of the gate insulating layer 30 is larger than the size of the gate electrode 40, and the area of the gate insulating layer 30 larger than the size of the gate electrode 40 is the insulating tail region 302. Optionally, along the length direction X of the channel region 201, the length of the gate 40 ranges from 3um to 5um, and the length of the insulation tail region 302 at one side of the gate 40 ranges from 500nm to 800 nm.
And S120, manufacturing a source-drain electrode 60 at a position corresponding to the source-drain region 203 to form the thin film transistor.
The source/drain electrodes 60 are made of a conductive material, such as molybdenum or titanium aluminum titanium. Optionally, a dielectric layer 50 is further disposed between the source-drain electrode 60 and the semiconductor layer 20, a via hole is disposed at a position of the dielectric layer 50 corresponding to the source-drain region 203, and the source-drain electrode 60 is connected to the source-drain region 203 through the via hole. Illustratively, the manufacturing steps of the source-drain electrode 60 include: firstly, manufacturing a dielectric layer 50 on a source drain region 203 and a grid 40, and patterning the dielectric layer 50 to form a through hole exposing the source drain region 203; then, an electrode material layer is formed on the dielectric layer 50 (for example, by a deposition process), and the electrode material layer is overlapped with the source and drain regions 203 through the via holes; finally, the electrode material layer is patterned to form source and drain electrodes 60.
In summary, the embodiments of the present invention provide a method for manufacturing a thin film transistor, in which the size of the gate insulating layer 30 is set to be larger than the designed length 204 of the channel region during the manufacturing process of the thin film transistor, so as to be beneficial to forming a buffer for the semiconductor diffusion of the semiconductor layer 20. Compared with the prior art, on one hand, the embodiment of the invention is beneficial to increasing the actual length of the channel region 201, so that the actual length of the channel region 201 is closer to the design length 204, the yield of the thin film transistor is improved, and the characteristic uniformity of the thin film transistor is improved. On the other hand, the LDD structure is formed corresponding to a portion where the buffer is formed by the conductor diffusion action of the semiconductor layer 20. Therefore, in the embodiment of the present invention, the size of the gate insulating layer 30 is set to be larger than the design length 204 of the channel region, so that the transition region 202 is moved outward, which is not only beneficial to making the length of the channel region 201 closer to the design length 204, but also beneficial to improving the yield and the characteristic uniformity of the thin film transistor; the transition region 202 also functions as an LDD, which is beneficial to reducing the leakage current of the tft and improving the performance of the tft.
On the basis of the above embodiments, there are various methods for preparing the gate insulating layer 30 and the gate electrode 40, and for example, one mask process may be used to simultaneously prepare the gate insulating layer 30 and the gate electrode 40, or two mask processes may be used to respectively prepare the gate insulating layer 30 and the gate electrode 40. The following is a specific description of the method for manufacturing the gate insulating layer 30 and the gate electrode 40, but the present invention is not limited thereto.
Fig. 5 is a schematic flow chart of another manufacturing method of a thin film transistor according to an embodiment of the present invention, and fig. 6 to 7 are schematic structural diagrams formed in each step of the manufacturing method of fig. 5. Referring to fig. 5 to 7, in an embodiment of the present invention, a method for manufacturing a thin film transistor optionally includes the steps of:
s210, sequentially forming a gate insulating material layer 31 and a gate material layer 41 on the semiconductor layer 20.
The material of the gate insulating material layer 31 includes at least one of silicon oxide (SiOx) and silicon nitride (SiNx). Illustratively, a deposition process may be employed to fabricate a layer of gate insulating material 31 on the semiconductor layer 20.
The material of the gate material layer 41 may include at least one of aluminum (Al), an aluminum alloy, silver (Ag), a silver alloy, copper (Cu), a copper alloy, molybdenum (Mo), a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), or titanium (Ti). Illustratively, a deposition process may be employed to fabricate the gate material layer 41 on the gate insulating material layer 31.
S220, patterning the gate insulating material layer 31 and the gate material layer 41 by adopting a half-tone mask process to form a gate insulating layer 30 and a gate 40; wherein, along the length direction of the channel region 201, the size of the gate insulating layer 30 is larger than that of the gate electrode 40.
Wherein the halftone mask process is one of the photolithography processes, for example, S220 may be divided into the following steps:
and S221, forming a photoresist layer 70 on the gate material layer 41.
Wherein the material of the photoresist layer 70 may include a positive photoresist for which the exposed portions are soluble in a developing solution and the unexposed portions are insoluble in a developing solution or a negative photoresist; for a negative photoresist, the exposed portions are insoluble in the developer and the unexposed portions are soluble in the developer. The material of the photoresist layer 70 is generally organic, and the photoresist layer 70 may be coated by static coating or dynamic coating, for example.
S222, exposing the photoresist layer 70 with the halftone mask 80.
Among them, the half-tone mask 80 enables the photoresist layer 70 to be formed in different thicknesses in one exposure and development process, unlike a general mask. The half-tone mask 80 includes at least three kinds of light transmittances corresponding to different positions of the photoresist layer 70, respectively. If the photoresist layer 70 is a positive photoresist, the higher the light transmittance, the thinner the corresponding photoresist layer 70 after development is; the lower the light transmittance, the thicker the corresponding photoresist layer 70 after development. If the photoresist layer 70 is a negative photoresist, the lower the light transmittance, the thinner the corresponding thickness of the developed photoresist layer 70; the higher the light transmission, the thicker the corresponding developed photoresist layer 70.
Illustratively, the gate insulating material layer 31 includes an insulating main region 311, an insulating tail region 312, and an etched region 313; the insulated tail region 312 is located outside the insulated main region 311, and the etched region 313 is located outside the insulated tail region 312. For example, the insulating tail region 312 is symmetrical with respect to the insulating main region 311, and the etched region 313 is symmetrical with respect to the insulating main region 311, so that the manufactured thin film transistor is a symmetrical thin film transistor.
The corresponding relationship between each region of the gate insulating material layer 31 and each film layer is as follows:
in the first aspect, the regions of the gate insulating material layer 31 have a correspondence relationship with the semiconductor layer 20: the insulating main region 311 corresponds to the channel region 201 of the semiconductor layer 20, the insulating tail region 312 corresponds to the transition region 202 of the semiconductor layer 20, and the etched region 313 corresponds to the source/drain region 203 of the semiconductor layer 20.
In the second aspect, if the length of the channel region 201 of the semiconductor layer 20 is equal to the size of the gate 40, the regions of the gate insulating material layer 31 correspond to the gate material layer 41: the insulated main region 311 corresponds to the gate region of the gate material layer 41, and the insulated tail region 312 and the etched region 313 correspond to the etched region of the gate material layer 41.
In the third aspect, there is a correspondence relationship between each region of the gate insulating material layer 31 and the photoresist layer 70: the insulating main region 311 corresponds to a reserved region of the photoresist layer 70, the insulating tail region 312 corresponds to a semi-reserved region of the photoresist layer 70, and the etched region 313 corresponds to a non-reserved region of the photoresist layer 70.
In the fourth aspect, there is a correspondence relationship between each region of the gate insulating material layer 31 and the halftone mask 80: the half-tone mask plate 80 includes a first light-transmitting region 801, a second light-transmitting region 802, and a third light-transmitting region 803, in which light transmittances are sequentially reduced. Taking the photoresist layer 70 as a positive photoresist, the third light-transmitting region 803 corresponds to the insulated main region 311 of the gate insulating material layer 31 (i.e., the remaining region of the photoresist layer 70), the second light-transmitting region 802 corresponds to the insulated tail region 312 of the gate insulating material layer 31 (i.e., the semi-remaining region of the photoresist layer 70), and the first light-transmitting region 801 corresponds to the etched region 313 of the gate insulating material layer 31 (i.e., the non-remaining region of the photoresist layer 70). In this way, in a subsequent etching process, the gate insulating layer 31 may leave the insulating main region 311 and the insulating tail region 312, and the portion of the gate material layer 41 located on the insulating main region 311.
And S223, developing the exposed photoresist layer 70, and removing the part, corresponding to the source drain region 203, on the photoresist layer 70.
The portion of the photoresist layer 70 corresponding to the source/drain region 203 is an unreserved region of the photoresist layer 70, and the unreserved region of the photoresist layer 70 is removed to expose the etched region 313 of the gate insulating material layer 31. Specifically, since the transmittance of the first light transmission region 801 on the half-tone mask plate 80 is the highest, for example, it may be full transmission, the portion of the photoresist layer 70 corresponding to the first light transmission region 801 (the source drain region 203 of the semiconductor layer 20) is completely removed; since the second light-transmitting region 802 has a lower transmittance than the first light-transmitting region 801, for example, it can be semi-transparent, the photoresist layer 70 is partially removed from the portion corresponding to the second light-transmitting region 802; since the third light-transmitting region 803 has the lowest transmittance and may be opaque, for example, the photoresist layer 70 has the thickest thickness corresponding to the third light-transmitting region 803. That is, the photoresist layer 70 after exposure takes a staircase shape.
S224, performing a first etching on the gate insulating material layer 31 and the gate material layer 41 to form a gate insulating layer 30.
Here, since the semi-reserved region and the reserved region remain in the photoresist layer 70 in S223, the non-reserved region is removed, so that a portion of the gate insulating material layer 31 corresponding to the etched region 313 is exposed. Therefore, under the etching process, the gate insulating material layer 31 and the gate material layer 41 are all etched in the portions corresponding to the non-remaining regions, exposing the source and drain regions 203 of the semiconductor layer 20. The portion of the gate insulating material layer that is not etched at this time is the gate insulating layer 30, and the portion of the gate material layer 41 that is not etched continues to be etched in the subsequent steps. Illustratively, the process of etching the gate insulating material layer and the gate material layer 41 is a dry etching process or a wet etching process. The gate insulating layer 30 has a size equal to that of the gate material layer 41 after the first etching along the length direction of the channel region 201.
Optionally, the material of the semiconductor layer 20 includes an Oxide, and optionally, the Oxide includes at least one of Indium Gallium Zinc Oxide (IGZO), Indium Tin Zinc Oxide (ITZO), or Indium Zinc Oxide (IZO). The process of conducting the oxide semiconductor layer 20 may be to utilize plasma etching gas to destroy some chemical bonds inside the oxide, so as to release oxygen in the oxide, increase the content of oxygen vacancies, and achieve the conduction of the oxide. Accordingly, the gate insulating material layer 31 and the gate material layer 41 may be etched using a dry etching process. And the dry etching process adopts plasma etching gas, so that while the gate insulating material layer 31 and the gate material layer 41 are etched for the first time by plasma, the etching region 313 of the gate insulating material layer 31 is corroded by the plasma, the unreserved region of the gate material layer 41 is corroded by the plasma, and the source and drain regions 203 of the semiconductor layer 20 are treated by the plasma to reduce the resistance, so that the semiconductor layer 20 is made into a conductor, namely the semiconductor layer 20 is made into a conductor by the dry etching process. By the arrangement, the source and drain regions 203 of the semiconductor are not required to be independently transformed into a conductor by adopting an additional step, so that the preparation process of the thin film transistor is facilitated to be simplified.
And S225, removing the part of the photoresist layer 70, which is outside the corresponding gate region.
Wherein, the thickness of the photoresist layer 70 corresponding to the portion outside the gate region (i.e. the half-reserved region of the photoresist layer 70) is thinner, and the photoresist layer 70 of the portion is easier to remove. Illustratively, the removal process of the photoresist layer 70 may be an ashing process, a wet removal process, or the like. After removing the half-remaining regions of the photoresist layer 70, the remaining regions of the photoresist layer 70 remain such that the portions of the gate material layer 41 outside the corresponding gate regions are exposed.
And S226, carrying out second etching on the gate material layer 41 to form the gate 40.
Illustratively, the process of performing the second etching on the gate material layer 41 is dry etching, wet etching, or the like. Unlike the first etching, the second etching only needs to etch the gate material layer 41, and the gate insulating layer 30 is not etched. For example, the second etching may be performed with a different etchant, a different concentration of etchant, a different etching time, etc. to etch the gate material layer 41 while leaving the gate insulating layer 30.
And S227, removing the residual photoresist layer 70.
Illustratively, the removal process of the photoresist layer 70 may be an ashing process, a wet removal or grinding process, or the like.
The step of patterning the gate insulating material layer 31 and the gate material layer 41 using the halftone mask process to form the gate insulating layer 30 and the gate electrode 40 is realized by S221 to S227.
And S230, manufacturing a source drain electrode 60 at a position corresponding to the source drain region 203 to form the thin film transistor.
Through the steps, the embodiment of the invention realizes that the gate insulating layer 30 and the gate 40 are simultaneously manufactured by adopting one mask process, so that the number of the mask processes is favorably reduced, the process is simplified, the equipment investment cost is reduced, and the unit price of a thin film transistor or a display panel comprising the thin film transistor is favorably reduced.
In the above embodiments, the photoresist layer 70 is exemplarily illustrated as a positive photoresist, and is not limited to the invention. In other embodiments, the photoresist layer 70 may be a negative photoresist, such that the first transparent region 801 of the mask corresponds to the insulating main region 301, the second transparent region 802 corresponds to the insulating tail region 302, and the third transparent region 803 corresponds to the etching region.
It should be noted that, in the above embodiments, the semiconductor layer 20 is made into a conductor while the gate insulating material layer 31 and the gate material layer 41 are etched for the first time, which is exemplarily shown, and the present invention is not limited thereto. In other embodiments, it may be further provided that after the first etching of the gate insulating material layer 31 and the gate material layer 41, the semiconductor layer 20 is further subjected to a conductor.
On the basis of the above embodiments, before the gate insulating material layer 31 is formed on the semiconductor layer 20, optionally, the method further includes: a semiconductor material layer is formed on the buffer layer 10, and the semiconductor material layer is patterned to form a semiconductor layer 20.
Wherein the material of the semiconductor material layer comprises an oxide, optionally, the oxide comprises at least one of indium gallium zinc oxide, indium tin zinc oxide or indium zinc oxide. The semiconductor material layer can be doped with P-type ions, so that a P-type thin film transistor is formed; the semiconductor material layer can also be doped with N-type ions, thereby forming an N-type thin film transistor. Illustratively, the semiconductor material layer may be etched using a photolithography process or a laser etching process to form the semiconductor layer 20.
Alternatively, the buffer layer 10 is formed on the substrate, and then the preparation method provided by the embodiment of the invention is performed to form the oxide thin film transistor. Alternatively, a buffer layer 10 (a first buffer layer) is fabricated on a substrate, and then the fabrication method provided by the embodiment of the present invention is performed; then, a second buffer layer is formed continuously, a preparation method of a Low Temperature Polysilicon (LTPS) thin film transistor is performed, and finally a Low Temperature Polysilicon Oxide (LTPO) thin film transistor is formed. Alternatively, a preparation method of the low temperature polysilicon thin film transistor is performed, then the buffer layer 10 is fabricated on the low temperature polysilicon thin film transistor, and then the preparation method provided by the embodiment of the invention is performed to form the low temperature polysilicon oxide thin film transistor. In the formed LTPO thin film transistor, the source and drain electrodes of the low-temperature polysilicon thin film transistor and the source and drain electrodes of the oxide thin film transistor can be arranged on the same layer or different layers, and can be set according to requirements in practical application.
Fig. 8 is a schematic flow chart of a manufacturing method of another thin film transistor according to an embodiment of the present invention, and fig. 9-10 are schematic structural diagrams formed in various steps of the manufacturing method of fig. 8. Referring to fig. 8 to 10, in an embodiment of the present invention, a method for manufacturing a thin film transistor optionally includes the steps of:
s310, a gate insulating material layer 31 is formed on the semiconductor layer 20, and the gate insulating material layer 31 is patterned to form a gate insulating layer 30.
The process of patterning the gate insulating material layer 31 may be, for example, a photolithography process, and for example, S310 may be divided into the following steps:
s311, a gate insulating material layer 31 is formed on the semiconductor layer 20.
S312, a first photoresist layer 71 is formed on the gate insulating material layer 31.
S313, the first photoresist layer 71 is exposed by using the first mask 81.
The first mask 81 used for exposing the first photoresist layer 71 does not need to use a halftone mask, and a common mask can be used. The first mask plate 81 includes a light-transmitting region 811 and a non-light-transmitting region 813, and taking the first photoresist layer 71 as a positive photoresist as an example, the non-light-transmitting region 813 corresponds to a remaining region of the first photoresist layer 71 (i.e., the insulating main region 311 and the insulating tail region 312 of the gate insulating material layer 31), and the light-transmitting region 811 corresponds to a non-remaining region of the first photoresist layer 71 (i.e., the etched region 313 of the gate insulating material layer 31). Thus, the gate insulating layer may remain the insulating main region 311 and the insulating tail region 312 in a subsequent etching process.
And S314, developing the exposed first photoresist layer 71, and removing a part, corresponding to the source drain region 203, of the first photoresist layer 71.
The portion of the first photoresist layer 71 corresponding to the source/drain region 203 is an unreserved region of the first photoresist layer 71, and the unreserved region of the first photoresist layer 71 is removed to expose the etched region 313 of the gate insulating material layer 31.
And S315, etching the gate insulating material layer 31 to form the gate insulating layer 30.
The etching process may be, for example, a dry etching process or a wet etching process, and since the etching region 313 of the gate insulating material layer 31 is exposed, the etching region 313 of the gate insulating material layer 31 is etched to expose the source/drain region 203 of the semiconductor layer 20. Alternatively, the material of the semiconductor layer 20 includes an oxide, and the gate insulating material layer 31 is etched using a dry etching process (plasma etching gas). As described above, the gate insulating material layer 31 is etched by plasma, and the source-drain regions 203 of the semiconductor layer 20 are plasma-treated to reduce resistance and become a conductor, that is, the semiconductor layer 20 is made a conductor by a dry etching process. By the arrangement, the source and drain regions 203 of the semiconductor are not required to be independently transformed into a conductor by adopting an additional step, so that the preparation process of the thin film transistor is facilitated to be simplified.
And S316, removing the residual first photoresist layer 71.
The step of patterning the gate insulating material layer 31 to form the gate insulating layer 30 is realized through S311-S316.
S320, forming a gate material layer 41 on the gate insulating layer 30, and patterning the gate material layer 41 to form a gate 40.
The process of patterning the gate material layer 41 may be, for example, a photolithography process, and for example, S320 may be divided into the following steps:
s321, a gate material layer 41 is formed on the gate insulating layer 30.
And S322, forming a second photoresist layer 72 on the gate material layer 41.
S323, the second photoresist layer 72 is exposed by using the second mask 82.
Similarly to the first mask, the second mask 82 used for exposing the second photoresist layer 72 does not need to use the halftone mask 80, and may be a common mask. The second mask 82 includes a light-transmitting region 821 and a non-light-transmitting region 823, and taking the second photoresist layer 72 as a positive photoresist as an example, the non-light-transmitting region 823 corresponds to a remaining region of the second photoresist layer 72 (i.e., the gate region of the gate material layer 41 or the insulating main region 311 of the gate insulating material layer 31), and the light-transmitting region 821 corresponds to a non-remaining region of the first photoresist layer 71 (i.e., the etched region of the gate material layer 41 or the etched region 313 and the insulating tail region 312 of the gate insulating material layer 31). In this way, the gate 40 may remain the gate region during subsequent etching processes.
S324, developing the exposed second photoresist layer 72, etching the gate material layer 41, and removing the remaining second photoresist layer 72.
Here, the forming of the gate electrode 40 includes steps of development and etching, similar to the step of forming the gate insulating layer 30. Specifically, after the exposed second photoresist layer 72 is developed, the portions of the second photoresist layer 72 corresponding to the source/drain regions 203 and the transition region 202 may be removed. The portions of the second photoresist layer 72 corresponding to the source/drain regions 203 and the transition region 202 are non-reserved regions of the second photoresist layer 72, and the non-reserved regions of the second photoresist layer 72 are removed to expose the etched regions of the gate material layer 41.
The gate insulating layer 30 may be formed by etching the gate insulating material layer 31. The etching process may be, for example, a dry etching process or a wet etching process, and since the etched region of the gate material layer 41 is exposed, the etched region of the gate material layer 41 is etched to expose the source and drain regions 203 of the semiconductor layer 20 and the insulation tail region 302 of the gate insulation layer 30. Alternatively, the material of the semiconductor layer 20 includes an oxide, and the gate material layer 41 is etched using a dry etching process (plasma etching gas). As described above, while the gate material layer 41 is etched by plasma, the source-drain regions 203 of the semiconductor layer 20 are plasma-treated to reduce resistance, thereby making the semiconductor layer 20 a conductor, that is, a conductor by a dry etching process. By the arrangement, the source and drain regions 203 of the semiconductor are not required to be independently transformed into a conductor by adopting an additional step, so that the preparation process of the thin film transistor is facilitated to be simplified.
The step of patterning the gate material layer 41 to form the gate electrode 40 is realized through S321-S324.
And S330, manufacturing a source drain electrode 60 at a position corresponding to the source drain region 203 to form the thin film transistor.
Through the steps, the embodiment of the invention realizes that the gate insulating layer 30 and the gate 40 are respectively manufactured by adopting two mask processes, so that a halftone mask plate is not needed, and the process difficulty is favorably reduced.
In the above embodiments, a Top Gate Top Contact (TG-TC) structure is exemplified, and the present invention is not limited thereto. In other thin film transistor structures, the method for manufacturing a thin film transistor provided in many embodiments of the present invention may be applied as long as there is a problem with ion diffusion in the process of making a semiconductor into a semiconductor.
The embodiment of the invention also provides a thin film transistor which can be manufactured by adopting the manufacturing method of the thin film transistor provided by any embodiment of the invention. Fig. 11 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention. Referring to fig. 11, the thin film transistor includes: a buffer layer 10, a semiconductor layer 20, a gate insulating layer 30, and a gate electrode 40. The semiconductor layer 20 includes a channel region 201 and source-drain regions 203, and source-drain electrodes 60 are provided at positions corresponding to the source-drain regions 203. The gate insulating layer 30 is positioned on one side of the semiconductor layer 20 close to the source-drain electrode 60; the gate electrode 40 is located on a side of the gate insulating layer 30 adjacent to the source-drain electrode 60. The dimension of the gate insulating layer 30 along the length direction X of the channel region 201 is greater than the designed length of the channel region 201.
Illustratively, a transition region 202 is located between the channel region 201 and the source and drain regions 203 of the semiconductor layer 20, and in the length direction X of the channel region, the transition region 202 is located on both sides of the channel region 201, and the source and drain regions 203 are located on both sides of the transition region 202. The gate insulating layer 30 includes an insulating main region 301 and an insulating tail region 302, the size of the insulating main region 301 is equal to the designed length of the channel region in the length direction X of the channel region, and the insulating tail regions 302 are located on both sides of the insulating main region 301.
The embodiment of the invention is beneficial to forming buffer for the conductor diffusion action of the semiconductor layer 20 by setting the size of the gate insulating layer 30 to be larger than the design length of the channel region. Compared with the prior art, on one hand, the embodiment of the invention is beneficial to increasing the actual length of the channel region 201, so that the actual length of the channel region 201 is closer to the designed length, the yield of the thin film transistor is improved, and the characteristic uniformity of the thin film transistor is improved. On the other hand, the LDD structure is formed corresponding to a portion where the buffer is formed by the conductor diffusion action of the semiconductor layer 20. Therefore, in the embodiment of the present invention, the transition region 202 can be moved outward by setting the size of the gate insulating layer 30 to be larger than the design length of the channel region, which is not only beneficial to making the length of the channel region 201 closer to the design length 204, but also beneficial to improving the yield and the characteristic uniformity of the thin film transistor; the transition region 202 also functions as an LDD, which is beneficial to reducing the leakage current of the tft and improving the performance of the tft.
With continued reference to fig. 11, in an embodiment of the present invention, optionally, along the length direction X of the channel region 201, the size of the insulating main region 301 is equal to the size of the gate 40, that is, the size of the channel region 301 is equal to the size of the gate 40, and the insulating tail regions 302 are located at two sides of the insulating main region 301. Optionally, along the length direction X of the channel region 201, the length of the gate 40 ranges from 3um to 5um, and the length of the insulation tail region 302 at one side of the gate 40 ranges from 500nm to 800 nm. This arrangement facilitates the length of the transition region 202 being equal to the length of the insulating tail region 302, thereby facilitating the length of the insulating main region 301 being equal to the length of the channel region 201, and facilitating the length of the channel region 201 being equal to the design length.
With continued reference to fig. 11, in one embodiment of the present invention, the insulating tail region 302 is optionally symmetric about the insulating main region 301 to facilitate formation of a structurally symmetric thin film transistor.
On the basis of the above embodiments, optionally, the material of the semiconductor layer 20 includes an oxide. Optionally, the Oxide includes at least one of Indium Gallium Zinc Oxide (IGZO), Indium Tin Zinc Oxide (ITZO), or Indium Zinc Oxide (IZO). The oxide semiconductor can use plasma etching gas to destroy some chemical bonds in the oxide, so that oxygen in the oxide is released, the oxygen vacancy content is increased, and the oxide is made into a conductor. And the gate insulating layer 30 and the gate electrode 40 may be etched using a dry etching process using plasma etching gas. As described above, the gate insulating layer 30 and the gate electrode 40 are formed by plasma etching, and the source-drain regions 203 of the semiconductor layer 20 are plasma-treated to reduce resistance and become a conductor, that is, the semiconductor layer 20 is made a conductor by a dry etching process. By the arrangement, the source and drain regions 203 of the semiconductor are not required to be independently transformed into a conductor by adopting an additional step, so that the preparation process of the thin film transistor is facilitated to be simplified.
On the basis of the above embodiments, optionally, the thin film transistor is an N-type thin film transistor or a P-type thin film transistor.
On the basis of the above embodiments, optionally, the thin film transistor is an oxide thin film transistor. Alternatively, the thin film transistor is a Low Temperature Polycrystalline Oxide (LTPO) thin film transistor. The LTPO thin film transistor comprises an oxide thin film transistor and a low-temperature polycrystalline silicon thin film transistor, wherein the oxide thin film transistor is positioned on the low-temperature polycrystalline silicon thin film transistor, or the low-temperature polycrystalline silicon thin film transistor is positioned on the oxide thin film transistor. In the formed LTPO thin film transistor, the source and drain electrodes of the low-temperature polysilicon thin film transistor and the source and drain electrodes of the oxide thin film transistor can be arranged on the same layer or different layers, and can be set according to requirements in practical application.
An embodiment of the present invention further provides a Display panel, where the Display panel may be at least one of an Organic Light-Emitting Diode (OLED) Display panel, a Liquid Crystal Display (LCD) panel, a Micro Light-Emitting Diode (Micro LED) Display panel, a Quantum Dot Light-Emitting Diode (QLED) Display panel, or an electrophoretic Display (EPD) panel. The display panel includes the thin film transistor provided in any embodiment of the present invention, and the thin film transistor may be disposed in a circuit of an array substrate of the display panel, where the circuit may be a multiplexing circuit, a pixel circuit, a shift register circuit, or the like. The thin film transistor may function as a switching transistor or a driving transistor in a circuit of the display panel. Since the display panel provided by the embodiment of the present invention includes the thin film transistor provided by any embodiment of the present invention, the principle and the effect thereof are similar, and detailed description thereof is omitted.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A method for manufacturing a thin film transistor includes:
sequentially manufacturing a grid electrode insulating layer and a grid electrode on a semiconductor layer, and conducting the semiconductor layer to form a channel region and a source drain region on the semiconductor layer; the size of the gate insulating layer is larger than the designed length of the channel region along the length direction of the channel region;
and manufacturing source and drain electrodes at positions corresponding to the source and drain regions to form the thin film transistor.
2. The method for manufacturing a thin film transistor according to claim 1, wherein the gate insulating layer and the gate electrode are simultaneously formed by a mask process;
preferably, the sequentially fabricating a gate insulating layer and a gate electrode on the semiconductor layer includes:
sequentially manufacturing a grid insulating material layer and a grid material layer on the semiconductor layer;
patterning the grid electrode insulating material layer and the grid electrode material layer by adopting a half-tone mask process to form the grid electrode insulating layer and the grid electrode; and the size of the gate insulating layer is larger than that of the gate along the length direction of the channel region.
3. The method for manufacturing a thin film transistor according to claim 2, wherein the halftone mask used in the halftone mask process comprises at least three light transmittances, and the at least three light transmittances respectively correspond to different positions of the photoresist layer;
preferably, the gate insulating material layer comprises an insulating main region, an insulating tail region and an etched region; the insulation tail region is positioned at the outer side of the insulation main region, and the etching region is positioned at the outer side of the insulation tail region; the half-tone mask plate comprises a first light transmission area, a second light transmission area and a third light transmission area, wherein the light transmission rates of the first light transmission area, the second light transmission area and the third light transmission area are sequentially reduced;
the photoresist layer is positive photoresist, the third light-transmitting area corresponds to the insulating main area, the second light-transmitting area corresponds to the insulating tail area, and the first light-transmitting area corresponds to the etching area;
or, the photoresist layer is a negative photoresist, the first light-transmitting area corresponds to the insulating main area, the second light-transmitting area corresponds to the insulating tail area, and the third light-transmitting area corresponds to the etching area.
4. The method for manufacturing a thin film transistor according to claim 2, wherein the patterning the gate insulating material layer and the gate material layer by using a halftone mask process comprises:
forming a photoresist layer on the gate material layer;
exposing and developing the photoresist layer by using the halftone mask plate, and removing a part, corresponding to the source drain region, on the photoresist layer;
performing first etching on the grid electrode insulating material layer and the grid electrode material layer to form a grid electrode insulating layer;
removing the photoresist layer corresponding to the part except the grid electrode;
performing second etching on the grid material layer to form the grid;
preferably, the method further comprises, while or after the first etching is performed on the gate insulating material layer and the gate material layer, the step of: and forming a conductor in the semiconductor layer.
5. The method for manufacturing a thin film transistor according to claim 1, wherein the gate insulating layer and the gate electrode are respectively formed by two mask processes;
preferably, the sequentially fabricating a gate insulating layer and a gate electrode on the semiconductor layer includes:
manufacturing a grid insulating material layer on the semiconductor layer, and patterning the grid insulating material layer to form a grid insulating layer;
and manufacturing a grid electrode material layer on the grid electrode insulating layer, and patterning the grid electrode material layer to form the grid electrode.
6. The method for manufacturing a thin film transistor according to any one of claims 1 to 5, wherein a material of the semiconductor layer includes an oxide; and forming the gate insulating layer by adopting a dry etching process, and performing conductor formation on the semiconductor layer by utilizing the dry etching process.
7. A thin film transistor, comprising:
the semiconductor layer comprises a channel region and a source drain region, and a source drain electrode is arranged at a position corresponding to the source drain region;
the grid electrode insulating layer is positioned on one side of the semiconductor layer close to the source drain electrode;
the grid is positioned on one side of the grid insulating layer close to the source drain electrode; wherein a dimension of the gate insulating layer in a length direction of the channel region is greater than a design length of the channel region.
8. The thin film transistor according to claim 7, wherein the gate insulating layer includes an insulating main region and an insulating tail region; along the length direction of the channel region, the size of the insulating main region is equal to that of the gate, and the insulating tail regions are located on two sides of the insulating main region;
preferably, along the length direction of the channel region, the length range of the gate is 3um to 5um, and the length range of the insulation tail region at one side of the gate is 500nm to 800 nm;
preferably, the insulated tail region is symmetrical about the insulated main region.
9. The thin film transistor according to claim 7, wherein a material of the semiconductor layer comprises an oxide;
preferably, the oxide comprises at least one of indium gallium zinc oxide, indium tin zinc oxide or indium zinc oxide.
10. A display panel comprising the thin film transistor according to any one of claims 7 to 9.
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| WO2023108429A1 (en) * | 2021-12-14 | 2023-06-22 | 京东方科技集团股份有限公司 | Manufacturing method for thin film transistor, array substrate, and display panel |
| CN116544245A (en) * | 2023-06-29 | 2023-08-04 | 绵阳惠科光电科技有限公司 | Array substrate, preparation method thereof and display panel |
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